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In this paper, circuit level analysis of the high frequency and low noise performance of an RF CMOS device with L\mathrm{ eff}= 36 nm is performed using various layout schemes. By using the modeling methodology of interconnect metals and vias, it is found that the gate parasitic capacitance from the interconnects mainly affects the degradation of high frequency and noise performance. An optimized layout scheme is proposed to reduce the gate parasitic resistance and capacitance in this paper, and the proposed layout exhibits improved RF behaviors for fT , f\mathrm {\mathrm {MAX}} , and NFmin at 26 GHz up to ~13%, ~24%, and ~18% compared with the reference layout scheme, respectively. [ABSTRACT FROM PUBLISHER]

Increased drain-induced barrier lowering caused by drain electric flux (or field) passing through the buried-oxide (BOX) layer in silicon-on-insulator (SoI) MOSFETs has been reported as an inherent disadvantage of SoI technology. Part I of this paper discussed derivation of the relationships between coordinates in MOSFETs and potential/stream function in preparation for the modeling of electric flux using conformal mapping in subthreshold regions of ground plane SoI MOSFETs and the validity of the approach was checked via device simulation. Here, in Part II of this paper, we discussed the model’s derivation based on these relationships. The dependences of the flux amount on BOX thickness, BOX permittivity, SoI thickness, and gate length estimated using the model were also discussed in comparison with those estimated via device simulation. [ABSTRACT FROM PUBLISHER]

This paper reports the performance of midwave infrared (MWIR) electron-injection avalanche photodiode (e-APD) fabricated using graded bandgap HgCdTe epilayers. Carrier transport in the e-APD is dominated by drift transport due to the built-in electric field associated with gradient in the bandgap. Carriers encounter fewer collision events before entering the multiplication region as the dead space effect is reduced. On-set of generation and multiplication processes is controlledmore effectively. High gain indicates a reduced in-elastic scattering by phonon-emission due to gradient. Quantum efficiency above 80% is achieved in merely 2–3- \mu \textm -thick absorbing layer because of more efficient collection of the photogenerated carriers. Lower generation volume is beneficial in terms of low dark current. The generation is confined in the vicinity of themultiplication region. Generated carriers are readily evacuated from the absorber region under the built-in electric field. An order of magnitude improvement over the state-of-the art performance in MWIR e-APD is achieved by introducing a controlled energy bandgap gradient in the HgCdTe epilayers. [ABSTRACT FROM AUTHOR]

The base series resistance is an important parameter for bipolar junction transistors and heterojunction bipolar transistor (HBTs). Although many methods have been proposed for its experimental determination, their results vary significantly. In this paper, the most widely used methods are reviewed and applied to SiGe HBTs of different technologies and generations including different device types, i.e. high-speed and high-voltage SiGe HBTs. The accuracy of the methods is evaluated by applying them to a sophisticated physics-based compact model, allowing to clearly detect and explain the causes for the observed inaccuracies or failures. The methods are then also applied to experimental data. In both cases, a large variety of device sizes have been investigated. This paper and its results provide insight into each method’s accuracy, its application limits with respect to a technology, device size, and operating range as well as its requirements in terms of equipment and extraction effort. [ABSTRACT FROM PUBLISHER]

Silicon-on-insulator (SoI) technology has been reported as a technique to improve electrical characteristics over those of bulk MOSFETs. However, this approach results in the disadvantage of increased drain-induced barrier lowering (DIBL) due to drain electric flux (or field) passing through the buried oxide (BOX) layer. Against such a background, the development of a method to easily estimate the amount of this electric flux is expected to support the prediction of BOX-related DIBL. This paper involved the investigation of a model-derived analytically using conformal mapping techniques to represent the amount of flux in subthreshold regions of ground-plane SoI MOSFETs. To create the model, this paper was divided into two parts. In Part I, as preparation for model development, the relationships between coordinates in MOSFETs and potential/stream function were derived using conformal mapping, and related validity was verified. In Part II, the model’s development was considered based on these relationships, and its validity was also verified. [ABSTRACT FROM PUBLISHER]

Light-emitting diode (LED) luminous flux and efficacy as a function of temperature and current is important to qualify and optimize the design of an LED system. In this paper, the extension of light output equation was used to estimate luminous flux and efficacy of low-power surface-mounted device LED. The photometric and thermal test reports of LED parameters at a certain range of injection current and ambient temperature were obtained by the combination of T3ster and TeraLED systems. The luminous flux and efficacy as a function of injection current and ambient temperature were predicted. The agreement between the experimental and theoretical results validates the extended equation used in this paper. The optimized operating conditions of LED under test are determined. [ABSTRACT FROM PUBLISHER]

The proposed chord-fractal pattern has a significant impact on IC capacitor, increasing the capacitance within a limited chip area. To reduce the device area, this paper presents a modified fractal algorithm. This proposed algorithm uses various initiators to perform chord iteration on the unit cell. The iteration procedure automatically generates an area-saving fractal layout of IC capacitor. To verify the proposed algorithm, an area-saving device of chord-fractal is fabricated using UMC 0.18- \mu \textm CMOS technology. [ABSTRACT FROM PUBLISHER]

In this paper, we show a validation of our compact model for negative capacitance FET (NCFET) presented in Part I. The model is thoroughly validated with the TCAD simulations with respect to ferroelectric thickness scaling and temperature effects. Interestingly, we find that an NCFET with PZT ferroelectric of a large thickness provides a negative output differential resistance in addition to an expected high ON current and a sub-60 mV/decade subthreshold swing. The model is also tested for the Gummel symmetry and its transient capabilities are highlighted through a ring oscillator circuit simulation. [ABSTRACT FROM PUBLISHER]

Recent developments to microwave tube simulator suite (MTSS) are reported in this paper. The MTSS is a full-featured tightly integrated software package for microwave tube analysis and design. It includes a commercial grade user interface and three physics simulators. The electron optics simulator is a finite-element (FE) 2-D and 3-D electrostatic steady-state beam trajectory code that has been used to design beam optics, including electron gun and collector. High-frequency circuit simulator is a full 3-D FE computational electromagnetic code that aims to get the accurate electromagnetic wave character spreading in high-frequency structures, such as dispersion, coupling impedance, and attenuation. Beam wave interaction simulator is a large-signal simulation code for helix traveling wave tubes (TWTs), coupled-cavity TWTs, and klystrons. The first version of MTSS was released in 2007, and all of these three physics simulators and user interface are improved and updated over the past six years. This paper reports on some significant advances to MTSS; new Ribbon style user interface, a lot of component modeling templates, more abundant postprocessing features, parallel version, full 64-bit version, more physics, and computation methods improvement. [ABSTRACT FROM AUTHOR]

In this paper, we propose a methodology to evaluate the potential of submicrometer organic thin-film transistors (OTFTs) with nanoimprinted gate and self-aligned source and drain contacts. In the first step, the dedicated static model we previously reported is updated to account for the subthreshold regime and is used to simulate a zero- $V_{{\rm GS}}$ inverter (one of the most basic unipolar logic gate). Based on the extracted noise margins, two methodologies were studied to assess the potential of this technology in terms of p-logic digital circuits. The first one is De Vusser's V_{T} -based method that we adapted to our OTFT model. The second one relies on statistical modeling and takes into account the actual worst case scenario for an inverter in terms of noise margins. It better represents the experimental distribution because of specific corner models. The different analysis studied in this paper shows that these OTFTs, in the current state of the technology, are still not ready for complex digital circuits as the throughput is expected to be quite low. In addition, the proposed methodology and related interpretation are technology-independent therefore this analysis may serve as a basis to characterize unipolar-logic printed electronics and can be further extended to complementary-logic circuits. [ABSTRACT FROM PUBLISHER]

Tunnel field-effect transistor (TFET) devices are gaining attention because of good scalability and they have very low leakage current. However, they suffer from low ON-current and high threshold voltage. In this paper, we present III-V heterojunctionless TFET (H-JLTFET) for circuit applications. This paper elaborates on interfacing of III-V with group IV semiconductors for heterojunction. Implementing heterojunction and bandgap engineering, we found that devices have significantly improved performance with very high speed even at very low operating voltage. As there is no doping junction present, future scaling could be feasible along with much higher speed of charge carriers than in silicon. GaAs:Si, Si:Si0.3Ge0.7, Si:InAs, and GaAs:Ge, H-JLTFET interface for 20-nm gate length (EOT=2~nm) and dielectric, HfO2 at VGS=1~\rm V and temperature of 300 K have I{ON} of 0.02–12.5 mA/\mum, I{ON}/I{OFF} of 10^5\--10^12, and subthreshold swing (average) of 16–74 mV/decade. [ABSTRACT FROM AUTHOR]

We investigate high current stress mechanisms and demonstrate how Auger hot carriers can damage both oxide interfaces and polysilicon regions of the emitter and base. A new current gain enhancement (CGE) effect is proposed, which involves hot-carrier damage to the polysilicon emitter and extrinsic base leading to the degradation of the associated minority carrier mobilities. We demonstrate the different CGE mechanisms in SiGe HBTs under forward and inverse modes of operation. The hot-carrier damage responsible for CGE at high injection is explored in depth with the help of TCAD simulations. Evidence for this effect has been gathered with good statistical significance from various stress conditions, various technologies, complimentary (NPN + PNP) devices, and from dc and ac measurements. The new polysilicon degradation mechanism proposed in this paper has been generalized and is important for accurately modeling the changes in base resistance and current gain ( $\beta$ ) at high injection, where circuits are typically biased to extract maximum device performance. [ABSTRACT FROM AUTHOR]

In this paper, a simplified Eulerian nonlinear beam-wave interaction (BWI) theory of a helix traveling-wave tube (TWT) is developed. Derived from this model, analytic solutions are first obtained by the method of successive approximation. Then, the linear analytic solution of group delay distortion (GDD) is obtained. Subsequently, the mechanism of group delay is studied. It is found that the main mechanism of GDD is the propagation time difference between the wave group and electron beam throughout the BWI region. Furthermore, a series of group delay suppression schemes is discussed by using the mechanism. Finally, the Eulerian formation and the suppression schemes are validated by an in-house code based on the Lagrangian theory. Results show that the analytic solutions of Eulerian model and GDD agree well with the Lagrangian theory in small-signal region. In addition, the suppression schemes are applied to a high-efficiency Ku-band space TWT. The GDD is greatly reduced by approximately 50% with a slightly drop of output power. [ABSTRACT FROM AUTHOR]

This paper analyzes both experimentally and by simulation the impact of traps on the transfer characteristics of tunnel-FETs (TFETs). The interface trap density in vertical heterojunction TFETs is varied by annealing in hydrogen or deuterium ambient. We show that a high-interface trap density (\sim 2\times 10^12/cm^2) results in a peak current in the device transfer characteristic at low-gate bias due to surface generation of carriers. The passivation of interface traps to state-of-the-art densities near 1-2\times 10^11/cm^2 reduces this peak, but improves only marginally the overall subthreshold swing, indicating that the trap-assisted tunneling responsible for the swing degradation is mainly occurring through bulk traps in these devices. [ABSTRACT FROM PUBLISHER]

As technology scales down, IC design is becoming more difficult due to the increase in process variations, which translates into a dispersion of circuit parameter values thus degrading manufacturing yield. Regular layouts are recommended to reduce variability with the cost of area overhead with respect to conventional layouts. The aim of this paper is to measure the impact of variability in two implementations of the same circuit in a commercial 40-nm technology: 1) a regular layout style and a compact and 2) nonregular layout. Experimental results show a 60% reduction in variability with a cost of 60% area overhead. [ABSTRACT FROM PUBLISHER]

A novel vertical field plate (VFP) lateral device with ultralow specific on-resistance (RON,sp) is proposed in this paper. The VFP surrounded by oxide is inserted in the bulk of the drift region. Compared to the surface local depletion of the conventional lateral field plate (LFP), the depletion layer of the VFP expands to the bulk of the drift region, which enhances the bulk electric field. Therefore, ultralow RON,sp is realized in the VFP device due to high drift-region doping (Nd) and short cell pitch. An analytical FP model is developed to describe the behavior of the VFP, in which the breakdown voltage (BV) and Nd are found to be proportional to the FP factor k. Then the uniform-doped VFP laterally diffused MOSs and the step-doped VFP laterally diffused MOS are proposed. The optimized device exhibits a BV of 945 V and a RON,sp of 34 m\Omega\cdotcm^2 which are superior to those of similar devices and the silicon limit. [ABSTRACT FROM PUBLISHER]

In this paper, a novel method of extracting tunneling resistance from a tunneling FET (TFET) is proposed and verified by small-signal analysis based on radio-frequency (RF) data. Unlike the approaches made in the small-signal equivalent circuits of conventional MOSFETs, the on -state total channel resistance can be separately analyzed into tunneling and inversion layer resistances. In this paper, an RF method is suggested and proven to be more practical and realistic since it calls for neither a set of complicated measurements with a number of geometric splits of devices under test nor device simulations with imaginary material parameters to identify the tunneling resistance of a TFET device as usually employed in DC methods. To verify the extracted tunneling resistances, their dependences on gate length and bias conditions have been investigated in silicon nanowire TFETs. Furthermore, related small-signal parameters are analyzed with the highlight of the relation between tunneling resistance and inversion layer length. It is confirmed by Y -parameters that models with extracted tunneling resistances are valid in the RF domain and under various geometric and operation conditions up to 300 GHz. [ABSTRACT FROM AUTHOR]

An extension of the detailed balance method for the thermoradiative conversion, including the transport properties, is presented in this paper. This formalism is applied to the study of the most important properties (maximum output power, the efficiency at which that power is delivered, and the maximum efficiency) of thermoradiative cells (TRCs) with bandgap values between 0.2 and 0.7 eV. The calculations demonstrate that the consideration of the electronic transport in the calculation of the properties of the TRCs leads to predict better working properties for them. [ABSTRACT FROM PUBLISHER]

A new theory of lateral double-diffused MOS (LDMOS) by the folded-silicon substrate field-effect (FSLDMOS) with the complete 3-D REduced SURface Field (RESURF) is proposed in this paper for the first time. The analytical model for the relationship between the breakdown voltage (BV) and the specific ON-resistance ( R\mathrm\scriptscriptstyle ON,sp ) of FSLDMOS is obtained, which breaks the limit relationship of the superjunction (SJ) LDMOS by applying three kinds of methods, including the additional electric-field modulation effect, majority carrier accumulation, and increasing the effective conduction paths simultaneously. In the analytical model, the influence of the structural parameters of the folded-drift and electric field modulation coefficients is considered. Besides, the optimal doping concentration of the folded-drift region for FSLDMOS is derived, which can give guidance for the dose of the folded-drift region. The results indicate that a new analytical expression for the relationship between the BV and R\mathrm{\scriptscriptstyle ON,\text {sp}} is obtained, which breaks the limit relationship of the SJ LDMOS by the complete 3-D RESURF. All analytical results are well verified by the simulation results conducted by ISE-TCAD, showing the validity of the presented model. [ABSTRACT FROM PUBLISHER]

The physical mechanisms that regulate carrier transport in polycrystalline chalcogenides, such as \Ge2\Sb2\Te5 (GST), are still debated. Recently, self-induced Joule-heating (SJH) effect has been claimed to be the key factor in explaining the nonlinearity of the I–V characteristics of polycrystalline GST-based phase-change memory (PCM). In this paper, we carefully investigate the SJH occurring in the GST material by analyzing the I–V characteristics of PCM cells at low voltages, i.e., in the memory-cell readout region. To accomplish the study, we use ad hoc fabricated PCM devices allowing an easier evaluation of SJH occurring in the chalcogenide layer. A novel procedure to test the SJH effect is also proposed. A comparison between numerical simulations and compact modeling is discussed as well. Our paper shows that the SJH effect is not sufficient to reproduce the experimental I–V nonlinearity, claiming for new experiments and theoretical investigations. Therefore, this paper can be considered a step forward toward the comprehension of the transport properties of polycrystalline GST, which is a key aspect for robust modeling of PCM devices. [ABSTRACT FROM PUBLISHER]

Continuous models are developed that go beyond the gradual channel approximation and extend MOSFET ${I}$ – ${V}$ characteristics into the velocity saturation region with finite output conductance. Both the ${n} = {1}$ and ${n} = {2}$ models have been employed. It is shown that the standard relation of channel length modulation for constant mobility must be modified for velocity saturation because the drain current is not simply inversely proportional to the channel length. Regional approximations are applied to derive the explicit expressions for the output conductance in the velocity saturation region in terms of basic device parameters. [ABSTRACT FROM AUTHOR]

In this paper, a 3-D fast time-domain nonlinear algorithm (FTDNA-3-D) based on particle-in-cell method for the beam–wave interaction of the sheet beam slow wave structure (SWS) is presented. Calculation equations of the circuit electric field and the space charge electric field are given. Calculation approaches of the energy exchange and the particle mover are displayed. A simplified coupling impedance simulation approach for sheet beam SWS is indicated. The FTDNA-3-D takes the transverse electric field and the focusing magnetic field into consideration. The FTDNA-3-D could reach a high simulation speed. This novel algorithm gives a faster accurate choice for the design of sheet beam traveling-wave tube (TWT). It could be used to enhance the design efficiency of sheet beam TWT. A Ka-band staggered double vane TWT is used to verify the FTDNA-3-D. Simulation results of output power and gain versus frequency from FTDNA-3-D are compared with results from CST particle studio. The results of FTDNA-3-D are in accord with CST particle studio well. [ABSTRACT FROM AUTHOR]

In this paper, we present the influence of eddy currents, skin and proximity effects on high-frequency losses in planar terahertz Schottky diodes. The high-frequency losses, particularly losses due to the spreading resistance, are analyzed as a function of the ohmic-contact mesa geometry for frequencies up to 600 GHz. A combination of 3-D electromagnetic (EM) simulations and parameter extraction based on lumped equivalent circuit is used for the analysis. The extracted low-frequency spreading resistance shows a good agreement with the results from electrostatic simulations and experimental data. By taking into consideration the EM field couplings, the analysis shows that the optimum ohmic-contact mesa thickness is approximately one-skin depth at the operating frequency. It is also shown that, for a typical diode, the onset of eddy current loss starts at \sim200 GHz, and the onset of a mixture of skin and proximity effects occurs around \sim400 GHz. [ABSTRACT FROM AUTHOR]

RF circuit design, thermal analysis, fabrication, and measurement of a continuous wave (CW) high-power sheet beam traveling wave tube (SB-TWT) operating in the Ku-band were demonstrated in this paper. The slow wave structure circuit was constructed by double staggered grating waveguides (DSGWs), and the lossy dielectrics attached in the H-plane were applied to suppress parasitic oscillations. The Particle-in-cell simulation predicted that the CW SB-TWT can provide >20-kW output power in the band range of 16.2–18.5 GHz, with a maximum small signal gain of 38 dB. Microchannel cooling, which has been proved to be an efficient cooling method for microelectronic chip, very large scale integration, and power electronic modules with very high heat flux were introduced to improve the thermal capacity and heat dissipation ability. A thermal analysis of the RF circuit considering attenuated losses and electrons interception was studied in detail. Investigation shows that the RF circuit can operate with maximum $\sim 1$ -kW dielectric loss power (1.5 times of the loss power generated from the saturated output power at center frequency) and a maximum of 7% interception of electrons. Furthermore, an interaction circuit, including 23 DSGWs implanted with BeO–SiC to provide necessary attenuation, was fabricated and cold tested. Vector network analyzer RF measurement shows excellent performance and agrees very well with our prediction. [ABSTRACT FROM AUTHOR]

In this paper, a compact fractional-order equivalent circuit model is developed to characterize three types of metamaterial transmission lines (T-lines): 1) composite right-/left-handed transmission line T-line; 2) split ring resonator T-line; and 3) complimentary split ring resonator T-line, all designed in 65-nm CMOS process at millimeter-wave frequency region. With the consideration of frequency-dependent dispersion loss and nonquasistatic effect, the proposed fractional-order equivalent circuit model can compactly characterize the measured results with good agreement up to 325 GHz. [ABSTRACT FROM AUTHOR]

In this paper, optical power of high-power white-light-emitting diode (LED) devices is evaluated and characterized. A theoretical model for optical power is proposed. The measurements reveal that optical power decreases exponentially with junction temperature and increases linearly with current. The model considers conjunct effect of current and junction temperature on emitted optical power. The proposed theoretical model of optical power will facilitate the optical and thermal performance evaluation of LED devices and will be helpful to device design. With the presented optical power model, heat power can be estimated, because they are complementary to each other. Then, junction temperature of LED device can be predicted with known heat power. In addition, the optical power model can be applied to eliminate chromaticity shift phenomenon of trichromatic-based white-LED devices, simply by monitoring junction temperature and injection current of each chip. Validity of the optical power model has been verified by experimental measurements on two types of commercial LED devices. [ABSTRACT FROM AUTHOR]

In this paper, the main MOSFET parasitic capacitances of planar devices (i.e., bulk, Fully depleted silicon-on-insulator (FDSOI), and planar double gate) are computed using two successive conformal mapping transforms. First, the structure is mapped to the real axis of the complex plane, and then the second transform, deduced directly from the Schwarz–Christoffel theorem, reduces the capacitance to the trivial parallel electrodes case. This second step involves elliptic integrals, which provide a generic expression for all parasitic capacitances. This method is later compared against other models based on conformal mapping. Finally, the results are validated with finite-element method simulations of the inner and outer fringe capacitances in different architectures, including metallic contacts and raised and faceted junctions. [ABSTRACT FROM AUTHOR]

In this paper, we build upon existing techniques to provide a self-consistent, physically based method particularly well suited for quantifying the mobility of solution-processed transition metal-oxide-based thin-film transistors (TFTs). The methodology is presented as a more appropriate alternative to existing square-law techniques whose assumptions are inapplicable to systems exhibiting dispersive transport. To demonstrate its utility in solution-processed electronics, this method was applied to solution-processed SnO2 and ZnO TFTs having various gate dielectrics. In addition, to account for the different operating voltages set by the differences in effective oxide thickness of the dielectric, mobility was evaluated as a function of the transverse electric field, allowing for the direct comparison of mobility independent of the choice of gate dielectric. [ABSTRACT FROM PUBLISHER]

This paper presents an effective current model ( ${I}_{\textsf {eff}}$ ) for a near-threshold voltage (NTV) inverter and two-input NAND/NOR gates. The proposed model is validated by 2-D technology computer-aided design mixed-mode device simulations and HSPICE simulations at two different technology nodes. When compared with our model, the existing nominal supply voltage ${I}_{\textsf {eff}}$ models fail to estimate an inverter/NAND/NOR gate performance in the NTV regime. The proposed model is also validated for process, voltage, and temperature variations. Performance variation due to layout-dependent effects (LDEs) and inverse narrow width effect (INWE) are significant in the NTV regime. Therefore, the model is validated while considering LDEs. We show that due to LDEs and INWE, the value of ${I}_{\textsf {eff}}$ per unit width is a function of the device width and the number of fingers. To account for this effect, a systematic methodology is presented to optimize a circuit performance in the NTV domain. An inverter chain with ${C}_{\textsf {out}}/{C}_{\textsf {in}}=\textsf {2000}$ designed employing our methodology results in 3.2%, 35%, and 30% improvement in the delay, energy per operation, and total transistor width, respectively, as compared with existing methodologies. Similarly, data paths resized using the proposed methodology result in a significant performance improvement when compared with their conventionally designed counterparts. [ABSTRACT FROM AUTHOR]

Several basic thin-film transistor (TFT) models have been developed to describe the electrical characteristics of the device, most of them only considering the fundamental instability effects during static mode operation. However, representing the dynamic behavior is also a major concern for circuit design due to the electrical stress changes over time. Under this scenario, empirical models have been previously demonstrated to reproduce the current instability effects under specific conditions, but they do not consider in detail the phenomena taking place when the TFT is under dynamic electrical stress. In this paper, a new semianalytical model is presented to describe the dynamical behavior of the TFT under stress. This model considers the impact of the negative charge trapped at interfacial states as well as the mobility degradation. To validate the model, we compare the results with experimental measurements from our group, (using CdS TFT), and other semiconductor TFTs (a-Si:H, SnO, IZO, and IGZO) reported by other authors. [ABSTRACT FROM AUTHOR]

In this paper, we investigate the effect of interface trap charges on the variation of heterogeneous gate dielectric junctionless-tunnel FET (JL-TFET) by introducing both donor and acceptor type of localized charges at the semiconductor/insulator interface. In this regard, we have analyzed dc and analog/RF performance parameters for conventional and heterogeneous gate dielectric JL-TFET (HD JL-TFET) in terms of electric field, transfer characteristics, transconductance (gm), output transconductance (gds), parasitic capacitances, device efficiency, cutoff frequency(fT), gain bandwidth product, and transconductance frequency product. Apart from these, linearity distortion parameters are also analyzed in the form of higher order transconductance coefficients (gm1, gm2, gm3), VIP2, VIP3, IMD3, and IIP3. For this, high-K gate dielectric material (HfO2) is used in the case of the HD JL-TFET to improve the performance of the device. All the simulations for both devices have been performed with the help of an ATLAS device simulator. [ABSTRACT FROM AUTHOR]

In this paper, we solved Poisson equation in cylindrical coordinates using approximations to obtain a compact model for the drain current of long-channel junctionless gate-all-around MOSFETs. The resulting model is analytical, explicit, and valid for depletion and accumulation, and consists of simple physically based equations, for better understanding of this device, and also easier implementation and better computation speed as a compact model. The agreement with TCAD simulations is very good. [ABSTRACT FROM PUBLISHER]

This paper presents a 2-D analytic potential model for double-gate (DG) tunnel field effect transistors (TFETs) by solving the 2-D Poisson's equation. From the potential profile, the electric field is derived and then the drain current expression is extracted by analytically integrating the band-to-band tunneling generation rate over the tunneling region. The model well predicts the potential, subthreshold swing (SS), and transfer and output characteristics of DG TFETs. We analyze the dependence of the tunneling current on the device parameters by varying the gate oxide dielectric constant, gate oxide thickness, body thickness, channel length and channel material and also demonstrate its agreement with TCAD simulation results. The SS which describes the switching behavior of TFETs, is derived from the current expression. The comparisons show that the SS of our model well coincides with that of simulations. [ABSTRACT FROM PUBLISHER]

A novel hybrid method, combining the conformal time domain finite integral theorem with the conformal particle-in-cell method, is applied to accurately analyze multipactor phenomena. To successfully apply this hybrid method in microwave devices, we propose a novel power-to-amplitude transformation technique in this paper. The PAT technique is effective and convenient to bridge the gap between the average input power in experiments and electromagnetic field amplitude in numerical simulations. In the end, a numerical example is given to demonstrate the effectiveness and accuracy of the proposed method, whose superiority is also greatly verified by experiments. [ABSTRACT FROM PUBLISHER]

The dc and RF circuit performance of memristor circuits, including transient behavior, is developed by considering current contributions arising from different conduction mechanisms, namely, filament-assisted and bulk tunneling currents and currents flowing through low and high conductivity filaments. The dc circuit model explains the observed I-V hysteresis and most importantly allows scaling and optimization. A transient circuit model of memristive system is developed, based upon the dynamics, incorporating underlying electrochemistry that suggests SET and RESET transitions for a 50-nm TiO2-based memristor take approximately 120 ps to stabilize. A faster READ/WRITE operation would require appropriate conditioning circuitry. RF analysis suggests for a maximum allowable frequency of 7.5 GHz beyond which memristors can no longer be used as RRAM. These values can be pushed to higher limits by increasing the device cross-sectional area or choosing lower permittivity materials. The developed model allows its incorporation in commercial circuit simulators. The derived model is validated by incorporating it in Chua's chaotic circuit. [ABSTRACT FROM PUBLISHER]

We report scaled Ge p-channel FinFETs fabricated on a 300-mm Si wafer using the aspect-ratio-trapping technique. For long-channel devices, a combination of a trap-assisted tunneling and a band-to-band tunneling leakage mechanism is responsible for an elevated bulk current limiting the OFF-state drain current. However, the latter can be mitigated by device design. We report low long-channel subthreshold swing of 76 mV/decade at VDS=-0.5~\rm V, good short-channel effect control, and high transconductance (gm=1.2~mS/\mum at VDS=-1~\rm V and 1.05 mS/\mum at VDS=-0.5~\rm V for LG=70~nm). The Ge FinFET presented in this paper exhibits the highest gm/SSsat at VDD=1~\rm V reported for nonplanar unstrained Ge p-FETs to date. [ABSTRACT FROM AUTHOR]

This paper reports the implementation and wafer-level mechanical and RF testing of three types of MEMS inductor—octagonal, square, and circular; the latter over a temperature range -30^\circC to 150^\circC. The devices were fabricated using a silicon on insulator process with deep reactive ion etching (DRIE) trench on a low-resistivity substrate (\rho=1-10~\Omega~cm) and contains gold bond wire overpass to complete the inductance loop. The three inductors exhibited nominal inductance of 3.36, 12.15, and 3.29 nH with peak quality factor of 9.51, 6.91, and 7.26, respectively, and self-resonance frequency more than 10 GHz. Afterward, the inductors were packaged in a pin grid array package and postpackaging RF testing was carried out to analyze the effect of packaging on RF performance of the inductors. [ABSTRACT FROM AUTHOR]

A 3-D quantum-corrected drift-diffusion (DD) simulation study of three sources of statistical variability, including discrete random dopants (RDs), line-edge roughness (LER), and metal gate workfunction (MGW) was performed for a 14-nm gate length In0.53Ga0.47As FinFET in the subthreshold region using Fermi–Dirac statistics. This paper has been done at both low (0.05 V) and high drain biases (0.6 V). The LER variability is characterized by the root mean square amplitude (\Delta) and correlation length (\Lambda), and the MGW variability by the metal grain size (GS). The RD-induced variation \sigmaVT=6~mV is similar to that observed in Si SoI FinFETs. The LER-induced threshold voltage variations (\sigmaVT<6~mV) are similar to the RD variations when \Delta=1~nm, and smaller than the observed in Si SoI FinFETs (18 mV). For larger \Delta, the LER exhibits \sigmaVT ranging from 11 mV when \Lambda=10~nm and \Delta=2~nm to 19 mV when \Lambda=20~nm and \Delta=3~nm. The MGW variations are the dominant source of variability in the subthreshold characteristics, the \sigmaVT ranges from 106 mV when GS=10~nm to 43 mV when GS=3~nm, which is larger than those observed in equivalent TiN metal-gate Si FinFETs. [ABSTRACT FROM AUTHOR]

The intrinsic properties of vertical InAs nanowire (NW) capacitors are investigated. The band structure is simulated using a Schrödinger–Poisson solver, taking the conduction band nonparabolicity into account. This is combined with a distributed RC model to simulate the current–voltage characteristics. It is found that the influence from the nonparabolicity is substantial for devices with a small nanowire diameter, resulting in an increased carrier concentration, a shift in the threshold voltage, and a higher intrinsic capacitance. These NW capacitors may be a suitable alternative in high frequency applications approaching 100 GHz, while maintaining a quality factor above 100. [ABSTRACT FROM PUBLISHER]

The device physics of nanoscale MOSFETs is related to traditional compact models. Beginning with the virtual source model, a model for nanoscale MOSFETs expressed in traditional form, we show how the Landauer approach gives a clear physical interpretation to the parameters in the model. The analysis shows that transport in the channel is limited by diffusion near the virtual source both below and above threshold, that the current saturation is determined by velocity saturation near the source, not by the maximum velocity in the channel, and that the channel resistance approaches a finite value as the channel length approaches zero. These results help explain why traditional models continue to work well at the nanoscale, even though carrier transport is distinctly different from that at the microscale, and they identify the essential physics that physics-based compact models for nanoscale MOSFETs should comprehend. [ABSTRACT FROM PUBLISHER]

In this paper, we introduce a new compact model of the parasitic resistance of a FinFET with a hexagonal-shaped raised source–drain (S/D) structure. In contrast to previous models that divided the extrinsic S/D region into three parts, we redefined the region boundaries and modeled them as a series connection of accumulation resistance, gradient resistance, bulk resistance, and contact resistance. The newly added bulk resistance model accounts for the highly doped silicon region. We also significantly improved the contact resistance model to reflect the contact area and contact resistivity for better accuracy in the raised S/D region. We validated the accuracy of our model by varying the gate voltage, doping diffusion length, epitaxy silicon height, and contact resistivity, finding the model errors to be within 2% of the 3-D technology CAD device simulation results. [ABSTRACT FROM PUBLISHER]

Amperometric glucose sensors with nanoparticle (NP) electrodes promise fast and highly sensitive detection of glucose concentration in both in vivo and in vitro applications. Unfortunately, the performance of the sensors, as a function of NP geometry and glucose oxidase distribution, is not fully understood, making it difficult to optimize the sensors generally. In this paper, we derive an analytical relationship that explicitly correlates sensor performance to the elementary properties of the electrodes and oxidase. The compact model quantitatively reproduces the redox current associated with NP-based glucose sensors based on carbon nanotube and graphene-petal substrates that have previously been reported in the literature. The model will facilitate predictive design and optimization of NP-based amperometric biosensors that can eventually be integrated into wearable platforms. [ABSTRACT FROM PUBLISHER]

We present an accurate and computationally efficient physics-based compact model to quantitatively analyze negative capacitance FET (NCFET) for real circuit design applications. Our model is based on the Landau–Khalatnikov equation coupled to the standard BSIM6 MOSFET model and implemented in Verilog-A. It includes transient and temperature effects, and accurately captures different aspects of NCFET. A comprehensive quasi-static analysis of NCFET in its different regions of operation is also performed using a simpler loadline approach. We also analyze the impact of ferroelectric and gate oxide thicknesses on the performance gain of NCFET over MOSFET. [ABSTRACT FROM PUBLISHER]

In this paper, a simple and accurate characterization method of the thermal impedance of silicon–germanium (SiGe) heterojunction bipolar transistors (HBTs) is proposed. This method relies on low-frequency S-parameter measurements in the 100 Hz–3 GHz frequency range. It is shown that feedback hybrid parameter h12 provides an image of the thermal impedance in the frequency domain, which is independent of the size of the transistor. Very short thermal time constants involved in SiGe HBTs are accurately determined by this method, as well as the temperature dependence of the thermal impedance in a truly simple way as electrical measurements can be performed in dc conditions either on a wafer or on an attached die. Finally, a nonlinear electrical equivalent circuit model is extracted, which can be readily implemented in computer-aided design software for nonlinear simulation of any SiGe HBT circuit. [ABSTRACT FROM PUBLISHER]

This paper surveys, reviews, and critiques analytic models of MOSFET short-channel effects (SCEs) in subthreshold published over the past four decades. In the first half of this paper, the published models on SCEs are categorized into the following four main groups based on their approach: 1) charging sharing models; 2) empirical expressions; 3) polynomial potential models; and 4) analytic solutions to 2-D Poisson's equation. The strength and weakness of each approach are elaborated in terms of its physical soundness and predictive ability. A key development was the exponential dependence of SCE on channel length (L), SCE \sim\exp(-L/l0), leading to the introduction of scale length (l0). In the second half of this paper, the predictions of each analytic SCE model are examined by generic 2-D numerical simulations. In particular, the merit of each model is judged by its prediction on the scale length (l0) as a function of the thickness and dielectric constant (\kappa) of the gate insulator. Only one model, i.e., the generalized scale length model that treated the silicon and insulator regions as two distinct dielectric regions with shared boundary conditions, correctly predicted the MOSFET scale length under all dielectric constant and thickness conditions. A variation of the generalized scale length model applies to recent multiple-gate MOSFETs near the limit of scaling. [ABSTRACT FROM PUBLISHER]

The cross-bridge Kelvin resistor is a commonly used method for measuring contact resistivity (\rhoc). For low \rhoc, the measurement has to be corrected for systematic error using measurements of contact resistance, semiconductor sheet resistance, and device dimensions. However, it is not straightforward to estimate the propagation of random measurement error in the measured quantities on the extracted \rhoc. In this paper, a method is presented to quantify the effect of random measurement error on the accuracy of \rhoc extraction. This is accomplished by generalized error propagation curves that show the error in \rhoc caused by random measurement errors. Analysis shows that when the intrinsic resistance of the contact is smaller than the semiconductor sheet resistance, it becomes important to consider random error propagation. Comparison of literature data, where \rhoc < \5 \cdot \10^{-8}\ \Omega\cdot \cm^{2} has been reported, shows that care should be taken since, even assuming precise electrical data, a 1% error in the measurement of device dimensions can lead to up to \sim50% error in the estimation of \rhoc. [ABSTRACT FROM PUBLISHER]

This paper provides a closed-form model of the “dark space (DS)” for Ge MOSFETs with high- k gate dielectrics. This model shows accurate dependences on barrier height, surface electric field, and quantization effective mass of the channel and gate dielectric. Our model predicts that the surface DS due to quantum confinement decreases with reverse substrate bias and increasing channel doping. Our model can be also used for devices with a steep retrograde doping profile. This physically accurate model will be crucial to the prediction of the subthreshold swing and electrostatic integrity of advanced Ge devices. [ABSTRACT FROM AUTHOR]

Through-silicon vias (TSVs) in 3-D integrated circuits (ICs), which are used for connecting different active layers, introduce an important source of coupling noise arising from electrical coupling between TSVs and the active regions. This paper, for the first time, presents compact models based on a fully analytical approach for the electrical coupling from a TSV to the active regions for a comprehensive set of 3-D IC substrate technologies including those with and without the high-conductivity buried layer in dual-well bulk CMOS technology in the presence of VDD/VSS rails. The models can be used during design validation of emerging 3-D ICs. The compact physical models are verified against full-wave electromagnetic (EM) simulations. A comparative analysis of the magnitude of the EM coupling noise for different 3-D technology scenarios, including both dual-well bulk CMOS and partially depleted silicon-on-insulator, is also presented. The compact models presented for dual-well bulk CMOS are subsequently employed for estimating the stay-away radius (safe distance) from the center of the TSVs to the active regions to minimize the impact of such coupling noise. In order to highlight the significance of the TSV to active-region EM coupling noise, a comparison is also made with the white noise in the active region and the flicker noise from the interface between the TSV oxide and silicon. [ABSTRACT FROM PUBLISHER]

This paper presents an evaluation of laterally double-diffused MOS transistors in synchronous dc–dc buck converters using a physical-based mixed device and circuit simulation. It is observed that impact ionization of the low-side transistor can be very high after the dead-time drain overshoot voltage point. In addition, heavy ion irradiation degrades power MOSFET performance and may lead to a potential circuit malfunction due to a significant increase in transient current if heavy ions strike the dc–dc buck converter at a critical time during switching. [ABSTRACT FROM PUBLISHER]

The nonstationary simulation of traveling-wave tubes (TWTs) is an important issue in vacuum electronics as it enables the study of a wide range of spurious phenomena. Software based on general time-domain models generally needs huge computational resources and is often useless for design activities. Various nonstationary reduced models of interaction in a TWT have been developed as an alternative to general ones. Among them, the discrete model of excitation of a periodic waveguide appears to be convenient. However, one of the main obstacles to an accurate representation of the slow-wave structure in this model is that reflections at its terminations are hard to control. In this paper, we present a simple method that overcomes this problem, and we apply it to a coupler of a helix TWT. [ABSTRACT FROM PUBLISHER]