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Several miniaturized viscometers, or microviscometers, have been developed exploiting numerous rapid prototyping techniques. Among them, paper microstrips, famously known as microfluidic paper-based analytical devices ( $\mu $ PADs), have become popular due to their cost-efficacy, simple fabrication, fast response, and easily disposable. Many fabrication methods are existing to develop paper microstrips. Herein, an alternative fabrication method is proposed where fused deposition modeling (FDM)-based 3-D printer (3DP) has been employed using polycaprolactone (PCL) filament. F, image processing has been utilized to measure viscosity in such microfluidic domain. Viscosity was calculated by measuring the time taken by the fluid to cover a fixed length between two spots in the microchannel based on the programed and color-coded regions-of-interest. The image processing program was developed considering the change in the gray scale in the virtual region of interests (ROIs) in the microchannel during the fluid flow in the paper microstrips. A 3-D printed handheld platform, containing raspberry pi with on-board camera and display, was developed to execute the image processing and automate the entire work flow. In the proposed device, the accuracy was measured to be >92%.

Various miniaturized viscometers have been developed utilizing several fabrication methods. Among them, microfluidic paper-based analytical devices ( $\mu $ PADs) are becoming popular due to their fabrication ease, cost-effectiveness, and the fact that the flow can be carried out using the embedded capillaries themselves. Mostly, $\mu $ PADs are reported to be fabricated by a solid-ink printer, which has significantly high capital and operational cost. To overcome such drawbacks, a novel rapid prototyping method has been proposed, wherein the formation of the hydrophobic regions was created by polycaprolactone (PCL) filament using a 3-D printer. To leverage this, $\mu $ PAD as a viscometer, velocity, or time between two points with known distances was required, which was carried out by an amperometric approach, established by fabricating the integrated screen-printed electrodes intersecting the microchannel of the $\mu $ PAD. The time measurement was fully automated by a microcontroller, and the relative viscosity was calculated by comparing the time taken by the reference fluid with that of a test fluid to cover a known length. Such integrated, automated, and low-cost paper-based microviscometer was leveraged to measure and analyze the viscosities of various milk variants, which has an accuracy of >92%.

We demonstrate edge electron emission from flexible free-standing graphene paper (GP). The turn-on field is measured at 2.2 V/ $\mu{\rm m}$ , and the maximum emission current density at 3 ${\rm A}/{\rm cm}^{2}$ . The field emission properties of GP can be optimized by adjusting the thickness and annealing temperature. Because it is flexible, it can be shaped into different forms to meet the requirements of specific applications. The electron beam shape can range from a sheet electron beam to a cylindrical (hollow) electron beam.

Since 2017, the IEEE Transactions on Electron Devices (TED) has published a selection of extended versions of papers presented at the Symposia on VLSI Technology and Circuits held in the corresponding years (vol. 64, no. 10; vol. 65, no. 11; vol. 66, no. 12). Since 2018, the papers have been collected in a Special Section of TED titled “Papers from Symposium on VLSI Technology.” This initiative, which was the result of a fruitful cooperation between the Electron Device Society and the VLSI Symposium chairs and committees, has brought to TED a number of carefully selected (by the VLSI TPC first and then through the TED usual review process), high-quality submissions. We have been able to continue this cooperation also in this difficult 2020, and we are therefore happy to announce the publication in the December issue (Vol. 67, No. 12) of a Special Section on papers from the 2020 Symposium, held virtually on June 15–19, 2020. A special thanks to the Guest Editors of the section, Peide Ye, Purdue University (Publication Chair, 2020 VLSI Symposium), and Masaharu Kobayashi, The University of Tokyo, Japan (Publication Co-Chair, 2020 VLSI Symposium).

We report on investigation of the mechanical properties of paper electronics (printed and made out of paper). One key objective of such paper electronics is to achieve ultraflexibility. Therefore, it is important to understand electrical functionality and reliability of paper electronics under various physical (mechanical) deformations. Here, we show the general mechanical properties of the cellulose paper used and its electrical behavior under applied strain, tackling the main effects that need to be identified when building paper-based systems, from product performance and stability perspective. An overview of the stress–strain behavior of silver ink on paper is discussed, and then, we tackle a more specific analysis of the performance variations of paper sensors made with recyclable household materials when exposed to various mechanical conditions of tensile and compressive bending. This paper is important for developing stable wearable sensors for incorporation into Internet of Everything applications.

During the past few years, we have seen an increasing number of submissions of “physics-based simulation only” papers to the IEEE TRANSACTIONS ON ELECTRON DEVICES (T-ED). The popularity of such papers may be explained by the fact that the present widespread technology computer-aided design (TCAD) tools are a significant and welcome boost to creativity in the electronic device community. In fact, TCAD tools allow researchers to explore and optimize device structures without being burdened by technology concerns in terms of availability, cost, and time delay.

Oxide-based thin-film transistors (TFTs) with a lateral in-plane electrode are self-assembled on paper substrates, and the electrical modulation effect of the in-plane electrode is investigated. A SiO2-based solid-electrolyte film with high specific capacitance is used as the gate dielectric, and the operation voltage is reduced to less than 2.0 V. The threshold voltage (Vth) of such paper TFTs is tuned from -0.98 to 0.94 V by different voltage biases on the in-plane electrode. The threshold voltage shift (ΔVth) can be described by ΔVth = -(CG2/CG1)VG2, where CG2 and CG1 are the in-plane electrode and bottom-gate specific capacitance values. High electrical performance with a current on/off ratio of 6 ×105 ~ 106, a subthreshold swing of 0.14 ~ 0.19 V/dec, and a mobility of 8.64 ~ 9.45 cm2/V·s is obtained at different in-plane electrode voltage biases. Such low-voltage paper TFTs are promising for low-cost and portable electronics.

Microporous SiO2 can provide large electric-double-layer (EDL) capacitance and negligible leakage current, owing to lack of electron carrier and limited mobility of mobile ions. The impedance spectroscopy (ionic-conductivity-frequency and capacitance-voltage characteristics) and Fourier-transformed infrared spectroscopy of microporous SiO2 are characterized, which demonstrated that such dielectric is actually a solid-electrolyte dielectric. InGaZnO4 thin-film transistors (TFTs) on paper substrates gated by microporous-SiO2 solid electrolyte are fabricated at room temperature. The large EDL-specific capacitance (1.36 μF/ cm2) results in the paper TFTs operate at a battery-drivable low voltage of 1.0 V. Both depletion-mode (Vth = -0.45 V) and enhancement-mode (Vth = 0.25 V) operations are realized by rationally controlling the oxygen concentration in argon ambient during InGaZnO4 channel deposition. Electrical characteristics with an equivalent field-effect mobility of ~ 21 cm2/V·s, a current on/off ratio of greater than 105, and a subthreshold swing of ~ 80 mV/dec are demonstrated at low frequencies, which are promising for portable paper electronics.

Alternating-current-type inorganic powder electroluminescence (PEL) devices were successfully fabricated on four kinds of paper substrates, i.e., glossy paper, sticker paper, magazine paper, and newspaper. To protect the paper from wet chemical and heating processes during the formation of the PEL device, the paper substrate was coated with a spin-on-glass layer that served as a buffer layer. In spite of the fragility of paper, quite satisfactory results were obtained-the performance of paper-based PEL devices was almost equivalent to that of PEL devices on a plastic substrate. Extension of a substrate to paper, even to flimsy daily newspaper, will widen the opportunity of PEL devices as one of flexible and disposable displays.

Computer-aided design techniques are now used extensively for the production of masks in the microelectronic industries. In these methods the microcircuit patterns are broken down into simpler component parts, such as rectangles, whose co-ordinates are punched onto paper tape. A logic system has been developed to control an electron probe from coordinates read in on paper tape. Successive rectangles specified on the tape are scanned by the probe on the specimen, exposing an electron-sensitive material. A microcircuit pattern is thus built up from these basic rectangular elements. The use of an electron probe allows the generation of patterns with submicron dimensions within a reasonable time. The system outlined above has been used to produce microcircuit patterns using two techniques. In one, electron-sensitive resist is used to define a pattern etched in underlying material; in the other, metallic patterns are deposited directly by the decomposition of a metallic compound.

A convenient form of graph paper is described that allows the frequency constant (f c ) and the MTF index ( n ) of many devices to be easily determined.

The electrophoretic display (EPD) is the main solution to electronic papers, but most of them can display the image or text in black and white particles only. The users may prefer the EPD showing multiple colors rather than the black/white content only. In this paper, we introduce the driving system for a color EPD, which is composed of three kinds of particles. The system aims at optimizing the visual quality based on a new driving waveform by equipping with an optimization method for color and tone reproduction. The experimental result shows that the proposed EPD driving system can display three-color pictures with promising visual quality.

This paper presents a parallel plate-type field emission device of potassium hydroxide-doped electrochemically reduced graphene oxide (GO) manufactured using highly oriented pyrolytic graphite through electrochemical exfoliation. The material properties of the GO were tested through Raman spectroscopy, X-ray diffraction, and X-ray photoelectron spectroscopy. The optimal electron emission characteristics of the device were as follows: turn-on field = 2.03 V/ $\mu \text{m}$ , field emission current $= \,\, 16.4~\mu \text{A}$ , and field emission enhancement factor = 8377. At an emission peak wavelength of 563.7 nm, the optimal device had a light flux of 4.21 lumens and an illumination of 140.3 lux. These properties can be utilized in various optoelectronic devices, such as nanoelectronics devices, sensors, electrochemical systems, and energy storage devices.

In this paper, a fully controlled photocatalytic reduction of graphene oxide (GO) sheets is presented in which electrical bias is applied in combination with UV illumination. It is proved that this controllability allows higher conductivities and lower UV illumination times for the achieved reduced graphene oxide (rGO) sheets, which are not allowed without gate voltage. We attribute the observed enhancement mechanism in photocatalytic reduction to electron accumulation at the ZnO/GO interface and decrement of recombination of photogenerated carriers. Then, we applied ZnO nanowires to reduce the GO sheets locally and realize rGO ribbons. The optoelectric response of the fabricated photodetector based on the realized rGO ribbon shows that by controlling the photocatalytic reduction, we can achieve a tunable/selective photodetector ( $\lambda _{\mathrm {incident}} = 520$ , 595, and 633 nm have been investigated). These functionalities allow tuning the output sensitivity of the device in response to different incident wavelengths along the fabrication process or even after the fabrication process. We believe that the presented approach introduces a new generation of tunable devices suitable for different application fields, including optoelectronics.

Completely biodegradable printed circuit boards (PCBs) have been developed using biocomposites made from natural cellulose fibers extracted from banana stems and wheat gluten, which are normally considered as agricultural wastes or coproducts. PCBs were fabricated using these composites with properties suitable for electronic applications. The biocomposites are free of chemicals, and an environmentally benign approach was adopted to fabricate the PCBs. Conventional PCBs are critical components in electronics and are currently made using fire resistant plastics (FRPs). FRPs are typically made using glass fibers and epoxy, which are nonbiodegradable when disposed in the environment. Several attempts have been made to develop environmentally friendly PCBs and other electronic components. Although dissolvable electronics and foldable PCBs have been reported, so far, there are no 100% biodegradable PCBs. The dielectric constant for banana fiber/wheat gluten composite varied between 2–36, which is in the range of dielectric materials used for PCB and other electronic components. A significant amount of heat (up to 45 °C) was dissipated through the biocomposite preventing overheating and thus reducing risk of fires. PCBs did not show any deterioration in performance even after exposure to high humidity (90%) or high temperature (100 °C). LED connected to the PCB was able to glow without any interruption. Natural fibers and protein-based PCBs may provide an alternative to the synthetic polymer-based electronic components and help us to reduce the environmental burden due to the disposal of electronic waste (e-waste).

A single atomic layer of graphene, integrated onto an undoped bulk substrate in a back-gated transistor configuration, demonstrates surprising strong photoconduction, and yet, the physical origin of the photoresponse is not fully understood. Here, we use a detailed computational model to demonstrate that the photoconductivity arises from the electrostatic doping of graphene, induced by the surface accumulation of photogenerated carriers at the graphene/substrate interface. The accumulated charge density depends strongly on the rate of charge transfer between the substrate and the graphene; the suppression of the transfer rate below that of carrier’s thermal velocity is an essential prerequisite for a substantial photoinduced doping in the graphene channel under this mechanism. The contact-to-graphene coupling (defined by the ratio of graphene–metal contact capacitance to graphene’s quantum capacitance) determines the magnitude of photoinduced doping in graphene at the source/drain contacts. High-performance graphene phototransistors would, therefore, require careful engineering of the graphene–substrate interface and optimization of graphene–metal contacts.

We present a computational study on hybrid nanomaterial-insulator-silicon solar cells where single-walled carbon nanotube or graphene forms the emitter as well as top conducting electrode on n-type crystalline silicon having a thin interfacial tunnel oxide. The effects of nanomaterial doping and tunnel oxide thickness on cell characteristics are modeled. Similar to bulk emitters, cell efficiency could be increased by chemical doping (p-type) of the nanomaterial. Unlike bulk, nanomaterial could get electrostatically doped (n-type) due to its low quantum capacitance, by the surface charge density in silicon. For chemically undoped graphene on lightly ( $10^{{16}}$ /cm $^{{3}}$ ) doped silicon, efficiency loss due to the electrostatic doping effect is $\sim 11$ %. A moderate p-type chemical doping (0.2 eV shift in Fermi level) of graphene reduces the aforementioned loss to $\sim 2$ %. The electrostatic doping effect in carbon nanotube-based cells is relatively small and independent to nanotube’s chemical doping. For tunnel oxide thickness $\ge 2$ nm, photogenerated carrier accumulation at silicon/oxide interface considerably enhances the electrostatic doping effect. The effect of tunnel oxide thickness variation on fill factor and open circuit voltage is shown to be qualitatively similar to standard bulk metal–insulator–silicon solar cells. Our model predicts an optimal oxide thickness of $\sim 1$ nm which confirms the experimental reports.

This paper investigates the plasma-spraying technique as applied to oxide cathodes compared with the conventional coating method. In the conventional oxide cathode manufacturing process, a carbonate powder layer BaSrCa(CO3) is either painted or sprayed onto the nickel-base material at room temperature after the carbonate powder has been mixed with a nitrocellulose binder to provide adhesion to the nickel surface. However, the by-products deposited due to the coating of the oxide cathode and the decomposing process, combined with the relatively weak adhesion resulting from this coating method, undermine the performance of the oxide cathode. Plasma spraying can produce a high-quality coating by applying a relatively inert medium using a high-temperature high-particle velocity process. Impacts on the performance of the plasma-sprayed oxide cathode, as compared with a conventionally coated oxide cathode, are presented. The experimental results show that the pulsed-current emission density of a plasma-sprayed oxide cathode is nearly twice that of the conventionally coated oxide cathode, whereas the evaporation rate of the plasma-sprayed oxide cathode is only 10% as much as the conventionally coated oxide cathode.

An electrophoretic display (EPD) cell with a triple-layered microcavity structure was fabricated using a convenient dry film resist. The inherent structural advantage arising from the function of the middle channel layer as a background colored state enabled the EPD to operate with two different-colored states by using a single type of electronic-ink particles, thereby eliminating the possible agglomeration of oppositely charged ink particles and supporting the potential application of the proposed structure to color the electronic paper. The preliminary operation of this new EPD structure was demonstrated as white and blue display states on a rigid glass exhibiting a contrast ratio of 1.5 : 1 with saturation voltages of + 30 and -30 V, respectively. Successful demonstrations on both the indium-tin-oxide-patterned glass and flexible polyethylene substrates are also provided.

A high-resolution active-matrix microencapsulated electrophoretic display (EPD) driven by polycrystalline-silicon thin-film transistors (poly-Si TFTs) with integrated drivers has been developed for the first feasibility study of electronic paper. The poly-Si TFTs were fabricated with a low temperature process below 425/spl deg/C. Microencapsulated electrophoretic material was coated on the TFT backplane, which was driven at 18 V. The resolution of the display is quarter VGA (video graphics array), and pixel pitch is 131 ppi (pixels per inch). As a result, this display offers a wide viewing angle, high contrast ratio and nonvolatilization of data. In addition, four-level grayscale images were also achieved by using an area ratio grayscale (ARG) driving method.

We present an approach to mass produce high-quality graphene on insulator substrate. Ni dots with single or few grains were achieved by annealing. Electron backscattered diffraction indicated that almost all of the Ni dots had (111) surface that is parallel to the substrate. Single-layer graphene with good crystalline quality has been grown on Ni dots. The patterned graphene films were transferred to insulating substrates by wafer bonding and etch back technique, which resulted in zero misalignment, low contamination, and high yield (>90%). Graphene-based field-effect transistors with self-aligned gate were fabricated with this method, which demonstrate the potential of this method as a candidate for mass production of graphene transistors.

A 3-level dot-pattern method (the 3-L method) has been developed in order to achieve stable and many gradational-level thermal printing with minimal loss in print resolution. This 3-L method employs dot-pattern matrices which consist of three density level dots; black (saturation density of thermal paper), gray (half-black density), and white (paper brightness) dots. The matrices are assigned to picture elements of continuous tone images according to their gradational levels. A theoretical analysis of the gradational printing characteristics was carried out on the basis of a modified Yule-Nielsen equation and an equation describing the color change of thermal paper. Using these equations, the numbers of equally spaced gradational levels were studied, and an optimum gray density for maximizing them was found. To further ensure high quality printing, optimum dot patterns were selected by the introduction of an evaluation function based on a discrete Fourier transform. The 3-L method was demonstrated to have good performance in tests with a thermal printing fixture employing a high-resolution (16 dots/mm) thermal head.

We propose a new kind of cathode-ray tube, namely, the thermal-transmission cathode-ray tube (TTCRT). In the TTCRT the electron beam focused to a small spot is called upon to heat in sequence small elements of a matrix that constitutes the faceplate of the tube. A heat-sensitive or thermal paper passed across the screen and maintained in contact with it, and outside the tube, will record characters and dot patterns generated through suitable two-dimensional deflection of the electron beam. We give a description of the main parameters regulating the performance of the TTCRT.

International audience; This paper presents the methodology, implementation and application of a full-band quantum transport model based on the non-equilibrium Green's function formalism and the empirical pseudopotentials. In particular the paper reports the treatment of heterojunctions between lattice matched semiconductors, comprising a gradual transition region described according to a virtual crystal approximation. Our approach entails several numerical techniques to make the full-band quantum transport method computationally affordable, and thus enable robust and efficient self-consistent device simulations. Then we employ our simulation scheme for the analysis of some exemplary devices based on quantum tunnelling, such as an Esaki tunnelling diode, as well as n-and p-type heterojunction Tunnel FETs. In particular we investigate the influence on the current-voltage characteristics of the width of the heterojunction transition region. We observe that a gradual transition region mainly affects the device characteristics by lengthening the tunnelling path at the heterojunction, which has a different impact on device current depending on the external bias conditions.

We demonstrate that the residual carbon concentration in the drift region can have a significant impact on the reverse leakage, breakdown voltage, and breakdown stability of GaN-on-GaN vertical diodes. Two generations (Gen1, Gen2) of polarization-doped p-n junctions with different C concentrations were compared, in terms of avalanche voltage, avalanche instability, and deep-level concentration. The original results collected within this paper show that: 1) both generations of devices can safely reach the avalanche regime; diodes with a lower residual CN have a higher reverse leakage and a lower avalanche voltage, due to an uneven distribution of the electric field; 2) the presence of residual carbon can lead to breakdown walkout, i.e. a recoverable increase in breakdown voltage under reverse-bias stress. Specifically, devices with higher C concentration show a fully-recoverable breakdown walkout, whereas the breakdown voltage is stable in devices with lower C concentration; and 3) steady-state photocapacitance measurements confirm the presence of CN in both generations, and are used to assess the relative difference in concentration between Gen1 and Gen2, even for levels below secondary ion mass spectroscopy (SIMS) sensitivity. The results described in this paper indicate the existence of a trade-off between breakdown voltage (increasing by improving compensation) and breakdown stability (improving by reducing CN concentration) and are of fundamental importance for the optimization of GaN power devices.

In this paper, a microfluidic device is introduced based on direct current (dc) dielectrophoresis for the separation of circulating tumor cells from normal blood cells. Differential sidewall electrodes are designed inside the channel and two middle-channel outlets are located after the end of the electrodes, which are assigned to collect the normal blood cells. A maximum dc potential of 3 V is applied to the electrodes, resulting in a differential dielectrophoretic forces acting on the cells. This paper involves isolating MCF-7 breast cancer cells from white blood cells (WBCs) and red blood cells (RBCs), eliminating the demand for primary RBC lysis. Numerical simulation results revealed that the differential electrodes not only suppressed successfully the need for high applied voltages by dc dielectrophoresis but also diminished the joule heating effects. Besides that, the arrangement of the differential electrodes was observed to play a critical role in the separation performance. In particular, designing the outlets, as well as adjusting the electrode potentials, has effectively assisted the device to be tunable for different cancer cells even with different radii. More strikingly, the ability of the device to deflect the waste cells (WBCs and RBCs) to out of the microchannel prior to the cancer cells was proven to positively affect the separation efficiency and purity. The proposed device was capable of separating different cells leveraging various diameters with capture purity and efficiency of higher than 83% and 100%, respectively.

Detailed physics of the third quadrant electrical characteristics of 1.2-kV rated 4H-SiC accumulation (Acc) and inversion (Inv) channel MOSFETs, based on experimentally measured data and TCAD numerical simulations, are described in this paper for the first time. The power MOSFETs with various channel lengths (0.3, 0.5, 0.8, 1.1 $\mu \text{m}$ ) used in this paper were fabricated in a 6-in commercial foundry. Numerical simulations verified that there are two current paths in the third quadrant: 1) through the base region and 2) through the p-n body diode. This paper demonstrates that the Acc MOSFETs have a smaller third quadrant knee voltage ( ${V}_{{\text {knee}}})$ of −1.2 V compared with −1.9 V for the Inv MOSFETs (at ${V}_{g} = {0}$ V and room temperature). Numerical simulations show that this difference is due to a smaller potential barrier for electron transport from the drain to the source in the base region for accumulation channel devices than inversion channel devices. Acc devices are shown to have a lower voltage drop in the third quadrant.

We report in this paper the design and fabrication of single-chip alternating current-LEDs (AC-LEDs) by monolithically integrating, for the first time, high-breakdown Schottky barrier diodes (SBDs) and micro-LED arrays using III-nitride LED epi-wafers of standard specs for volume production. A technique of cyclic mixed-etching has been introduced to restore the surface of inductively coupled-plasma (ICP) etching processed gallium nitride to device quality for fabricating high-breakdown Schottky junctions. Proof-of-concept single-chip AC-LED devices and a prototype driver-free white AC-LED lamp were demonstrated, showing high-efficiency LED emission, high chip area utilization efficiency, low power loss of the on-chip SBD bridge rectifier, and good luminous efficacy of the prototype AC-LED lamp. This paper paves the way toward mass-producing reliable and low-cost driver-free AC-LED lamps for solid-state lighting with existing LED manufacturing infrastructures.

This paper reports an industry standard monolithic 555-timer circuit designed and fabricated in the in-house silicon carbide (SiC) low-voltage bipolar technology. This paper demonstrates the 555-timer integrated circuits (ICs) characterization in both astable and monostable modes of operation, with a supply voltage of 15 V over the wide temperature range of 25 °C–500 °C. Nonmonotonic temperature dependence was observed for the 555-timer IC frequency, rise time, fall-time, and power dissipation.

Efficiency roll-off defined as the rapid efficiency drop by increasing the electrical current density is a major issue in the design of novel organic light-emitting diodes (OLEDs) based on thermally activated delayed fluorescence (TADF). In this paper, it is shown that efficiency enhancement and suppression of efficiency roll-off in TADF OLEDs can be accomplished by broadening the exciton generation zone by precisely tuning the doping concentration of the TADF emissive material in the host matrix. This universal and simply tunable parameter can be applied to any TADF OLED to further enhance its performance characteristics. In this paper, a typical TADF OLED with realistic parameters is numerically investigated by solving the charge carrier transport and excitonic equations and taking into account all relevant processes such as triplet–triplet annihilation, triplet–polaron, and singlet–triplet quenching, and (reverse) intersystem crossing. It is shown that the internal quantum efficiency (IQE) decreases at very low and very high doping densities due to exciton distribution nonuniformity and charge balance factor reduction, respectively. Power efficiency depends on the IQE as well as the potential drop across the emissive layer and decreases at very low doping densities even for a perfectly balanced device; however, the reduction for an unbalanced device is much more substantial. For a perfectly balanced device with an emissive layer thickness of 30 nm, at a current density of 10 mAcm−2, the IQE can be increased from 18% to more than 58% by decreasing the doping concentration from ${c}= {15}$ % to 0.5%. Power efficiency reaches its peak value of 38 lm/W at 1.4% doping.

A novel plasma Charge Accumulative Model (pCAM) by calculating time-integrated Fowler–Nordheim (FN) tunneling charges and field of the gate dielectric in plasma processes is proposed in this paper. Our prior studies have developed and presented a quantitative FinFET plasma recording device by an effective fin-shaped field effect transistor (FinFET) contact-to-metal coupling structure to record and quantify plasma ion charges created in FinFET backend processes. In this paper, a precise analytical model is proposed to model the magnitude of plasma ion charges, time-integrated stressing field, and the criteria of the plasma process for optimum FinFET process technology. The new pCAM is highly matching with the measurement result of 16- and 7-nm FinFET wafers. The model can be adapted to practically estimate the plasma damage with different charge types, process parameters, and ion distribution; it can optimize the FinFET process and further understand the plasma damage mechanism in charging processes of 7-nm FinFET and beyond.

The first part of this paper presented mymargin the device-level comparison of emerging materials (In0.53Ga0.47As and 2-D materials) and device architecture (NW FETs) with s-Si FinFETs. In order to further understand the performance and energy efficiency of these device options for future technology nodes, it is required to go beyond the device-level comparison by accounting for not only intrinsic but also the extrinsic parasitic elements. In this paper, we present the comparison of s-Si, In0.53Ga0.47As, and 2-D material-based n-type MOSFETs using the circuit-level figure of merits across three successive future technology nodes. The analysis incorporates both device characteristics obtained from an advanced quantum mechanical simulation tool and circuit-level comparison, which accounts for device parasitic elements and wiring load. The results show that 2-D material DG MOSFETs present a more energy-efficient device option than s-Si and In0.53Ga0.47As FinFETs in sub-0.7-V supply voltage regime and In0.53Ga0.47As nanowire (NW) FETs can outperform s-Si multi-gate (MuG) FETs and 2-D material FETs, but when considering non-idealities, s-Si NW FETs remain both faster and more energy-efficient device option.

To develop an efficient thermal design for gallium-nitride (GaN) high-electron-mobility transistors (HEMTs) that usually hold a super-high-power density, it is essential to accurately predict the junction temperature. In GaN HEMTs, the heat transfer process is dominated by thermal spreading resistance. Moreover, the phonon mean free paths (MFPs) of GaN are comparable with the channel layer thickness and the heat spot width. Thus, a ballistic effect emerges, resulting in the invalidity of Fourier’s heat conduction law. Therefore, Fourier’s law-based thermal resistance model should be reexamined and modified for this case. In this paper, we used the phonon Monte Carlo (MC) method to investigate the thermal spreading resistance in a ballistic-diffusive regime for GaN HEMTs. Our simulation results indicate that the ballistic effect significantly altered the temperature distributions within channel layers and resulted in a dramatic increase in the thermal resistance when compared with Fourier’s law-based predictions. Furthermore, a semiempirical thermal resistance model with a fitting parameter was derived. This model can accurately address the issues of thermal spreading and the ballistic effect. This paper can provide a more in-depth understanding of the thermal spreading resistance in a ballistic-diffusive regime, and it can be useful for the prediction of junction temperatures and for the thermal management of HEMTs.

This paper proposes a robust to defects and short length device (RDSLD), a newly in-plane resonant tunneling diode (RTD), and its ac-modeling with the minimum length of 3 nm. The proposed structure has robust performance in the presence of defects. It also has a high degree of flexibility in tuning electronic specifications. By using bipolar doping and a special h-boron nitride barrier pattern, these unique features are obtained. The simulation results verify that the proposed structure has the potential for replacing conventional RTD diodes. Such that the peak-to-valley ratio (PVR) and the maximum current of 4500, 450 nA for perfect bowtie and 3.45, 1256 nA for rhombic barrier shape structure are obtained, respectively. Also, negative differential resistance (NDR) is observed in all of the structures with vacancy and impurity defects. The effect of the geometrical parameters on the charge transmission of the device is another issue that is addressed in this paper. Furthermore, the analytical and numerical capacitance model parameters are presented.

Quantum dot (QD) white light-emitting diodes (LEDs) are promising devices in illumination and display applications, and the low thermal stability of QDs is one of the biggest problems limiting their practical use. In this paper, we proposed a metal-based inverted packaging (MIP) structure to enhance the thermal performance and stability of QD white LEDs. The results indicate that the thermal power of LED chips can greatly increase the surface temperature of QD white LEDs, especially that of the color-converted layer and the base. Therefore, the LED chip was separated from the QD layer and isolated with low thermal conductivity layers of air and glass using the MIP structure. This successfully reduces the base temperature and constrains the thermal power of the LED chip on the upper phosphor layer, thus enhancing the thermal performance for the QD layer. Consequently, MIP-QD white LEDs have a small deviation of 57.3 K in their correlated color temperature (CCT) and a deviation of 0.29 in their color rendering index (CRI) at injection power values in a wide range of 0.08–1.3 W, with mean values of 4382 K and 90.3, respectively. Moreover, these devices have negligible reduction in their electroluminescence intensity, and CCT and CRI values after aging for 10 h under severe conditions at an injection power of 0.9 W. Consequently, this paper can provide a general guide to enhance the thermal performance and stability of QD white LEDs by separating the thermal power of the LED chip from the QD layer.

Photodetectors (PDs) based on organic–inorganic hybrid materials such as graphene and perovskites have recently emerged at the forefront of the research in optoelectronic devices. Despite the remarkable progress in the performance of optoelectronic devices based on hybrid materials, some aspects such as stability have so far not been thoroughly addressed. This paper serves to demonstrate a fully inkjet-printed PD fabricated by hybrid perovskite (CH3NH3PbClx-3I3) layer between the two graphene electrodes as graphene/perovskite/graphene (GPG) heterostructure. The fully inkjet-printed GPG PD is found to be effective for the visible light region, which can be attributed by the high uniformity and low defects of the printed materials. Thus, the GPG PD achieves a high responsivity of 0.53 A/W. Fully inkjet-printed hybrid perovskite PD demonstrated in this paper unveils the facile, potentially large-scale and cost-effective methods for fabrication of hybrid perovskites-based optoelectronic devices, including PDs and solar cells.

The dielectric screening property of a semiconductor is very crucial for the electrical characteristics of a MOSFET, and which can be described mathematically by Poisson equation via the permittivity. While the theory and experiments have corroborated the permittivity reduction of nanoscale Si, this paper studies the electrical characteristics of MOSFETs considering the reduced channel permittivity by quantum transport simulations. It is found that the channel permittivity reduction may mitigate the short-channel effects, showing subthreshold swing improvement and threshold voltage shift of MOSFETs in nanoscale. Compared to quantization effects, the positive and negative impacts of the channel permittivity reduction on the devices in particularly nanoscale have been investigated. This paper elucidates the necessity of considering semiconductor permittivity reduction for nanoscale device design and simulations.

In recent years, triboelectric nanogenerators (TENGs) have been increasingly attracting attention owing to the ability for converting multiple mechanical energy into electricity. In this paper, we first propose a multifunctional conductive copper tape-based TENG (CCT-TENG) that is constructed completely using one piece of conductive copper tape. The triboelectric pairs, supporting structure, and conductive electrode were composed using bottom paper, silicone oil, and copper foil, all of which came from one roll of conductive copper tape. The approximate output power density of the CCT-TENG reached $240.1~\mu \text{W}$ /cm2. By spraying the aqueous solution of LiCl onto the surface of the bottom paper, a CCT-TENG incorporating LiCl was fabricated and used as a self-powered active sensor to detect the relative humidity (RH) of the environment. The obtained results revealed that the humidity sensor had good humidity response, response linearity, and reversibility. In addition, the RH was reflected by the brightness of light-emitting diodes (LEDs) that was driven by the humidity sensor. This paper realizes a promising, affordable, and portable integration of power supply systems and sensing systems, which can promote the application of TENG in the field of electronic detection device and environment monitoring.

In this paper, a charge plasma-based monolayer transition metal dichalcogenide (TMD) tunneling field-effect transistor (TFET) is investigated by solving self-consistent 3-D Poisson and Schrodinger equations in nonequilibrium Green’s function (NEGF) framework. We propose a work function engineered charge plasma-based dual-metal source TFET (DMS TFET) structure for an optimum performance of the device. The proposed TFET structure demonstrates superior performance than the conventional charge plasma TFETs in terms of ${I}_{{\scriptscriptstyle {\text {ON}}}}$ , ${I}_{{\scriptscriptstyle {\text {ON}}}}/{I}_{{\scriptscriptstyle {\text {OFF}}}}$ ratio, and subthreshold slope (SS). It provides ${I}_{{\scriptscriptstyle {\text {ON}}}}$ of $222~\mu \text{A}/\mu \text{m}$ , ${I}_{{\scriptscriptstyle {\text {ON}}}}/{I}_{ \mathrm{\scriptscriptstyle OFF}}$ ratio of $2.22\times 10^{{5}}$ , a minimum SS of 42.41 mV/decade, and an average SS of 54.15 mV/decade for three-decade increase in drain current ( ${I}_{\text {DS}}$ ). The performance of the device is observed at different channel lengths. Based on this analysis, a device design guideline for sub-10-nm channel length TFETs is presented in the paper. Finally, the circuit level metrics of the proposed structure are estimated by calculating delay and energy-delay product of a 45-stage inverter chain.