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A high-efficiency ${D}$ -band monolithically integrated GaN frequency doubler based on a pair of antiseries four-anode planar GaN Schottky barrier diodes (SBDs) has been successfully fabricated. Unlike the traditional hybrid integrated circuit technology, the monolithic integrated circuit technology has been used in the design and fabrication of GaN SBD-based frequency doubler circuits to achieve good alignment and low conversion losses. At room temperature, the experiments show that the peak conversion efficiency reaches 17.0% at 115.6 GHz under a continuous wave (CW) driving which is a critical requirement for many practical applications. The efficiency of 17.0% is the highest efficiency of GaN SBD-based multipliers at present under CW driving mode. This monolithically integrated doubler also exhibits a broadband high efficiency characteristic of more than 4.7% (−5.58 dB from 17%) across a 10% band from 109 to 121 GHz. In addition, high CW power handling capability of the proposed frequency doubler is verified. The experiments show that the frequency doubler can endure a maximum CW input power of 0.5 W. [ABSTRACT FROM AUTHOR]

The 6-in gate commutated thyristor (GCT) is suitable for hybrid dc circuit breaker (HDCB) application with its large chip area and high maximum controllable current (MCC), compared with traditional 4-in GCTs. P+ base doping dispersion control is of vital importance in the 6-in GCT chip. Based on the strong correlation between P+ base doping and the gate-cathode breakdown voltage (${V}_{\text {gbr}}$), P+ base doping dispersion is characterized through ${V}_{\text {gbr}}$. Test results show that ${V}_{\text {gbr}}$ dispersion in the 6-in GCT sample with etched depth of around $10~\mu \text{m}$ is about 2 V with the average ${V}_{\text {gbr}}$ of around 22 V. While ${V}_{\text {gbr}}$ dispersion in the sample with etched depth of above 20 $\mu \text{m}$ is above 6 V with the average ${V}_{\text {gbr}}$ of around 27 V. These are consistent with the 2-D simulation results. Then, P+ base doping parameter design is optimized through experiment. Both turn-on and turn-off characteristics of 6-in GCT samples with different P+ base doping parameter designs are compared with HDCB application. The final optimized 6-in GCT chip has no difficulty in turning on under a low dc-link voltage below 100 V and it can turn off 13 kA with the overvoltage of about 4.5 kV successfully, which shows potential in HDCB application. [ABSTRACT FROM AUTHOR]

Nanoelectromechanical (NEM) switches offer the advantages of zero OFF-state leakage current, abrupt switching characteristics, nonvolatile (NV) operation, and relatively low ON-state resistance as compared with CMOS transistors predominantly used for digital computing today. NEM switches can be implemented using metallic interconnect layers formed in the back-end-of-line (BEOL) steps of a standard CMOS IC manufacturing process, in order to enable compact implementation of hybrid CMOS-NEM circuits. In this article, a release-etch method is developed for realizing BEOL NV-NEM switches with $\leq 100$ -nm contact gaps. A functional array of BEOL NV-NEM switches is used to implement a hybrid CMOS-NEM IC for data search applications. NV-NEM switch design optimization to minimize the programming voltage and accelerate switching speed is discussed. A scaled NV-NEM technology is projected to be advantageous for high-speed, low-power reconfigurable computing applications. This projection is validated with experimental data for a BEOL NV-NEM switch implemented with a conventional 16-nm CMOS IC manufacturing process. [ABSTRACT FROM AUTHOR]

Quantum dots (QDs) can be used as conductive islands to build-up single-electron transistors (SETs). The characteristics of the QDs define the functional performance of the SETs. In consequence, analyzing the influence of the variations of QD dimensions on the performance of hybrid SET-FET circuits is of high relevance. We employ a self-developed SET compact model which is calibrated to 3-D quantum-mechanics-based simulations in order to obtain realistic model parameters. A method to improve the circuit behavior, i.e., to increase the output current, is proposed. It is concluded that the variation of the QD size presents the largest influence on the overall circuit behavior. [ABSTRACT FROM AUTHOR]

Recently, exploiting emerging nonvolatile memories to implement the process-in-memory (PIM) paradigm have shown great potential to address the von Neumann bottleneck and have attracted extensive research and development. In this paper, we present a novel PIM platform—spintronic processing unit (SPU), within spin transfer toque magnetic random access memory (STT-MRAM). This energy-efficient and reconfigurable PIM platform can perform different tasks—data storage and logic computing—using the same physical fabric that is programmable at the finest grain, i.e., the individual memory cell level, without the need to move data outside the memory fabric. The proposed SPU works just like a typical memory and all the logic functions are achieved through regularmemory-like write and read operations with minimal modifications. The functionality and performance are evaluated via hybrid circuit simulations under the 40-nm process technology node. Our proposed SPU is expected to be a feasible PIM platform in the near future, owing to the increasing maturity of STT-MRAM. [ABSTRACT FROM AUTHOR]

In this paper, ultrahigh-voltage (UHV) SiC devices with hybrid unipolar/bipolar operation are introduced and demonstrated. As the first step of such a device, a merged p-i-n Schottky (MPS) diode with an epitaxial p+-anode layer is proposed to reduce the conduction loss of a bipolar device in the low current region. A “snapback” phenomenon is intensively investigated by analytical modeling, device simulation, and experiment and a design guideline of snapback-free hybrid operating MPS diodes is presented. Using the design guideline, snapback-free MPS diodes are fabricated and forward characteristics are investigated. By using a proper edge termination structure, a UHV SiC MPS diode with breakdown voltage of 11.3 kV is demonstrated. [ABSTRACT FROM AUTHOR]

The current-induced perpendicular magnetic anisotropy magnetic tunnel junctions (p-MTJs) offer a number of advantages, such as high density and high speed. As p-MTJs downscale to $\sim 40$ nm, further performance enhancements can be realized thanks to high spin-torque efficiency, i.e., lower critical current density and higher thermal stability. In this paper, we investigate the origin of high spin-torque efficiency and give a phenomenological theory to describe the critical current reduction due to the subvolume activation. Based on various physical theories and structural parameters, a compact model of nanoscale MTJ is developed and demonstrates a satisfactory agreement with experimental results. Dynamic, static, and stochastic switching behaviors have been addressed and validated. Then, we perform mixed simulations for hybrid MTJ/CMOS read/write circuits, magnetic random access memory, and magnetic flip-flop to evaluate their performance. Analyses of energy consumption are given to show the prospect of MTJ technology node miniaturization. [ABSTRACT FROM AUTHOR]

A recently published hybrid circuit model for folded-waveguide slow wave structures has been implemented in the 1-D large signal code CHRISTINE. The resulting code is applied to a design for a G-band (220 GHz) folded-waveguide traveling wave tube. Results of small and large signal gain are compared with those from TESLA, a 2-D code using the same circuit model. Conditions for accuracy of the 1-D model are illustrated and explained. The effects of an offset beam tunnel on circuit dispersion and amplifier stability are illustrated using the CHRISTINE code. [ABSTRACT FROM AUTHOR]

The goal of neuromorphic engineering is to build electronic systems that mimic the ability of the brain to perform fuzzy, fault-tolerant, and stochastic computation, without sacrificing either its space or power efficiency. In this paper, we determine the operating characteristics of novel nanoscale devices that could be used to fabricate such systems. We also compare the performance metrics of a million neuron learning system based on these nanoscale devices with an equivalent implementation that is entirely based on end-of-scaling digital CMOS technology and determine the technology targets to be satisfied by these new devices. We show that neuromorphic systems based on new nanoscale devices can potentially improve density and power consumption by at least a factor of 10, as compared with conventional CMOS implementations. [ABSTRACT FROM AUTHOR]

Emerging synapse-like nanoscale devices such as memristive devices and synaptic transistors are of great interest to provide adaptability, high density, and robustness for the development of new bio-inspired circuits or systems. We have recently reported the nanoparticle organic memory field-effect transistor (NOMFET), which exhibits behaviors similar to a biological spiking synapse in neural network. It is considered as a promising nanocomponent to design neuromorphic adaptive computing circuits and systems. A functional model of NOMFET is presented in this paper, which allows the reliable conception and simulation of hybrid nano/complimentary metal–oxide–semiconductor circuits and architectures. Spice simulations of the model have demonstrated good agreement with the experimental results. By using the model, some complex neuromorphic functions such as synaptic gain control have been simulated. The model is developed in Verilog-A language and implemented on Cadence Virtuoso platform with Spectre 5.1.41 simulator. An iterative physical model and a number of experimental parameters have been integrated to improve the simulation accuracy. Special techniques and methods for dynamic behavior modeling have been developed, which could be extended to other nanodevices. [ABSTRACT FROM PUBLISHER]

We have developed an integration technology for the single electron transistor (SET)/CMOS hybrid systems. SET and CMOS transistors can be optimized without any possible degradation due to mixing dissimilar devices by adopting just one extra mask step for the separate gate oxidation (SGOX). We have confirmed that discrete devices show ideal characteristics required for the SET/CMOS hybrid systems. An SET shows obvious Coulomb oscillations with a 200-mV period and CMOS transistors show high voltage gain. Based on the hybrid process, new hybrid circuits, called periodic multiband filters, are proposed and successfully implemented. The new filter is designed to perform a filtering operation according to the periodic multiple blocking bands of which a period is originated from the SET. Such a novel function was implemented efficiently with a few transistors by making full use of the periodic nature of SET characteristics. [ABSTRACT FROM AUTHOR]