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In this paper, an improved 4H-SiC U-shaped trench-gate metal–oxide–semiconductor field-effect transistors (UMOSFETs) structure with low ON-resistance (${R}_{ \mathrm{\scriptscriptstyle ON}}$) and switching energy loss is proposed. The novel structure features an added n-type region, which reduces ON-resistance of the device significantly while maintaining the breakdown voltage (${V}_{\textsf {BR}}$). In addition, the gate of the improved structure is designed as a p-n junction to reduce the switching energy loss. Simulations by Sentaurus TCAD are carried out to reveal the working mechanism of this improved structure. For the static performance, the ON-resistance and the figure of merit (FOM $= {V}_{\textsf {BR}}^{\textsf {2}}/{R}_{ \mathrm{\scriptscriptstyle ON}}$) of the optimized structure are improved by 40% and 44%, respectively, as compared to a conventional trench MOSFET without the added n-type region and modified gate. For the dynamic performance, the turn-on time (${T}_{ \mathrm{\scriptscriptstyle ON}}$) and turn-off time (${T}_{ \mathrm{\scriptscriptstyle OFF}}$) of the proposed structure are both shorter than that of the conventional structure, bringing a 43% and 30% reduction in turn-on energy loss and total switching energy loss (${E}_{\mathbf {SW}}$). [ABSTRACT FROM AUTHOR]

In the domain of printed electronics (PE), field-effect transistors (FETs) with an oxide semiconductor channel are very promising. In particular, the use of high gate-capacitance of the composite solid polymer electrolytes (CSPEs) as a gate-insulator ensures extremely low voltage requirements. Besides high gate capacitance, such CSPEs are proven to be easily printable, stable in air over wide temperature ranges, and possess high ion conductivity. These CSPEs can be sensitive to moisture, especially for high surface-to-volume ratio printed thin films. In this paper, we provide a comprehensive experimental study on the effect of humidity on CSPE-gated single transistors. At the circuit level, the performance of ring oscillators (ROs) has been compared for various humidity conditions. The experimental results of the electrolyte-gated FETs (EGFETs) demonstrate rather comparable currents between 30%–90% humidity levels. However, the shifted transistor parameters lead to a significant performance change of the RO frequency behavior. The study in this paper shows the need of an impermeable encapsulation for the CSPE-gated FETs to ensure identical performance at all humidity conditions. [ABSTRACT FROM AUTHOR]

The TCAD framework developed in part-I of this paper is used to study the impact of fin length (FL) and fin width (FW) scaling on interface trap generation ($\Delta \mathrm{V}_{\mathrm {IT}}$) during negative bias temperature instability (NBTI) in FinFETs. Structure and mechanical stress are obtained by Sentaurus process. Sentaurus device having capture-emission depassivation (CED) and multistate configuration (MSC) models are used for the trap kinetics. The mechanical strain and quantum confinement (QC) impacts are considered. The framework is validated using measured data from p-FinFETs having different FL and FW. The calibrated framework is used to estimate the impact of scaling on NBTI for 14-nm technology node and below. Different scenarios such as iso-stress bias ($\mathrm{V}_{\mathrm {GSTR}}$) versus iso-stress overdrive (OD), and devices having iso-workfunction (WF) or iso-off current ($\mathrm{I}_{ \mathrm{\scriptscriptstyle OFF}}$) are used for comparison. [ABSTRACT FROM AUTHOR]

Integrated circuits operated in the near-threshold region exhibit specific merit with high energy efficiency. A near-threshold model is highly required for the circuit design. In this paper, a near-threshold drain current model is proposed based on the surface inversion layer charge model for analyzing digital circuits. The short-channel effect in deep submicrometer is also included in the model. Moreover, the delay and energy parts based on the near-threshold drain current model are derived and integrated in the model. Two process design kits (PDKs) are used for parameter extraction to demonstrate the feasibility of the proposed model. The results show that the proposed model can be used for the near-threshold circuit calculation, with the benefit of high accuracy. [ABSTRACT FROM AUTHOR]

This paper presents the GaxZn1−xO (x = 0, 0.1, and 0.3)-based photodetectors (PDs) by using mist atmospheric pressure chemical vapor deposition. X-ray diffraction and X-ray photoelectron spectroscopy are used to characterize crystal orientation, chemical qualitative, and quantitative characteristics of the GaxZn1−x (x = 0, 0.1, and 0.3) thin films. The photoluminescence is used to observe the near-band-edge emission and trap energy level. Among these three PDs, the Ga0.3Zn0.7O-based PD shows the lowest dark current, smallest noise current, and shortest response time. Furthermore, the Ga0.3Zn0.7O-based PD exhibits higher UV-B to UV-A rejection ratio and higher UV-B to visible rejection ratio. It is found that the cutoff wavelength is tunable by changing Ga contents in GaxZn1−x thin films. [ABSTRACT FROM AUTHOR]

InGaAs FinFETs are challenged by relatively high leakage current in the OFF state. This originates from band-to-band tunneling (BTBT) at the drain end of the channel that is amplified by a parasitic bipolar effect (PBE) as a result of its floating body. In this paper, we present a simple model of the PBE in InGaAs FinFETs, which captures the key gate length and fin width dependences. Our model accounts for surface recombination at the sidewalls of the fin as well as bulk recombination at the heavily doped source. When compared with experimental results, our model suggests that fin sidewall recombination dominates in long gate length transistors and leads to an exponential gate length dependence of the current gain on the parasitic bipolar junction transistor (BJT). The model enables the extraction of the carrier diffusion length which exhibits the predicted fin width dependence. For short gate length transistors, source recombination is shown to dominate and the parasitic bipolar gain scales with the inverse of the gate length. [ABSTRACT FROM AUTHOR]

This paper investigates the advantages and disadvantages of bonding pad over active area (BPOA) layout over a conventional layout for lateral AlGaN/GaN HEMTs designed for use in power applications. Extensive analysis of the performance of a BPOA device, both experimentally and supported by 3-D TCAD model simulations, reveals that while it can offer a higher current capability per unit area, it can lead to other disadvantages compared to a conventional design when considering reliability aspects. [ABSTRACT FROM AUTHOR]

Ferroelectric and negative-capacitance field-effect transistors (FeFETs and NCFETs) have recently garnered great attention as devices for applications in memory and low-power logic, respectively. As these technologies are pursued, it is critical to have a variety of measurement approaches, including methods familiar to the electron-device and microwave communities that can aid in fully understanding the behavior of ferroelectrics in FeFETs and NCFETs. In this paper, we propose and show the viability of using frequency-domain electrical measurement techniques employing the well-known microwave S-parameters, and their large-signal generalization and X-parameters. Our methods provide the means to trace the intrinsic polarization versus electric-field curve of the ferroelectric, i.e., with the parasitics de-embedded, thereby showing the innate ferroelectric response, which cannot be done using conventional techniques. These methods also enable extraction of all the parameters of the Landau–Khalatnikov equation, which is commonly used to model ferroelectric behavior in FeFETs and NCFETs. This paper hence takes a useful step toward methods familiar to the electron-device community that can help to better understand and optimize FeFET and NCFET technologies. [ABSTRACT FROM AUTHOR]

Transient cell current caused by the trapping/detrapping of grain boundary traps in the polycrystalline silicon (poly-Si) channel of a 3-D NAND cell string is comprehensively studied in this paper. This transient has a time constant of $10~\mu \text{s}$ or longer and is strongly dependent on the bias history. It is also affected by the trap distribution as revealed by TCAD simulations. Sensing offset between program verify and read results in “pseudo” charge loss/gain that reduces the sensing margin. The posttreatment of the poly-Si channel is suggested to mitigate this effect. [ABSTRACT FROM AUTHOR]

Silicon carbide (4H-SiC) devices experiencing avalanche conditions can reach temperatures above 1500 K. Simulation of impact ionization in devices should, therefore, include models valid up to such high temperatures. However, calibrations of impact ionization coefficients are available only up to 580 K, and simulations of switching show deviations from measurements at higher temperatures. In this paper, a more accurate model based on the underlying physics of high temperature and anisotropic avalanche generation is proposed. This model enables calibrations performed at room temperature along the ${c}$ -axis to be more precisely extrapolated to any temperature of interest in 2-D device simulations. The model provides an excellent fit to the measurements of breakdown voltages during unclamped inductive switching tests of power MOSFETs, enabling a more accurate prediction of ruggedness. The more comprehensive physics included in the model makes it also applicable to other wide bandgap semiconductors such as GaN, diamond, and Ga2O3, which also exhibit a high critical electric field. [ABSTRACT FROM AUTHOR]

In this paper, we show that MoS2 multilayers have mechanical and electrical properties that qualify them as promising channel materials for an n-type piezoelectric FET (PZ-FET). We present extensive density functional theory calculations to investigate the effects of a compressive, out-of-plane stress on MoS2 monolayers and multilayers and extract the corresponding stiffness, as well as the sensitivity to stress of the conduction and valence band edge, and of the effective masses. Then, we use these material properties and a top-of-the-barrier ballistic transistor model to evaluate numerically the ${I}_{\textsf {DS}}$ versus ${V}_{\textsf {G}}$ characteristics of n-type PZ-FETs with an MoS2 channel material. Our results indicate that MoS2 multilayers are the best material option for n-type PZ-FETs, which can reach a subthreshold swing of about 40 mV/decade for a 5-nm-thick piezoelectric layer. This is because the weak interlayer van der Waals bonding makes the conduction band edge in MoS2 multilayers very sensitive to vertical compressive stress. The simulated MoS2 PZ-FETs exhibit large ${I}_{ \mathrm{\scriptscriptstyle ON}}/{I}_{ \mathrm{\scriptscriptstyle OFF}}$ ratios at low voltage and have better subthreshold steepness compared with the counterpart device employing a 3-D semiconductor. [ABSTRACT FROM AUTHOR]

This paper examines metal–ferroelectric–insulator–semiconductor negative-capacitance FinFET (NC-FinFET) based VLSI subsystem-level logic circuits. For the first time, with the aid of a short-channel NC-FinFET compact model, we confirm the functionality and evaluate the standby-power/switching-energy/delay performance of large logic circuits (e.g., dynamic 4-bit Manchester carry-chain adder and the formal hierarchical 32-bit carry-look-ahead adder) employing 14-nm ultra-low-power NC-FinFETs. Our study indicates that the inverse Vds-dependence of threshold voltage (VT), also known as the negative drain-induced barrier lowering, of negative-capacitance field-effect transistor is not only acceptable but also beneficial for the speed performance of both the static and pass-transistor logic (PTL) circuits, especially for the PTL at low VDD. [ABSTRACT FROM AUTHOR]

Recently, exploiting emerging nonvolatile memories to implement the process-in-memory (PIM) paradigm have shown great potential to address the von Neumann bottleneck and have attracted extensive research and development. In this paper, we present a novel PIM platform—spintronic processing unit (SPU), within spin transfer toque magnetic random access memory (STT-MRAM). This energy-efficient and reconfigurable PIM platform can perform different tasks—data storage and logic computing—using the same physical fabric that is programmable at the finest grain, i.e., the individual memory cell level, without the need to move data outside the memory fabric. The proposed SPU works just like a typical memory and all the logic functions are achieved through regularmemory-like write and read operations with minimal modifications. The functionality and performance are evaluated via hybrid circuit simulations under the 40-nm process technology node. Our proposed SPU is expected to be a feasible PIM platform in the near future, owing to the increasing maturity of STT-MRAM. [ABSTRACT FROM AUTHOR]

In this paper, we propose and simulate a novel drain-engineered structure of a quadruple-gate tunnel field-effect transistor (TFET). The proposed device employs a lateral dual source with a vertical drain extension on top of T-shaped channel region. This enables the modification of screening length ($\lambda $) by varying the silicon film (${t}_{\textsf {Si},\textsf {v}}$) and the oxide (${t}_{\textsf {Si},\textsf {v}}$) thicknesses at the channel–drain junction to overcome the limitations of high ambipolar leakage in the conventional double-gate TFET (DG-TFET). A 2-D calibrated simulation study has revealed the doubling of on-current (${I}_{ \mathrm{\scriptscriptstyle ON}}$) and significantly suppressed ambipolar leakage (${I}_{\textsf {AMB}}$) in the proposed device as compared to the conventional DG-TFET. Furthermore, a five orders of magnitude improvement in ${I}_{ \mathrm{\scriptscriptstyle ON}}/{I}_{ \mathrm{\scriptscriptstyle OFF}}$ , 73% increase in transconductance (${g}_{\textsf {m}}$), 62% increase in cutoff frequency (${f}_{\textsf {T}}$), 72% increase in gain-bandwidth product, and 54% improvement in fall propagation delay (${t}_{\textsf {pHL}}$) are achieved in the proposed device. [ABSTRACT FROM AUTHOR]

In this paper, we develop an accurate analytical electrostatic potential model for both the n-type and p-type double-gate heterostructure tunnel field-effect transistors (H-TFETs). We solve the Poisson’s equation in four distinct regions inside the device, the depletion regions of the source, channel, and drain, and the drift-diffusion region of the channel, where the mobile charge carriers should be taken into account. It is shown that the model predicts the electrostatic potential profile of the various heterostructure devices with different material systems in all regions of the device operation accurately. The potential model is used for developing a model for the tunneling distance at the given energy level. Due to the physical nature of the models, the influence of the transistor parameters on the electrostatic characteristics of H-TFETs with desired heterojunction materials may be easily pursued. We show that the model results accurately predict the numerical simulation results for different device parameters. [ABSTRACT FROM AUTHOR]

This paper investigates the issues of oxygen accumulation and variation in the high-resistance state of HfO2-based resistive random access memory (RRAM), with improvement attained by inserting a thin oxygen-vacancy-rich layer of indium-tin-oxide (ITO) film. By acting as the oxygen ion reservoir, this ITO thin film on the TiN electrode can further stabilize resistance switching (RS) characteristics. In terms of reliability, ac endurance, and retention tests confirm stable RS characteristics for the Pt/HfO2/ITO/TiN device. Finally, a conducting model was proposed to explain the influence of the ITO thin layer and clarify the physical mechanism of electrical improvements. [ABSTRACT FROM AUTHOR]

Leakage phenomena are increasingly affecting the performance of nanoelectronic devices, and therefore, advanced device simulators need to include them in an appropriate way. This paper presents the modeling and implementation of direct source-to-drain tunneling (S/D tunneling), gate leakage mechanisms (GLMs) accounting for both direct tunneling and trap-assisted tunneling, and nonlocal band-to-band tunneling (BTBT) phenomena in a multissubband ensemble Monte Carlo (MS-EMC) simulator along with their simultaneous application for the study of ultrascaled fully depleted silicon-on-insulator, double-gate silicon-on-insulator, and FinFET devices. We find that S/D tunneling is the prevalent phenomena for the three devices, and it is increasingly relevant for short-channel lengths. [ABSTRACT FROM AUTHOR]

In this paper, uniformly doped drift region of silicon carbide (SiC) super-junction (SJ) MOSFET is replaced with vertical variable doping profile (VVD) to achieve a better tradeoff between breakdown voltage (BV) and specific ON-resistance (${R}_{\text {sp,on}}$). While it is known that the SJ device consists of two vertical columns of n- and p-type, SJ VVD feature lies in increasing the doping concentration from top to bottom in the N-column and vice-versa in the P-column within the drift region. The proposed SJ VVD allows $\text {R}_{{\text {sp, on}}}$ to reduce further due to increased average doping concentration in conducting N-column and BV to increase further due to shifting of an electric field from corners to the center of the drift region. BV and ${R}_{\text {sp,on}}$ improved by 10% in an SJ VVD MOSFET and these parameters follow linear relationship similar to SJ MOSFET. The 2-D numerical simulations from Synopsys TCAD are used for investigating the static and dynamic characteristics of the device. In addition to 30% improvement in Baliga figure of merit, 35% improvement is obtained over SJ MOSFET in turn on and turn off switching energies for a clamped inductive circuit at 1200 V–20 A. Improved dynamic characteristics of SJ VVD can be attributed to reduction in gate charge (${Q}_{g}$) and miller capacitance (${c}_{\text {rss}}$) compared to SJ MOSFET. [ABSTRACT FROM AUTHOR]

This paper extends Johnson’s classical theory [Johnson, Proc. IRE 43, 684 (1955)] for the threshold of backward-wave oscillation (BWO) in a traveling-wave tube by considering the effects of: 1) small random variations of the circuit phase velocity along the tube axis and 2) end reflections. We find that both the BWO threshold and BWO frequency are minimally affected by random variations of the phase velocity, but we find that the oscillation threshold depends sensitively on the magnitude and phase of the composite reflection coefficients. [ABSTRACT FROM AUTHOR]

This paper presents a low-temperature process to transfer devices on ultrathin silicon layers from a parent substrate to a foreign substrate or stack. MOS devices were fabricated on silicon-on-insulator (SOI) wafer. The device wafer was then temporarily bonded on a carrier wafer. The handle layer was etched and the remaining ultrathin silicon device layer of ~1.4 $\mu \text{m}$ was transferred to a foreign substrate using permanent bonding. Here, we explored two different bonding approaches, namely, 1) the gold–indium (Au–In) transient liquid phase (TLP) bonding and 2) the epoxy bonding. We demonstrate the advantages of epoxy bonding method over the TLP method. The unique characteristic of this epoxy bonding approach is its capability to vertically stack multiple thin silicon layers. Furthermore, we demonstrate three-layer stacking of the ultrathin silicon layers with functional metal–oxide–semiconductor field-effect transistors in each layer. Electrical characterization results of nMOS/pMOS devices in each layer is presented and compared for before and after transfer. Changes in measured device performance before and after stacking are studied using simulations. The maximum process temperature in this approach is 150 °C, which is considerably lower than those reported in the literature. This result demonstrates the feasibility of multilayer low-temperature stacking. [ABSTRACT FROM AUTHOR]

This paper describes the design and performance of two new high-resolution interline charge-coupled device image sensors for use in industrial, machine vision, and aerial photography applications. These sensors feature 4.5- $\mu \text{m}$ pixels, 4 outputs, fast dump gate, horizontal lateral overflow drain, and vertical electronic shutter. The 43-Mp sensor has a 35-mm optical format and the 50-Mp sensor has a larger format with a 2.175:1 aspect ratio that matches many modern mobile phone displays. This paper discusses the challenges and solutions to manufacture such large sensors with superior image quality such as uniformity, read noise, dark current, smear, transfer gate blooming, lag, and so on. [ABSTRACT FROM AUTHOR]

Oxide semiconductors are highly attractive for fabrication of large-area thin-film electronics because of their high electrical performance, low process temperature, high uniformity, and ease of industrial manufacturing. n-type oxide semiconductors, such as InGaZnO, are highly developed and have already been commercialized for backplane drivers of flat-panel displays. To date, developing CMOS technology is still an urgent issue in order to build low-power electronic circuits based on oxide semiconductors. In this paper, various CMOS circuits, including inverters, NAND, NOR, XOR, d-latches, full adders, and 7-, 11-, 21-, and 51-stage ring oscillators (ROs), are fabricated based on sputtered p-type tin monoxide and n-type InGaZnO. The inverters show rail-to-rail output voltage behavior, low average static power consumption of 8.84 nW, high noise margin level up to ~40% supply voltage, high yield of 98%, and high uniformity with negligible standard deviation. The NAND, NOR, XOR, d-latches, and full adders show desirably ideal input–output characteristics. The performances of ROs indicate small stage delay of $\sim 1~\mu \text{s}$ , extremely high uniformity and high yieldwhich are essential for large-area thin-film electronics. This paper may inspire constructions of low power, large area, large scale, and high-performance transparent/flexible CMOS circuits fully based on oxide semiconductors for applications beyond flat-panel displays. [ABSTRACT FROM AUTHOR]

The state-of-the-art RF and millimeter-wave circuits design requires accurate prediction of the nonquasi-static (NQS) effects at high frequency for all levels of channel inversion. This paper provides a practical insight to help high-frequency performance assessment of ultrathin body and box fully depleted silicon-on-insulator MOSFETs through a powerful frequency normalization scheme. Frequency dependence of small signal characteristics derived from experimental S-parameters is analyzed and reveals that the transconductance efficiency (${g}_{\textsf {m}}/{I}_{\textsf {D}}$) concept, already adopted as a low-frequency analog figure-of-merit (FoM), can be generalized to high frequency, including under asymmetric operation. We report that the normalized frequency dependence of the generalized transadmittance efficiency (${y}_{\textsf {m}}/{I}_{\textsf {D}}$) FoM only depends on the mobility and inversion coefficient. In addition, this approach is also used to extract essential parameters such as the critical NQS frequency ${f}_{\textsf {NQS}}$. [ABSTRACT FROM AUTHOR]

In this paper, a comparison of gate-all-around nanowire-FETs, nanoplate (NP)-FETs, and FinFETs was undertaken for the same areas of not only the gate metal but also the silicon channel, assuming the same conditions regarding the parasitic components. It is known that an NP-FET structure not only improves the delay performance but also enhances the immunity to short-channel effects. In addition, it is found that the use of a dual-k spacer with an NP-FET further improves the on-state as well as the off-state performances. [ABSTRACT FROM AUTHOR]

In this paper, we propose a novel static random access memory (SRAM) unit cell design and its array structure consisting of single-gated feedback field-effect transistors (FBFETs). To verify the SRAM characteristics, the basic memory operations and write disturbances of the unit cell are investigated through the mixed-mode technology computer-aided design simulations. The unit cell exhibits the superior SRAM characteristics including a write speed of 0.6 ns, a fast read-out speed of ~0.1 ns, and a retention time of 3600 s. Furthermore, the unit cell design exhibits advantages in density, with a small cell area of 8F2, and in the power consumption; the standby power consumption is 0.24 nW/bit for holding “1” and negligible for holding “0.” Moreover, our SRAM array shows reliable ${3} \times {3}$ array operations without any disturbances. This paper demonstrates the promising potential of the FBFET SRAM for high-performance, high-density, and low-power memory applications. [ABSTRACT FROM AUTHOR]

This paper presents the analyses on the self-sustained oscillation of superjunction MOSFET intrinsic diode. At first, the characteristics of the self-sustained oscillation for the superjunction MOSFET intrinsic diode are identified by the double-pulse switching test. The test results show that the self-sustained oscillation with significant self-amplification phenomenon can be triggered during the reverse recovery transient of superjunction MOSFET intrinsic diode. Based on the Sentaurus TCAD simulation, the self-sustained oscillation is reproduced. The simulation results reveal the root cause of the self-sustained oscillation. Due to the snappy reverse recovery of superjunction MOSFET intrinsic diode, the steep slope of diode snap off current can generate high voltage across the common source inductance, which drives the gate–source voltage and turns on the high-side MOSFET. The unexpected MOSFET turn-on can, in return, enhance the steepness of the current slope when the diode snap off. This leads to a positive feedback process and self-sustained oscillation is generated. In the end, based on the theoretical analyses and experimental results, the necessary methods that can suppress the oscillation are presented. [ABSTRACT FROM AUTHOR]

Feedback field-effect transistor (FBFET), an alternative switching device, has received attention due to its ideal steep switching feature. By utilizing the positive feedback phenomenon, the total amount of electrons and holes contributing to drain current is sharply surged. Although the device has conspicuous subthreshold slope (SS) properties, advanced research for structure and performance of it is lacking. In this paper, single-gated and spacer-less silicon-on-insulator (SOI) FBFET with extremely steep switching (~1 mV/decade) characteristic is studied in various aspects; SS attribute, performance variation of scaled FBFET, the impact of structural variation, the gate margin for the device layout, and the hysteresis window. The prospect of SOI FBFET as a future candidate for CMOS logic application is investigated in detail. [ABSTRACT FROM AUTHOR]

Variability is a challenge for future scaling as process dimensions reduce. The emerging 3-D sequential stacking technology is more than Moore’s scaling alternative. The 3-D design flow requires the partitioning of the netlist between the tiers. This paper presents the variability analysis of circuits partitioned into different levels. A comparison among local and global variations effects on ring oscillators (ROs) and SRAM is demonstrated. The across-chip variations and correlation range are shown as a critical point for the 3-D very large-scale integrated circuits, where the local variability is dominant. The correlations between devices due to the distances or the allocation into different tiers are directly taken into account in the SPICE model due to a statically unified model applied to 3-D circuits based on Monte Carlo simulations. Design wise, the 3-D integration can further decrease the circuit variability as shown in RO output frequency and SRAM static noise margin. [ABSTRACT FROM AUTHOR]

In this paper, the read margin (RM) and write power (WP) of 3-D vertical resistive random access memory (VRRAM) are analyzed by considering the variation in RRAM cell (self-rectifying cell) characteristics. To demonstrate the cell variation effect on a large 3-D VRRAM array, we develop a modified lumping method in HSPICE simulator and show that this method substantially reduces the computation time while maintaining high accuracy. Read and write performances including cell variation are investigated according to various array sizes and RRAM characteristics. A large distribution of cell current reduces the RM but hardly affects the WP. Moreover, in 3-D VRRAM with a small number of wordline (WL) layers, a large on/off ratio (RHRS/RLRS) is advantageous for improving the RM and reducing the variation effect. In contrast, a large on/off ratio has little effect on the RM in 3-D VRRAM with many WL layers. This difference occurs because the increased leakage induced in the half-selected cells mainly affects the RM, and the half-selected cells are located in the selected vertical pillar in 3-D VRRAM. [ABSTRACT FROM AUTHOR]

This paper proposes amorphous indium–gallium–zinc oxide thin-film transistors (TFTs) four-transistor-two-capacitor (4T2C) pixel circuit in combination with a top-anode organic light-emitting diode (OLED) for the use in 8K4K active-matrix organic light-emitting diode displays (AM-OLEDs). The proposed pixel circuit compensates for driving TFTs threshold voltage (${V} _{\textsf {TH}}$) shifts and mobility variations, ${V} _{\textsf {DD}}$ current–resistance (${I}$ – ${R}$) drops, and ${V} _{\textsf {SS}}~{I}$ – ${R}$ -induced rises. Both the positive and negative ${V} _{\textsf {TH}}$ of the driving TFT can be sensed by the proposed circuit. In this paper, we analyze the impact of the driving TFT compensation time for low gray levels. The current error rates are calculated when TFT mobility variations are considered. The proposed pixel circuit allows an increase in the compensation time to reduce the impact of driving TFT ${V} _{\textsf {TH}}$ and mobility variations on the performance of 4T2C pixel circuit. Conventional two-transistor-one-capacitor, five-transistor-two-capacitor, and proposed 4T2C pixel circuits are simulated and compared in this paper. The proposed pixel 4T2C circuit reduces the current error rates to below 5.79% when the ${V} _{\textsf {TH}}$ shifts of ±2 V, mobility variations of ±10%, ${V} _{\textsf {DD}}~{I}$ – ${R}$ drops of 1 V, and ${V} _{\textsf {SS}}~{I}$ – ${R}$ rises of 1 V are all considered. We show that the proposed 4T2C pixel circuit is suitable for 8K4K AM-OLEDs. [ABSTRACT FROM AUTHOR]

In this paper, we propose a physics-based compact model of the pinned photodiode (PPD) combined with the transfer gate. A set of analytical expressions is derived for the 2-D electrostatic profile, the PPD capacitance, and the charge transfer current. The proposed model relies on the thermionic emission current mechanism, the barrier modulation, and the full-depletion approximation to obtain the charge transfer current. The proposed physics-based model is fully validated with technology computer-aided design simulations, i.e., stationary and optoelectrical simulations. The development of such a compact model for PPD represents an essential step toward the design, simulation, and optimization of PPD-based pixels in CMOS image sensors. [ABSTRACT FROM AUTHOR]

We present the latest developments in Advance SPICE Model for GaN (ASM GaN) HEMTs in this paper. The ASM GaN model has been recently selected as an industry-standard compact model for GaN radio frequency (RF) and power devices. The core surface-potential calculation and the modeling of real device effects in this model are presented. We discuss the details of the nonlinear access region model and enhancement in this model to include a physical dependence on barrier thickness. We also present the novel model feature of configurable field-plate modeling and discuss the extraction procedure for the same. New results with the ASM GaN model on high-frequency and enhancement-mode GaN power devices are also presented. [ABSTRACT FROM AUTHOR]

This paper proposes a compact model for chipless radio frequency identification (RFID) tag. This compact scalable model consists of capacitors, inductors, and resistors of which their values are directly described by the physical dimension of the chipless tag. Moreover, based on this compact model, radar cross section of chipless RFID tag is predicted, by analyzing polarizability based on surface current distribution in different modes. To validate the proposed model, a 5-bit chipless RFID tag based on high-impedance surface (HIS) is presented, with good agreement among modeled, simulated, and measured results. A wide range of physical parameters have also been validated to show the scalability. This compact scalable model of chipless RFID tag not only simplifies the tag design, but also provides an insight understanding of the HIS structure. [ABSTRACT FROM AUTHOR]

This paper illustrates the usefulness of the physics-based compact device models in investigating the impact of device behavioral nuances on the operation and performance of the circuits and systems. The industry standard MIT virtual source gallium nitride high electron-mobility transistor (GaN HEMT) (MVSG) model is used as the modeling framework to understand the operation of the GaN HEMTs and study the key device–circuit interactions in the GaN-based high-frequency and power conversion circuits. Details of the core model equations along with their physical underpinnings are presented along with the benchmark tests to verify the model’s convergence robustness and simulation accuracy. The usefulness of such a compact model in circuit design is highlighted through examples of the GaN-based high-voltage converter and RF-power amplifiers. It is shown that the slew-rates in hard-switched buck converters are determined by the dynamic charge distribution among the field plates in GaN HEMTs, indicating the importance of the device-level effect on circuit performance. Likewise, it is shown using the MVSG model that the performance metrics, such as drain efficiency and linearity, of the GaN RF-power amplifiers are heavily dependent on the device-level effects, such as access-region depletion, thermal effects, and charge-trapping effects. These GaN-based circuits designed using the MVSG model can be used as the example cases to demonstrate the importance of the accurate physical compact models in designing high performance circuits and systems in emerging technologies. [ABSTRACT FROM AUTHOR]

A new concept of vertical gallium nitride (GaN) Schottky barrier diode based on nanowire (NW) structures and the principle of dielectric REduced SURface Field (RESURF) is proposed in this paper. High-threading dislocation density in GaN epitaxy grown on foreign substrates has hindered the development and commercialization of vertical GaN power devices. The proposed NW structure, previously explored for LEDs offers an opportunity to reduce defect density and fabricate low cost vertical GaN power devices on silicon (Si) substrates. In this paper, we investigate the static characteristics of high-voltage GaN NW Schottky diodes using 3-D TCAD device simulation. The NW architecture theoretically achieves blocking voltages upward of 700 V with very low specific on-resistance. Two different methods of device fabrication are discussed. Preliminary experimental results are reported on device samples fabricated using one of the proposed methods. The fabricated Schottky diodes exhibit a breakdown voltage of around 100 V and no signs of current collapse. Although more work is needed to further explore the nano-GaN concept, the preliminary results indicate that superior tradeoff between the breakdown voltage and specific on-resistance can be achieved, all on a vertical architecture and a foreign substrate. The proposed NW approach has the potential to deliver low cost reliable GaN power devices, circumventing the limitations of today’s high electron mobility transistors (HEMTs) technology and vertical GaN on GaN devices. [ABSTRACT FROM PUBLISHER]

Direct conversion crystalline silicon X-ray imagers are used for low-energy X-ray photon (4–20 keV) detection in scientific research applications such as protein crystallography. In this paper, we demonstrate a novel pixel architecture that integrates a crystalline silicon X-ray detector with a thin-film transistor amorphous silicon pixel readout circuit. We describe a simplified two-mask process to fabricate a complete imaging array and present preliminary results that show the fabricated pixel to be sensitive to 5.89-keV photons from a low activity Fe-55 gamma source. This paper presented can expedite the development of high spatial resolution, low cost, direct conversion imagers for X-ray diffraction and crystallography applications. [ABSTRACT FROM PUBLISHER]

Compact flicker noise models used in SPICE circuit simulators are derived from the seminal BSIM unified noise model. In this paper, we show that use of this model can give anomalous bias dependence of input referred noise. In addition, we find that the state-of-the art flicker noise models are not adequate to capture the drain bias dependence of flicker noise in short channel devices. In this paper, we address both the issues with a new compact model. [ABSTRACT FROM AUTHOR]

In this paper, a 1-Transitor (1-T) capacitorless dynamic random access memory (DRAM) using bandgap-engineered silicon-germanium Bipolar ionization metal oxide semiconductor field effect transistor (I-MOS) is investigated through numerical simulations. We have demonstrated the application of the proposed Si0.6Ge0.4 Bipolar I-MOS for realization of a 1-T capacitorless DRAM. The proposed device can achieve hysteresis at significantly lower drain voltages ( V\mathrm{LD} =0.45 V to V\mathrm{LU} =1.15 V), in comparison to the inversion mode device ( V\mathrm{LD} = 8 V to V\mathrm{LU} =11 V). In addition, the proposed 1-T capacitorless DRAM exhibits a wider hysteresis window ( \Delta \textV ) of the order ~700 mV and a sensing margin ( \Delta \textI ) of ~5 orders in comparison to the inversion mode based 1-T capacitorless DRAM. Moreover, the proposed 1-T capacitorless DRAM exhibits the retention time of ~750 msec and ~320 msec for T = 25 °C and T = 85 °C, respectively. The proposed 1-T capacitorless DRAM also shows nondestructive read and an extreme long-term endurance. Therefore, the results presented in this paper can provide an opportunity for future DRAM design in deep nanometer technology. [ABSTRACT FROM PUBLISHER]

An analytical model for junctionless double-gate FETs (JLDGFETs) in the subthreshold region is proposed in this paper. As the analytical models based on Young’s approximation demonstrate certain limitations due to the heavily doped channel of the JLDGFET, it is essential to model the electrical characteristics of a JLDGFET using alternative methods. Therefore, in this paper, by using the Fourier series and Green’s function, the potential distribution ( \phi ( {x} , {y} )) in the channel is solved, and the hot-carrier effects and random dopant fluctuation are modeled using localized trap charges and macroscopic analysis. Using the calculated \phi (x, y), {I} _{{\mathsf {DS}}} and {V} _{{\mathsf {th}}} are solved analytically with respect to various L and t {\mathsf {ox}} variations, subthreshold swing, the drain-induced barrier lowering, the localized trap charges, and a single impurity dopant. All results from the analytical model are verified through comparisons with commercially available 2-D ATLAS numerical simulation results. [ABSTRACT FROM PUBLISHER]

This paper demonstrates that—for high-electric fields and drain current levels—the electroluminescence (EL) versus VGS curves of GaN-on-Si radio frequency HEMTs significantly deviate from the well-known bell-shape, due to the turn-on of a secondary EL process that has not been described so far in the literature. Based on the combined EL measurements, electrical characterization, and thermal analysis, we demonstrate that: 1) for moderate gate and drain voltages, the EL versus VGS curve has the characteristic bell shape, and light emission originates from hot electrons injected from the source; EL signal is stronger at the edges of the gate, due to the higher electric field; 2) at high drain/gate bias and temperature, a second process induces a monotonic increase in the EL versus VGS curve; in this case, the EL signal is stronger at the center of the gate, and the EL intensity is directly correlated with the gate leakage current. Based on the experimental evidence collected within this paper, the secondary luminescence process is ascribed to: 1) the injection of carriers from the gate metal to the channel; 2) the acceleration of these electrons by the high gate–drain field; and c) the subsequent radiative emission. [ABSTRACT FROM AUTHOR]

This paper reports the performance of midwave infrared (MWIR) electron-injection avalanche photodiode (e-APD) fabricated using graded bandgap HgCdTe epilayers. Carrier transport in the e-APD is dominated by drift transport due to the built-in electric field associated with gradient in the bandgap. Carriers encounter fewer collision events before entering the multiplication region as the dead space effect is reduced. On-set of generation and multiplication processes is controlledmore effectively. High gain indicates a reduced in-elastic scattering by phonon-emission due to gradient. Quantum efficiency above 80% is achieved in merely 2–3- \mu \textm -thick absorbing layer because of more efficient collection of the photogenerated carriers. Lower generation volume is beneficial in terms of low dark current. The generation is confined in the vicinity of themultiplication region. Generated carriers are readily evacuated from the absorber region under the built-in electric field. An order of magnitude improvement over the state-of-the art performance in MWIR e-APD is achieved by introducing a controlled energy bandgap gradient in the HgCdTe epilayers. [ABSTRACT FROM AUTHOR]

In this paper, we report on the prospect of achieving very high values ( \geq 10^13 cm ^-2 ) of 2-D electron gas (2-DEG) density in ZnO-based heterostructures through buffer layer engineering. A physics-based analytical model is developed and utilized to demonstrate up to 25\times higher 2-DEG values in MgZnO/CdZnO as compared with that in the MgZnO/ZnO heterostructure at lower Mg composition of 0.10 in barrier layer. It is shown that a lower spontaneous polarization in buffer layer due to more electronegative Cd and higher lattice constant of CdZnO, which introduces tensile piezoelectric strain in the barrier layer, favorably add up, and increase polarization difference at barrier-buffer interface, which eventually enhances 2-DEG density. This paper demonstrates new opportunities to effectively utilize buffer layer properties to significantly improve the 2-DEG sheet density (~ 4 \times 10^{\mathrm { {13}}} cm ^{\mathrm { {-2}}}$ ) in ZnO heterostructures. [ABSTRACT FROM AUTHOR]

This paper reports ultralow contact resistivities ( \rho c) achieved on highly doped p-SiGe with two low-temperature contact formation methods. One method combines precontact amorphization implantation with ~500 °C rapid thermal processing (RTP)-based Ti germano-silicidation; \rho c achieved was \sim 2.9\times 10^-9~\Omega \cdot cm2. The other method combines codeposited TiSi—Ti:Si =1:1—with ~450 °C RTP-based Ti silicidation; \rho c achieved was \sim 1.7\times 10^-9~\Omega \cdot cm2. When \rho c reaches minimum, the TiSi(Ge) alloy is generally amorphous with embedded small crystallites, similar to the previous observations on pure Si substrates. [ABSTRACT FROM PUBLISHER]

The impact of triple metal with unalike work functions on the gate all around (GAA) tunnel FET is studied for the first time in this paper. An analytical model is introduced for surface potential and drain current of GAA triple metal tunnel FET with circular cross section, by using Poisson’s equation and Kane’s model. The modeling results are in good agreement with Synopsys 3-D TCAD results, thereby corroborating our analysis. The different metal work functions assist to create the potential barrier in the channel region to suppress the reverse tunneling from the drain side and also provides a more band bending at source end which revamp the drive current. [ABSTRACT FROM PUBLISHER]

In this paper, an n-p-n collector incorporated in the back side of a 4H-SiC trench IGBT is presented to reduce the turn-off energy loss. A comparative study between the proposed structure and the conventional structure is conducted through ATLAS. The simulation results have demonstrated that the turn-off energy loss is reduced by more than 82.96% with a slight degradation in the on-state voltage drop. [ABSTRACT FROM PUBLISHER]

This paper investigated the optical and thermal performance of the nitride-based ultraviolet light-emitting diodes fabricated by the eutectic flip-chip method. A new packaging structure was proposed by introducing a thin encapsulation layer doped with 0.4 wt% AlN nanoparticles (NPs) and uniform quartz lens simultaneously. Experimental results showed that the packaging structure proposed in this paper could significantly enhance the light output power, reduce the junction temperature, and increase the emission angle compared with the encapsulation layer consisting silicone only. When the NPs concentration increased from 0.1 to 0.4 wt%, the light output power increased from 7.6% to 17.4% at the forward current of 800 mA. Meanwhile, the junction temperature decreased by 5.7 °C, while the emission angle increased by 11.3°. What is more, it was found that the enhancement of light output power depended on the NPs concentration and showed the maximum at the concentration of 0.4 wt%. The enhanced light output power was attributed to the additional light scattering and the increased average refractive index resulted from the NPs introduced in the proposed package structure. [ABSTRACT FROM PUBLISHER]

This paper examines the fundamental reliability differences between n-p-n and p-n-p SiGe HBTs. The device profile, hot carrier transport, and oxide interface differences between the two device types are explored in detail as they relate to device reliability. After careful analysis under identical electrical stress conditions for n-p-n and p-n-p, the differences in activation energies for the damage of the oxide interfaces of the two devices is determined to be the primary cause for accelerated degradation seen in p-n-p SiGe HBTs. An analytical model has been adapted for simulating these aging differences between p-n-p and n-p-n devices. This paper has significant implications for predicting the degradation of complementary SiGe HBTs and even engineering future generations with well-matched n-p-n and p-n-p device-level reliability. [ABSTRACT FROM PUBLISHER]

In this paper, we systematically examined the impact of fin height ( H\mathrm{ Fin} ) and fin angle ( \theta \mathrm{ Fin} ) on the ac performance parameters including total gate capacitance ( C\mathrm{ gg} ), RC delay ( C_{\mathrm{ gg}}V_{\mathrm{ DD}}/I_{\mathrm{\scriptscriptstyle ON}} ), cutoff frequency ( f_{T} ), energy ( E ), total power ( P_{\mathrm{ Total}} ), and leakage power ( P_{\mathrm{ Leakage}} ) of hybrid FinFETs at the supply voltage, V\mathrm{ DD} with on-current I\mathrm{\scriptscriptstyle ON} . The RC delay, energy, and total power consumption are the primary factors limiting the operating frequency of the high-performance devices. Therefore, these electrical parameters are needed to be addressed in the architectural level of the fin based devices. In this paper, a calibrated numerical device simulation tool is used to achieve the best device performances of 14-nm hybrid FinFETs. From the simulated current–voltage ( I – V ) and capacitance–voltage ( C – C\mathrm{ gg}V\mathrm{ DD}/I\mathrm{\scriptscriptstyle ON} , fT , CV2, P\mathrm{ Total} , and P\mathrm{ Leakage} are extracted to analyze the effect of H\mathrm{ Fin} and \theta \mathrm{ Fin} on the performance matrices of these devices. In addition, this paper proposes an optimum structural configuration for 14-nm hybrid FinFET architecture for digital application perspective. [ABSTRACT FROM AUTHOR]

This paper reports on an extensive analysis of the breakdown of GaN-based Schottky-gated HEMTs submitted to high-voltage stress. The analysis was carried out on transistors with different lengths of the drain-side gate-head ( L\mathrm {GH} ), corresponding to different levels of electric field across the SiN passivation. Based on dc measurements, 2-D simulations, and optical analysis, we demonstrate the following original results: 1) when submitted to high drain voltages (in the OFF-state), the transistors can show catastrophic failure; 2) electroluminescence microscopy indicates the presence of hot-spots on the drain-side of the gate; 2-D simulations support the hypothesis that failure occurs in correspondence of the gate-head, on the drain-side edge, where the electric field in the silicon nitride passivation has its maximum; 3) this hypothesis is confirmed by the results of transmission electron microscope failure analysis that demonstrate the generation of a leakage path between the gate metal and the channel, 4) and by the dependence of the destructive voltage on the L\mathrm {GH} value. 5) in addition, we propose and demonstrate an approach for improving the reliability of the devices, i.e., using a graded SiN passivation with increased thickness. The results described in this paper provide important information for the device optimization of Schottky-gated HEMTs. [ABSTRACT FROM AUTHOR]

In this paper, gate resistance thermometry (GRT) was used to determine the channel temperature of AlGaN/GaN high electron-mobility transistors. Raman thermometry has been used to verify GRT by comparing the channel temperatures measured by both techniques under various bias conditions. To further validate this technique, a thermal finite-element model has been developed to model the heat dissipation throughout the devices. Comparisons show that the GRT method averages the temperature over the gate width, yielding a slightly lower peak temperature than Raman thermography. Overall, this method provides a fast and simple technique to determine the average temperature under both steady-state and pulsed bias conditions. [ABSTRACT FROM PUBLISHER]