Search

There have been a lot of ambiguities related to physics of quasi-saturation (QS) in laterally diffused MOS (LDMOS) devices in the published literature. For example, models that explain QS in input characteristics do not explain the same in output characteristics and vice versa. In addition to this, none of the earlier models explain early onset of QS at higher temperatures nor the models were validated using counter arguments. Attributed to this, a need for unified theory explaining physics of QS is justified in this paper. Furthermore, this paper for the first time, while addressing missing links between the observations reported in the past, develops a unified theory to explain physics of QS behavior. The theory presented here is independent of device architecture and covers all voltage-current–temperature trends. While considering velocity saturation and space charge modulation, we have discovered key role of high field mobility degradation of majority carriers and electric field screening, which is found to be the root cause of QS in LDMOS devices. The theory presented is further validated with numerous counter arguments. Finally, based on the new physical insight developed, we have proposed different approaches to mitigate QS effect. A detailed device design guideline to mitigate QS and its correlation with analog/RF performance, electo static discharge, hot-carrier reliability, self-heating, and safe operating area concern is presented in Part II of this paper. [ABSTRACT FROM PUBLISHER]

In this paper, a physics-based compact model for calculating the semiconductor charges and gate capacitance of III-V nanowire (NW) MOS transistors is presented. The model calculates the subband energies and the semiconductor charges by considering the wave function penetration into the gate insulator, effective mass discontinuity at the semiconductor-oxide interface, 2-D confinement in the NW, and Fermi-Dirac statistics. The semiconductor charge expression proposed in this paper is completely explicit in terms of applied gate voltage, therefore, making it highly suitable for large circuit simulations. The model is also compared with the results from self-consistent Schrödinger-Poisson solver for different NW sizes and materials and found to be accurate over a wide range of gate voltages. [ABSTRACT FROM AUTHOR]

With the emergence of a multichip Light-emitting diodes (LEDs) device based on different chip arrays, a new modeling for a multichip LED device with different array becomes urgent. This paper presents a compact thermal model (CTM) for the multichip LED device with different chip array for nonuniform thermal properties. Based on a general 3-D CTM, LED chips can be arranged in various array forms according to the multichip LED construction design. By linking the thermal matrix to junction temperature prediction, the proposed CTM provides accurate predictions of temperature distribution of the multichip LED device, compared to the practical physical model and infrared radiation measurement. The modeling technique has been successfully demonstrated and verified. Based on the proposed method, this paper presents the multichip LED device with a staggered array to optimize the LED positions so that heat concentration of the LED array can be reduced. [ABSTRACT FROM AUTHOR]

In this paper, we propose a vertical transistor with n-bridge and body on gate (BOG-DRAM) for Low-power 1T-DRAM application. The vertical channel of the device can reduce the short-channel effect and improve scalability. The storage region stacked on the gate leads to the efficient utilization of storage space. The device with junctionless channel layers on three sides can improve writing time. The conventional current bridge device only has one side gatecontrol depletion region, but the proposed BOG-DRAM has triple-side gate-control depletion region which can improve programming window at shorter gate lengths. BOG-DRAM achieves programming window of 33.6 μA/μm when the storage length is 20 nm. In addition, the work function offset is exploited for low-power application. [ABSTRACT FROM AUTHOR]

With lots of interest in negative capacitance field-effect transistors for ultralow-power complementary metal-oxide-semiconductor technology, negative capacitance thin-film transistors (NCTFTs) have also received much attention. Although previous studies on NCTFTs were done, the NC effect in organic-based TFTs was not studied yet. In this paper, P(VDF-TrFE) ferroelectric-gated P3HT semiconductor channel TFTs are experimentally demonstrated with solution-based fabrication process. Especially, this paper shed light on the NC effect in the organic based TFTs. The step-up current-voltage characteristics are repeatedly and reliably observed in diverse TFTs, and then, with the results, transconductance (gm) amplification implemented by the negative capacitance was delved. Moreover, with the aid of ferroelectric polarization switching, super steep-switching characteristic of the organic-based TFT was experimentally confirmed. These experimental results and discussion would be helpful in understanding NC effects in TFTs. [ABSTRACT FROM AUTHOR]

This paper presents using ultrasonic spray pyrolysis deposition method to grow MgO nanorod arrays on the top surface and the sidewall of the GaN-based ultraviolet light-emitting diodes. It is found that when the thickness of the MgO film is over 60 nm, the self-assembled MgO nanorod arrays are obtained. Transmission electron microscopy, scanning electron microscopy, X-ray diffraction, X-ray photoelectron spectroscopy, refractive index, extinction coefficient, and photoluminescence spectrum are used to analyze the structural, chemical, and optical characteristics of the MgO nanorod arrays. The LED chip with the MgO nanorod arrays shows slightly degraded electrical characteristics for it requires a higher forward voltage to provide 0.35-A forward current and higher series resistance. However, the LED chip with the MgO nanorod arrays has great improvement in electroluminescence and efficiency. Compared to the LED chip with a standard SiO2 passivation layer, the LED chip with the MgO nanorod arrays shows improvement of 14.1% in light output power (LOP), 12% in external quantum efficiency and wall plug efficiency. The uniformity of the LED performance like forward voltage, LOP, and wall-plug efficiency is investigated in this paper. [ABSTRACT FROM AUTHOR]

In this paper, we report a physics-based compact model for monolayer graphene field-effect transistors (m-GFETs) based on the 2-D Density of States of monolayer graphene and the drift-diffusion equation. Furthermore, the Ward-Dutton charge partitioning scheme has been incorporated to the model extending its capabilities to AC and transient simulations. The model has been validated through comparison with DC and RF measurements from two different long-channel m-GFET technologies. Moreover, values of parasitic elements included in the model are extracted from measurements on dedicated test structures and verified through electromagnetic simulations (EM). Finally, an EM-SPICE co-simulation has been carried out to assess the applicability of the developed m-GFET model for the design of “balun” circuits. [ABSTRACT FROM PUBLISHER]

The main purpose of this paper is to introduce an ultracompact device for electrostatic discharge (ESD) protection based on a bipolar metal oxide silicon (BIMOS) transistor merged with a dual back-to-back silicon-controlled rectifier (SCR) for bulk and for ultrathin body box fully depleted (FD)-silicon on insulator (SOI) advanced CMOS technologies in the hybrid bulk thanks to process co-integration. It is well known that ESD protection is a challenge for IC in advanced CMOS technology. In this paper, an optimized solution is described through the concept, design, 3-D technology computer aided design (TCAD) simulation, and silicon characterization in 28-nm FD-SOI in hybrid bulk. Measurements are done thanks to transmission line pulsed (TLP), very fast TLP and dc behavior. Moreover, the overvoltage is investigated through very fast transient characterization system measurements. It demonstrates a promising candidate to protect against ESD event and to develop new ESD network dedicated to system on chip. [ABSTRACT FROM PUBLISHER]

In this paper, an innovative process flow developed to improve the thermal resistance of power ICs was presented. In this field, one of the major device failure mechanisms is related to the high temperatures reached during the working cycles due to the extremely critical electrical current densities. Therefore, heat transfer and dissipation are crucial aspects that need continuous improvements. Usual approaches to face this issue deal with package heat sinks design, solder selection, and wafer thinning. In this paper, a novel technological approach was settled, in which heat sinks microstructures were successfully integrated at wafer level stage on standard p-i-n diodes. To this aim, the bulk Si on the backside was partially replaced with Cu, a material characterized by a higher thermal conductivity material. Moreover, the well microstructures filled by Cu provide the advantage of wafer self-support, without requiring dedicated and more expensive thinning and handling technologies. An extensive characterization of the final devices was also carried out to evaluate the process and the thermal and electrical improvements. Finally, a failure analysis on selected devices was performed to identify any critical issue with the standard packaging process. [ABSTRACT FROM PUBLISHER]

Wafer-scale, CMOS compatible graphene transfer has been established for device fabrication and can be integrated into a conventional CMOS process flow back end of the line. In Part I of this paper, statistical analysis of graphene FET (GFET) devices fabricated on wafer scale is presented. Device yield is approximately 75% (for 4500 devices) measured in terms of the quality of the top gate, oxide layer, and graphene channel. Statistical evaluation of the device yield reveals that device failure occurs primarily during the graphene transfer step. In Part II of this paper, device statistics are further examined to reveal the primary mechanism behind device failure. The analysis from Part II suggests that significant improvements to device yield, variability, and performance can be achieved through mitigation of compressive strain introduced in the graphene layer during the graphene transfer process. The combined analyses from Parts I and II present an overview of mechanisms influencing GFET behavior as well as device yield. These mechanisms include residues on the graphene surface, tears, cracks, contact resistance at the graphene/metal interface, gate leakage as well as the effects of postprocessing. [ABSTRACT FROM PUBLISHER]

As the transparent contact in radial p-n junction core-shell nanowire array solar cells can be either planar or conformal, the characteristics of these two types of device structure would be very different since conformal contact gives rise to severe band bending. Although radial p-n junction GaAs core-shell nanowire array solar cell with conformal transparent contact has been briefly inferred to have an inferior performance compared to the same nanowire array solar cell with planar transparent contact, the characteristics of these two types of radial p-n junction core-shell nanowire array solar cells are not known. Furthermore, it is unknown how the performance of these two types of solar cell compares with each other when the nanowire design parameters are optimized according to device physics of these two types of solar cell. In this paper, it is shown that radial p-n junction GaAs core-shell nanowire array solar cells with planar transparent contact are prone to carrier avalanche breakdown, and hence have a limited range of doping density. On the other hand, carrier diffusion in radial p-n junction GaAs core-shell nanowire array solar cells with conformal transparent contact is poor and hence requires a high doping to the core in order to increase the output voltage. All in all, this paper reveals that either type of transparent contact structure yields essentially the same energy conversion efficiency as long as the radial p-n junction GaAs core-shell nanowires are designed to suit the device physics of the type of transparent contact. [ABSTRACT FROM PUBLISHER]

This paper presents a compact analytical I – V model for short-channel double-gate transition metal dichalcogenide filed-effect transistors in the subthreshold region. A closed-form expression is proposed for the characteristic length in the scale length approach, which is based on physical device parameters. It is then used to find the channel potential and drain current in the subthreshold region. This model is verified with the numerical results of a nonequilibrium Green’s function (NEGF) simulator. There is good agreement between the results of the proposed model and the numerical NEGF simulations in the subthreshold region, while it captures the effects of the device’s physical parameters. [ABSTRACT FROM PUBLISHER]

In our earlier work, we presented a percolation theory-based analytical model to estimate FinFET’s VT distribution due to fin edge roughness. The earlier models in the literature were based on minimum fin width, the limitations of which were discussed in detail. In this paper, we advance the percolation theory-based model to capture the variability in all key-device parameters, viz. I \mathrm{\scriptscriptstyle ON} , I \mathrm{\scriptscriptstyle OFF} , subthreshold slope, and VT . The entire distribution of these parameters obtained by the model is presented and compared against stochastic TCAD to demonstrate excellent match. The model reduces rms error in $\mu $ of various parameters by 5%–60%, and 20%–50% in $\sigma $ with respect to the minimum fin width-based models present in the literature. [ABSTRACT FROM PUBLISHER]

This paper presents the 2-D numerical simulation results of the single-event burnout (SEB) in the floating field ring (FFR) termination of a power MOSFET for the first time. We investigate the SEB triggering mechanism and SEB performance based on a 140-V typical FFR termination, and find that the structure is sensitive to SEB because of a sharp temperature rise appearing at the p+ base/n-drift junction. A 140-V hardened FFR termination (an n-type buffer layer is added between the epitaxial layer and substrate layer) is also studied in this paper that can demonstrate much better SEB performance without sacrificing the basic characteristics compared to the standard one. In addition, the hardening mechanism is explained, and the performances of the hardened structures with different buffer layer thickness are discussed. As a result, the safe operating area can reach the value of the breakdown voltage when the thickness achieves or exceeds 3~\mu \textm . [ABSTRACT FROM AUTHOR]

Motivation to study the ZnO channel for thin-film transistors (TFTs) is strong in light of its decent high mobility and large bandgap, enabling simultaneous coexistence of high on current and low off-state leakage. Nevertheless, the improvement in device performance for ZnO TFTs has not been fully exercised and even the field-effect mobility ( \mu \text {FE} ) is degraded with downscaling the channel length owing to considerable series source/drain (S/D) resistance ( R\text {SD} ). In this paper, we show that inserting a thin contact layer of ZnON between the ZnO channel and Al S/D effectively suppresses the formation of interfacial layer of AlOx and thereby reduces R \text {SD} dramatically. This is evidenced by a significant reduction in R \text {SD} from 30.1 to 14.4 \textk\Omega \cdot \mu \textm measured on 0.5- \mu \textm ZnO TFTs with a ZnON contact layer or not, leading to an improvement in \mu \text {FE} from 18.2 to 29.6 cm ^2/\text V\cdot \text s . [ABSTRACT FROM AUTHOR]

A new concept of vertical gallium nitride (GaN) Schottky barrier diode based on nanowire (NW) structures and the principle of dielectric REduced SURface Field (RESURF) is proposed in this paper. High-threading dislocation density in GaN epitaxy grown on foreign substrates has hindered the development and commercialization of vertical GaN power devices. The proposed NW structure, previously explored for LEDs offers an opportunity to reduce defect density and fabricate low cost vertical GaN power devices on silicon (Si) substrates. In this paper, we investigate the static characteristics of high-voltage GaN NW Schottky diodes using 3-D TCAD device simulation. The NW architecture theoretically achieves blocking voltages upward of 700 V with very low specific on-resistance. Two different methods of device fabrication are discussed. Preliminary experimental results are reported on device samples fabricated using one of the proposed methods. The fabricated Schottky diodes exhibit a breakdown voltage of around 100 V and no signs of current collapse. Although more work is needed to further explore the nano-GaN concept, the preliminary results indicate that superior tradeoff between the breakdown voltage and specific on-resistance can be achieved, all on a vertical architecture and a foreign substrate. The proposed NW approach has the potential to deliver low cost reliable GaN power devices, circumventing the limitations of today’s high electron mobility transistors (HEMTs) technology and vertical GaN on GaN devices. [ABSTRACT FROM PUBLISHER]

Direct conversion crystalline silicon X-ray imagers are used for low-energy X-ray photon (4–20 keV) detection in scientific research applications such as protein crystallography. In this paper, we demonstrate a novel pixel architecture that integrates a crystalline silicon X-ray detector with a thin-film transistor amorphous silicon pixel readout circuit. We describe a simplified two-mask process to fabricate a complete imaging array and present preliminary results that show the fabricated pixel to be sensitive to 5.89-keV photons from a low activity Fe-55 gamma source. This paper presented can expedite the development of high spatial resolution, low cost, direct conversion imagers for X-ray diffraction and crystallography applications. [ABSTRACT FROM PUBLISHER]

Compact flicker noise models used in SPICE circuit simulators are derived from the seminal BSIM unified noise model. In this paper, we show that use of this model can give anomalous bias dependence of input referred noise. In addition, we find that the state-of-the art flicker noise models are not adequate to capture the drain bias dependence of flicker noise in short channel devices. In this paper, we address both the issues with a new compact model. [ABSTRACT FROM AUTHOR]

In this paper, a 1-Transitor (1-T) capacitorless dynamic random access memory (DRAM) using bandgap-engineered silicon-germanium Bipolar ionization metal oxide semiconductor field effect transistor (I-MOS) is investigated through numerical simulations. We have demonstrated the application of the proposed Si0.6Ge0.4 Bipolar I-MOS for realization of a 1-T capacitorless DRAM. The proposed device can achieve hysteresis at significantly lower drain voltages ( V\mathrm{LD} =0.45 V to V\mathrm{LU} =1.15 V), in comparison to the inversion mode device ( V\mathrm{LD} = 8 V to V\mathrm{LU} =11 V). In addition, the proposed 1-T capacitorless DRAM exhibits a wider hysteresis window ( \Delta \textV ) of the order ~700 mV and a sensing margin ( \Delta \textI ) of ~5 orders in comparison to the inversion mode based 1-T capacitorless DRAM. Moreover, the proposed 1-T capacitorless DRAM exhibits the retention time of ~750 msec and ~320 msec for T = 25 °C and T = 85 °C, respectively. The proposed 1-T capacitorless DRAM also shows nondestructive read and an extreme long-term endurance. Therefore, the results presented in this paper can provide an opportunity for future DRAM design in deep nanometer technology. [ABSTRACT FROM PUBLISHER]

An analytical model for junctionless double-gate FETs (JLDGFETs) in the subthreshold region is proposed in this paper. As the analytical models based on Young’s approximation demonstrate certain limitations due to the heavily doped channel of the JLDGFET, it is essential to model the electrical characteristics of a JLDGFET using alternative methods. Therefore, in this paper, by using the Fourier series and Green’s function, the potential distribution ( \phi ( {x} , {y} )) in the channel is solved, and the hot-carrier effects and random dopant fluctuation are modeled using localized trap charges and macroscopic analysis. Using the calculated \phi (x, y), {I} _{{\mathsf {DS}}} and {V} _{{\mathsf {th}}} are solved analytically with respect to various L and t {\mathsf {ox}} variations, subthreshold swing, the drain-induced barrier lowering, the localized trap charges, and a single impurity dopant. All results from the analytical model are verified through comparisons with commercially available 2-D ATLAS numerical simulation results. [ABSTRACT FROM PUBLISHER]

This paper demonstrates that—for high-electric fields and drain current levels—the electroluminescence (EL) versus VGS curves of GaN-on-Si radio frequency HEMTs significantly deviate from the well-known bell-shape, due to the turn-on of a secondary EL process that has not been described so far in the literature. Based on the combined EL measurements, electrical characterization, and thermal analysis, we demonstrate that: 1) for moderate gate and drain voltages, the EL versus VGS curve has the characteristic bell shape, and light emission originates from hot electrons injected from the source; EL signal is stronger at the edges of the gate, due to the higher electric field; 2) at high drain/gate bias and temperature, a second process induces a monotonic increase in the EL versus VGS curve; in this case, the EL signal is stronger at the center of the gate, and the EL intensity is directly correlated with the gate leakage current. Based on the experimental evidence collected within this paper, the secondary luminescence process is ascribed to: 1) the injection of carriers from the gate metal to the channel; 2) the acceleration of these electrons by the high gate–drain field; and c) the subsequent radiative emission. [ABSTRACT FROM AUTHOR]

In this paper, we report on the prospect of achieving very high values ( \geq 10^13 cm ^-2 ) of 2-D electron gas (2-DEG) density in ZnO-based heterostructures through buffer layer engineering. A physics-based analytical model is developed and utilized to demonstrate up to 25\times higher 2-DEG values in MgZnO/CdZnO as compared with that in the MgZnO/ZnO heterostructure at lower Mg composition of 0.10 in barrier layer. It is shown that a lower spontaneous polarization in buffer layer due to more electronegative Cd and higher lattice constant of CdZnO, which introduces tensile piezoelectric strain in the barrier layer, favorably add up, and increase polarization difference at barrier-buffer interface, which eventually enhances 2-DEG density. This paper demonstrates new opportunities to effectively utilize buffer layer properties to significantly improve the 2-DEG sheet density (~ 4 \times 10^{\mathrm { {13}}} cm ^{\mathrm { {-2}}}$ ) in ZnO heterostructures. [ABSTRACT FROM AUTHOR]

This paper reports the performance of midwave infrared (MWIR) electron-injection avalanche photodiode (e-APD) fabricated using graded bandgap HgCdTe epilayers. Carrier transport in the e-APD is dominated by drift transport due to the built-in electric field associated with gradient in the bandgap. Carriers encounter fewer collision events before entering the multiplication region as the dead space effect is reduced. On-set of generation and multiplication processes is controlledmore effectively. High gain indicates a reduced in-elastic scattering by phonon-emission due to gradient. Quantum efficiency above 80% is achieved in merely 2–3- \mu \textm -thick absorbing layer because of more efficient collection of the photogenerated carriers. Lower generation volume is beneficial in terms of low dark current. The generation is confined in the vicinity of themultiplication region. Generated carriers are readily evacuated from the absorber region under the built-in electric field. An order of magnitude improvement over the state-of-the art performance in MWIR e-APD is achieved by introducing a controlled energy bandgap gradient in the HgCdTe epilayers. [ABSTRACT FROM AUTHOR]

In this paper, an n-p-n collector incorporated in the back side of a 4H-SiC trench IGBT is presented to reduce the turn-off energy loss. A comparative study between the proposed structure and the conventional structure is conducted through ATLAS. The simulation results have demonstrated that the turn-off energy loss is reduced by more than 82.96% with a slight degradation in the on-state voltage drop. [ABSTRACT FROM PUBLISHER]

This paper reports ultralow contact resistivities ( \rho c) achieved on highly doped p-SiGe with two low-temperature contact formation methods. One method combines precontact amorphization implantation with ~500 °C rapid thermal processing (RTP)-based Ti germano-silicidation; \rho c achieved was \sim 2.9\times 10^-9~\Omega \cdot cm2. The other method combines codeposited TiSi—Ti:Si =1:1—with ~450 °C RTP-based Ti silicidation; \rho c achieved was \sim 1.7\times 10^-9~\Omega \cdot cm2. When \rho c reaches minimum, the TiSi(Ge) alloy is generally amorphous with embedded small crystallites, similar to the previous observations on pure Si substrates. [ABSTRACT FROM PUBLISHER]

The impact of triple metal with unalike work functions on the gate all around (GAA) tunnel FET is studied for the first time in this paper. An analytical model is introduced for surface potential and drain current of GAA triple metal tunnel FET with circular cross section, by using Poisson’s equation and Kane’s model. The modeling results are in good agreement with Synopsys 3-D TCAD results, thereby corroborating our analysis. The different metal work functions assist to create the potential barrier in the channel region to suppress the reverse tunneling from the drain side and also provides a more band bending at source end which revamp the drive current. [ABSTRACT FROM PUBLISHER]

This paper investigated the optical and thermal performance of the nitride-based ultraviolet light-emitting diodes fabricated by the eutectic flip-chip method. A new packaging structure was proposed by introducing a thin encapsulation layer doped with 0.4 wt% AlN nanoparticles (NPs) and uniform quartz lens simultaneously. Experimental results showed that the packaging structure proposed in this paper could significantly enhance the light output power, reduce the junction temperature, and increase the emission angle compared with the encapsulation layer consisting silicone only. When the NPs concentration increased from 0.1 to 0.4 wt%, the light output power increased from 7.6% to 17.4% at the forward current of 800 mA. Meanwhile, the junction temperature decreased by 5.7 °C, while the emission angle increased by 11.3°. What is more, it was found that the enhancement of light output power depended on the NPs concentration and showed the maximum at the concentration of 0.4 wt%. The enhanced light output power was attributed to the additional light scattering and the increased average refractive index resulted from the NPs introduced in the proposed package structure. [ABSTRACT FROM PUBLISHER]

Presents an introduction to the July 2005 issue of the journal "IEEE Transactions on Electron Devices."

This paper investigates the impact of backgate biasing ( VBS ) on the drain current ( ID ) of ultrathin-body III-V heterojunction tunnel FET (HTFET). Compared with homojunction TFET and III-V/Ge MOSFET, this paper indicates that HTFET exhibits significantly higher I\mathrm{{\scriptstyle OFF}} ( ID at VGS = 0 V and VDS=0.5 V) modulation efficiency and the influence of VBS rapidly decreases with increasing VGS . In addition, it is observed that the change of source available states with VBS determines the ID modulation efficiency of p-type HTFET (pHTFET). Depending on the source doping concentration and operating VGS , the ID of HTFET under forward VBS can be anomalously smaller than that at VBS=0 V. Furthermore, the impacts of source/drain doping concentrations and junction properties are discussed and shown to be critical in determining the ID modulation efficiency of HTFET. We find that, under controlled ambipolar current, reverse backgate biasing can be utilized to suppress the I\mathrm{{\scriptstyle OFF}} of HTFET, and the modulation efficiency increases with decreasing source doping concentration. Our study may provide insights for device/circuit designs with advanced TFET technologies. [ABSTRACT FROM PUBLISHER]

Silicon-on-insulator (SoI) technology has been reported as a technique to improve electrical characteristics over those of bulk MOSFETs. However, this approach results in the disadvantage of increased drain-induced barrier lowering (DIBL) due to drain electric flux (or field) passing through the buried oxide (BOX) layer. Against such a background, the development of a method to easily estimate the amount of this electric flux is expected to support the prediction of BOX-related DIBL. This paper involved the investigation of a model-derived analytically using conformal mapping techniques to represent the amount of flux in subthreshold regions of ground-plane SoI MOSFETs. To create the model, this paper was divided into two parts. In Part I, as preparation for model development, the relationships between coordinates in MOSFETs and potential/stream function were derived using conformal mapping, and related validity was verified. In Part II, the model’s development was considered based on these relationships, and its validity was also verified. [ABSTRACT FROM PUBLISHER]

Closed form model for skin and proximity effect is necessary for GSI interconnects. In this paper, exact formulation for current distribution inside multiwall carbon nanotube (MWCNT) bundles is derived using multiconductor transmission line model. The current distribution is different from copper wires and it is geometry dependent because of kinetic inductance and quantum capacitance. This current distribution is used to compute and formulate high frequency resistance of MWCNT bundles. [ABSTRACT FROM AUTHOR]

The aim of this paper is the analysis of the multipactor effect in a parallel-plate waveguide when a ferrite slab, transversally magnetized by a static magnetic field parallel to the waveguide walls, is present. Employing an in-house developed code, numerical simulations are performed to predict the multipactor radio frequency voltage threshold in such a ferrite-loaded waveguide. Variations of the ferrite magnetization field strength and the ferrite slab height are analyzed. Effective electron trajectories are also shown for a better understanding of the breakdown phenomenon, finding different multipactor regimes. [ABSTRACT FROM AUTHOR]

The purpose of this paper is to present the main results of an electrostatic discharge (ESD) protection for advanced CMOS technology with electromagnetic (EM) field effect and Lorentz Force (LF) contributions during fast transient and high-current surge. To address this goal, the first step is building a tool to simulate fast transient conditions with all participating physical mechanisms included. The relevant equations describing these mechanisms are: 1) the charge transport equations and 2) the Maxwell equations to describe the EM fields. The LF is also included using an extended formulation of the current-continuity equations. An integrated approach is followed to simulate the full structure (metal connections $+$ silicon device) during the ESD surge and to compare the results between ElectroMagnetic Lorentz Force simulations and transmission line pulse measurements. Obviously, in general, this paper and tool can be used to address electromagnetic compatibility topics and more. [ABSTRACT FROM AUTHOR]

Thanks to the high electron velocities, III–V semiconductors have the potential to meet the challenging ITRS requirements for high performance for sub-22-nm technology nodes and at a supply voltage approaching 0.5 V. This paper presents a comparative simulation study of ultrathin-body InAs, In0.53Ga0.47As , and strained Si MOSFETs, by using a comprehensive semiclassical multisubband Monte Carlo (MSMC) transport model. Our results show that: 1) due to the finite screening length in the source-drain regions, III–V and Si nanoscale MOSFETs with a given gate length (L{G}) may have a quite different effective channel length (Leff) ; 2) the difference in Leff provides a useful insight to interpret the performance comparison of III–V and Si MOSFETs; and 3) the engineering of the source-drain regions has a remarkable influence on the overall performance of nanoscale III–V MOSFETs. [ABSTRACT FROM AUTHOR]

In this paper, the harmonic distortion (HD) in the underlap double-gate MOSFETs (UDG-MOSFETs) with high-k spacers is analyzed. The HD occurs due to the nonlinearity in the device performance and therefore, a detailed analysis of the HD as a function of spacer dielectric constant (k) is critical to ensure device reliability for RF performance. In this paper, the analysis is performed for the primary components, the second-order distortion (HD2), and the third-order distortion (HD3) along with the total HD. The parameters analyzed for the HD study of the UDG-MOSFETs with high-k spacers are the drain current, the transconductance, and the transconductance generation factor. The results of the analysis suggest a reduction in the distortion phenomenon for the high-k spacer devices, thereby ensuring reliability of these devices for RF applications. Also, a detailed analysis of HD2 and HD3 as a function of k of the high-k spacers are performed using UDG-MOSFETs in cascode and differential amplifier circuits. [ABSTRACT FROM PUBLISHER]

This paper exhibits systematic results for lateral light emitting diodes (LEDs) with various conditions. The simulation results and circuit model are both included to describe the current spreading effect at the same time. A fully 2-D model that solves Poisson and drift-diffusion equations to investigate the current flow and radiative recombination distribution specifies the uniformity of the carrier distribution, which is combined with the Monte Carlo ray tracing technique to calculate the light extraction efficiency (LEE). This paper focuses on the modulation of the transparent conducting layer. In addition, this paper will discuss bottom emission LEDs addressing the current spreading effect and LEE compared with top emission LEDs. We also examine the droop effect to verify our discussion. A thorough analysis provides deep insights for achieving high efficiency lateral LEDs. [ABSTRACT FROM PUBLISHER]

This paper examines the fundamental reliability differences between n-p-n and p-n-p SiGe HBTs. The device profile, hot carrier transport, and oxide interface differences between the two device types are explored in detail as they relate to device reliability. After careful analysis under identical electrical stress conditions for n-p-n and p-n-p, the differences in activation energies for the damage of the oxide interfaces of the two devices is determined to be the primary cause for accelerated degradation seen in p-n-p SiGe HBTs. An analytical model has been adapted for simulating these aging differences between p-n-p and n-p-n devices. This paper has significant implications for predicting the degradation of complementary SiGe HBTs and even engineering future generations with well-matched n-p-n and p-n-p device-level reliability. [ABSTRACT FROM PUBLISHER]

In this paper, we systematically examined the impact of fin height ( H\mathrm{ Fin} ) and fin angle ( \theta \mathrm{ Fin} ) on the ac performance parameters including total gate capacitance ( C\mathrm{ gg} ), RC delay ( C_{\mathrm{ gg}}V_{\mathrm{ DD}}/I_{\mathrm{\scriptscriptstyle ON}} ), cutoff frequency ( f_{T} ), energy ( E ), total power ( P_{\mathrm{ Total}} ), and leakage power ( P_{\mathrm{ Leakage}} ) of hybrid FinFETs at the supply voltage, V\mathrm{ DD} with on-current I\mathrm{\scriptscriptstyle ON} . The RC delay, energy, and total power consumption are the primary factors limiting the operating frequency of the high-performance devices. Therefore, these electrical parameters are needed to be addressed in the architectural level of the fin based devices. In this paper, a calibrated numerical device simulation tool is used to achieve the best device performances of 14-nm hybrid FinFETs. From the simulated current–voltage ( I – V ) and capacitance–voltage ( C – C\mathrm{ gg}V\mathrm{ DD}/I\mathrm{\scriptscriptstyle ON} , fT , CV2, P\mathrm{ Total} , and P\mathrm{ Leakage} are extracted to analyze the effect of H\mathrm{ Fin} and \theta \mathrm{ Fin} on the performance matrices of these devices. In addition, this paper proposes an optimum structural configuration for 14-nm hybrid FinFET architecture for digital application perspective. [ABSTRACT FROM AUTHOR]

In this paper, gate resistance thermometry (GRT) was used to determine the channel temperature of AlGaN/GaN high electron-mobility transistors. Raman thermometry has been used to verify GRT by comparing the channel temperatures measured by both techniques under various bias conditions. To further validate this technique, a thermal finite-element model has been developed to model the heat dissipation throughout the devices. Comparisons show that the GRT method averages the temperature over the gate width, yielding a slightly lower peak temperature than Raman thermography. Overall, this method provides a fast and simple technique to determine the average temperature under both steady-state and pulsed bias conditions. [ABSTRACT FROM PUBLISHER]

This paper describes an extensive analysis of the degradation of (InAlGa)N-based UV-B light-emitting diodes (LEDs) submitted to constant current stress. This paper is based on combined electrical characterization, spectral analysis of the emission, deep-level transient spectroscopy (DLTS) and photocurrent (PC) spectroscopy. The results of this analysis demonstrate that: 1) UV-B LEDs show a gradual degradation when submitted to constant current stress; the decrease in optical power is stronger for low measuring current levels, indicating that degradation is related to the increase in Shockley–Read–Hall (SRH) recombination; 2) the current–voltage characteristics measured before/during stress show an increase in the current below the turn-on voltage, that is ascribed to the increase in trap-assisted tunneling (TAT) components; and 3) DLTS analysis and PC spectroscopy measurements were carried out to identify the properties of the defects responsible for the degradation of the optical and electrical characteristics. The results indicate that stress induces or activates defects centered around 2.5 eV below the conduction band edge. These defects, close to midgap, can explain both the increased SRH recombination and the increase in TAT components detected after stress. Moreover, the DLTS measurements allowed to identify the signature of Mg-related acceptor traps. [ABSTRACT FROM PUBLISHER]

This paper reports on an extensive analysis of the breakdown of GaN-based Schottky-gated HEMTs submitted to high-voltage stress. The analysis was carried out on transistors with different lengths of the drain-side gate-head ( L\mathrm {GH} ), corresponding to different levels of electric field across the SiN passivation. Based on dc measurements, 2-D simulations, and optical analysis, we demonstrate the following original results: 1) when submitted to high drain voltages (in the OFF-state), the transistors can show catastrophic failure; 2) electroluminescence microscopy indicates the presence of hot-spots on the drain-side of the gate; 2-D simulations support the hypothesis that failure occurs in correspondence of the gate-head, on the drain-side edge, where the electric field in the silicon nitride passivation has its maximum; 3) this hypothesis is confirmed by the results of transmission electron microscope failure analysis that demonstrate the generation of a leakage path between the gate metal and the channel, 4) and by the dependence of the destructive voltage on the L\mathrm {GH} value. 5) in addition, we propose and demonstrate an approach for improving the reliability of the devices, i.e., using a graded SiN passivation with increased thickness. The results described in this paper provide important information for the device optimization of Schottky-gated HEMTs. [ABSTRACT FROM AUTHOR]

The expected explosive growth of big data, the Internet of Things, artificial intelligence, and 5G mobile networks will not only challenge but also offer new opportunities to solid-state memories in the next decade. Mainstream technologies such as the 3-D NAND Flash and the 1T-1C DRAM technology will have to keep evolving to prolong their scaling trends and maintain their undisputed leadership in the standalone memory arena. At the same time, other memory technologies may take advantage of the rise of the new market applications, likely changing the balance among cost, performance, and reliability. Phase-change memories (PCM), magnetoresistive random-access memories (MRAM), resistive random-access memories (ReRAM), and ferroelectric memories have the potential to play a role both in the embedded and in the standalone memory market. However, all of them will need innovations to fully demonstrate their long-term performance. Finally, all the memory technologies will have to compete to prove the benefits of new applications and solutions, such as the mixing of storage and computing with in-memory computing, neuromorphic computing, and nonvolatile logic. [ABSTRACT FROM AUTHOR]

The base series resistance is an important parameter for bipolar junction transistors and heterojunction bipolar transistor (HBTs). Although many methods have been proposed for its experimental determination, their results vary significantly. In this paper, the most widely used methods are reviewed and applied to SiGe HBTs of different technologies and generations including different device types, i.e. high-speed and high-voltage SiGe HBTs. The accuracy of the methods is evaluated by applying them to a sophisticated physics-based compact model, allowing to clearly detect and explain the causes for the observed inaccuracies or failures. The methods are then also applied to experimental data. In both cases, a large variety of device sizes have been investigated. This paper and its results provide insight into each method’s accuracy, its application limits with respect to a technology, device size, and operating range as well as its requirements in terms of equipment and extraction effort. [ABSTRACT FROM PUBLISHER]

In this paper, we propose a novel dual-metal gate-stack (DMSG) architecture with HfO2 spacer for scaling the nanowire FETs (NWFETs) to the sub-10-nm regime. We demonstrate that the electric field at the channel–drain extension interface is reduced when the inbuilt electric field arising due to a difference in the work function at the interface of the two metals in the DMSG is coupled to the nanowire through the fringing fields through the HfO2 spacer. The reduction in the electric field leads to a larger tunneling width, and therefore suppresses the lateral band-to-band-tunneling component of the gate-induced drain leakage in the DMSG NWFETs. Although the gate capacitance increases in the DMSG NWFETs due to the fringing fields, this paper demonstrates that the increase in the intrinsic delay (~1.5 times) is not very significant to degrade the circuit performance drastically. Using calibrated 3-D simulations, we show that the off-state current is reduced by more than five orders of magnitude in the DMSG NWFETs, leading to a significantly high on-state to off-state current ratio of ~106 even when the channel length is scaled to 7 nm. [ABSTRACT FROM PUBLISHER]

Silicon heterojunction solar cells having semiconducting oxide-selective contacts can revolutionize the photovoltaic industry with the promise of low cost and high efficiency. In this paper, we have identified the potential design issues of silicon heterojunction cell using simulation. This paper compares two possible electron-selective oxides (TiO2 and ZnO) and two possible hole-selective oxides (CuAlO2 and NiO). The Fermi level in the oxide at the oxide/metal interface is pinned by the metal (its workfunction and eventual interface dipoles). We considered this effect, which determines the effective workfunction of the metal contact as opposed to the actual metal workfunction. Our simulation suggests that Fermi level pinning has significant impact on the device performance. We also considered different interface passivation effects and oxide dopings in our simulation. The simulation suggests that high doping in oxides is beneficial to counter balance the effect of poor surface passivation. This paper provides an extensive understanding of the design of Si heterojunction solar cell using band-engineered semiconducting oxide as the selective contact replacing highly doped emitter and back surface field. [ABSTRACT FROM PUBLISHER]

An electrostatic nonuniformity in the cantilever vertical tunneling FETs intrinsically exists in the InAs/GaSb junction to InAs cantilever transition region. The effects of the coupling ratio (CR) nonuniformity are investigated in this paper. The results show that the switching characteristics are degraded by the CR nonuniformity, especially in the case of large InAs/GaSb band offset. This paper also reveals that the nonuniformity in InAs/GaSb vertical tunneling FETs can be mitigated with the optimized band offset of heterojunction, scaling of oxide thickness, and acute angle etching profile. [ABSTRACT FROM AUTHOR]

This paper studies on the RF MEMS switch based on flexible liquid crystal polymer (LCP) substrate and the influence of the LCP substrate bending characteristics on mechanical properties of the switch. Due to the excellent properties of flexible LCP materials, RF MEMS devices based on LCP substrates will be very suitable for microwave systems with high space requirements and wearable devices. Obviously, the deformation of flexible substrate will affect the performance of RF MEMS switch. Therefore, this paper proposes a modeling of the substrate bending to analyze it. The experimental results of the fabricated switches show that the pull-in voltage of the switch is $\sim 22$ V, the insertion loss is better than −0.6 dB, the isolation is better than −15 dB, and the return loss is better than −18 dB up to 20 GHz. According to the experiments, we can find that when the curvature of the substrate is increased from zero to 22.2 (1/m), then the measured pull-in voltage is increased from 22.1 to 23.9 V and when the curvature of the substrate is increased from 22.2 to 44.2 (1/m), then the measured pull-in voltage is decreased from 23.9 to 18.9 V. In conclusion, with the increase of substrate curvature, the switch pull-in voltage will increase at first and then decrease. The experimental results are in good agreement with the modeling. [ABSTRACT FROM AUTHOR]

High-temperature integrated circuits provide important sensing and controlling functionality in extreme environments. Silicon carbide bipolar technology can operate beyond 500 °C and has shown stable operation in both digital and analog circuit applications. This paper demonstrates an 8-b digital-to-analog converter (DAC). The DAC is realized in a current steering R-2R configuration. High-gain Darlington current switches are used to ensure ideal switching at 500 °C. The measured differential nonlinearity (DNL) and integral nonlinearity (INL) at 25 °C are 0.79 and 1.01 LSB, respectively, while at 500 °C, the DNL and INL are 4.7 and 2.5 LSB, respectively. In addition, the DAC achieves 53.6 and 40.6 dBc of spurious free dynamic range at 25 °C and 500 °C, respectively. [ABSTRACT FROM AUTHOR]

In this paper, we explore the electrical characteristics of ring oscillator (RO) by optimizing fabrication inline windows of 16-nm high- \kappa /metal-gate bulk FinFET devices. Key process parameters are ranked according to ROs’ performance, including effective capacitance ( C_{\mathrm {eff}}) , effective resistance ( R_{\mathrm {eff}}) , and integrated circuit quiescent current (IDDQ). Process-dependence factors are then extracted and classified to reveal the actual root cause of each cluster. The findings of this paper indicate the dual gate spacer, the source/drain (S/D) proximity, the S/D depth, and the S/D implant affect C\mathrm {eff} , R\mathrm {eff} , and IDDQ significantly, but the variation source of these parameters is the thickness of the dual gate spacer. Furthermore, impacts of the ON-state current ratio of N/P devices on delay and IDDQ of RO are examined by replacing dual spacers with single ones, the uniformity of implantation can be enhanced. Thus, the fluctuation of IDDQ is seven times reduced (from 252 to 37 nA) and RO characteristic can fit to designing target. [ABSTRACT FROM PUBLISHER]

Thin-body self-aligned InGaAs MOSFETs are fabricated on a III-V-On-Insulator structure on a silicon active substrate (III-V-OIAS). The p-type Si active substrate acts as a back gate that can modulate the threshold voltage and other electrical characteristics of the device. This paper explores the physics behind this effect through 2-D simulations and comparison with experiments. In the off-state, we find that the application of a positive body-to-source ( V\mathrm{ bs} ) voltage increases the subthreshold swing but reduces drain-induced barrier lowering. The first effect is related to the electron profile and the location of the centroid of electron charge in the channel while the second is closely associated with the modulation of a depletion region in the silicon substrate. In the on-state, the series resistance is observed to improve under positive V\mathrm{ bs} due to the increased accumulation of electrons in the extrinsic portion of the device. In addition, the channel mobility exhibits a two-branch behavior in its dependence on the average vertical electric field in the channel. This is explained by the different interfacial scattering that takes place at the front and back channel surfaces. This paper highlights the tradeoffs involved in attempting to exploit the body bias in the operation of QW-MOSFETs in III-V-On-Insulator with active substrate. [ABSTRACT FROM PUBLISHER]