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This Special Issue of the IEEE Transactions on Electron Devices will feature the most recent developments and the state of the art in the field of ultra wide band gap semiconductors and devices for power control and conversion, including both experimental results and theoretical developments. Papers must be new and present original material that has not been copyrighted, published or accepted for publications in any other archival publications, that is not currently being considered for publications elsewhere, and that will not be submitted elsewhere while under considerations by the Transactions on Electron Devices. Topics of interest include, but are not limited to: IDtra Wide Band Gap Materials: Advances in material synthesis, defect characterization, transport and high-field properties, and material-level integration; evaluation of fundamental materials-limited figures of merit; Power Devices: Vertical and lateral MOSFETs, HEMTs and MIS-HEMTs, IGBTs, Schottky and pn junction rectifiers, and other device concepts; fabrication and device characterization; designs and device structures for controlling field profiles, edge termination; Thermal Management: Approaches to mitigate thermal effects in power devices using ultra wide band gap materials; Integration: Monolithic and heterogenous integration for system-level applications using ultra wide band gap materials. Integration with Si or other semiconductors for system-on-chip and system-in-package implementations, including heterogenous and package-level integration for high-performance power conversion applications. [ABSTRACT FROM AUTHOR]

The dielectric screening property of a semiconductor is very crucial for the electrical characteristics of a MOSFET, and which can be described mathematically by Poisson equation via the permittivity. While the theory and experiments have corroborated the permittivity reduction of nanoscale Si, this paper studies the electrical characteristics of MOSFETs considering the reduced channel permittivity by quantum transport simulations. It is found that the channel permittivity reduction may mitigate the short-channel effects, showing subthreshold swing improvement and threshold voltage shift of MOSFETs in nanoscale. Compared to quantization effects, the positive and negative impacts of the channel permittivity reduction on the devices in particularly nanoscale have been investigated. This paper elucidates the necessity of considering semiconductor permittivity reduction for nanoscale device design and simulations. [ABSTRACT FROM AUTHOR]

It is well known that there is a critical Sn content for a GeSn alloy, at which the conduction band edges at ${L}$ and $\Gamma$ symmetry points are aligned in energy. For GeSn tunnel FET (TFET) simulations, with a given donor concentration, this paper reveals that simulations neglecting the multivalley and nonparabolic band structure would incorrectly predict the subthreshold slope (SS) and the off-currents. We highlight the indispensability of the consideration of the multivalley band structure of GeSn for TFET simulations. This paper provides the required parameters, which may be useful for numerical simulations of other optoelectronic and electronic GeSn devices. [ABSTRACT FROM AUTHOR]

This paper revisits the physics of current filamentation in grounded-gate NMOS (ggNMOS) devices and presents new physical insights which were not addressed in earlier works. A clear distinction between electrical and thermal instabilities is presented. Moreover, filament dynamics under electrical and thermal instability in both silicided and silicide blocked devices is discussed while highlighting observations which contradict with established theory of current ballasting. Interplay between electrical and thermal instabilities and its dependence on the presence or absence of silicide blocking is explored further. Filament spreading in ggNMOS devices and it is dependence on silicide blocking is discussed. Finally, while using the developed physical insights, missing correlation between TLP and HBM extracted failure current of silicided ggNMOS device is explained. [ABSTRACT FROM AUTHOR]

In this paper, we propose a vertical transistor with n-bridge and body on gate (BOG-DRAM) for Low-power 1T-DRAM application. The vertical channel of the device can reduce the short-channel effect and improve scalability. The storage region stacked on the gate leads to the efficient utilization of storage space. The device with junctionless channel layers on three sides can improve writing time. The conventional current bridge device only has one side gatecontrol depletion region, but the proposed BOG-DRAM has triple-side gate-control depletion region which can improve programming window at shorter gate lengths. BOG-DRAM achieves programming window of 33.6 μA/μm when the storage length is 20 nm. In addition, the work function offset is exploited for low-power application. [ABSTRACT FROM AUTHOR]

Motivation to study the ZnO channel for thin-film transistors (TFTs) is strong in light of its decent high mobility and large bandgap, enabling simultaneous coexistence of high on current and low off-state leakage. Nevertheless, the improvement in device performance for ZnO TFTs has not been fully exercised and even the field-effect mobility ( \mu \text {FE} ) is degraded with downscaling the channel length owing to considerable series source/drain (S/D) resistance ( R\text {SD} ). In this paper, we show that inserting a thin contact layer of ZnON between the ZnO channel and Al S/D effectively suppresses the formation of interfacial layer of AlOx and thereby reduces R \text {SD} dramatically. This is evidenced by a significant reduction in R \text {SD} from 30.1 to 14.4 \textk\Omega \cdot \mu \textm measured on 0.5- \mu \textm ZnO TFTs with a ZnON contact layer or not, leading to an improvement in \mu \text {FE} from 18.2 to 29.6 cm ^2/\text V\cdot \text s . [ABSTRACT FROM AUTHOR]

This paper examines the fundamental reliability differences between n-p-n and p-n-p SiGe HBTs. The device profile, hot carrier transport, and oxide interface differences between the two device types are explored in detail as they relate to device reliability. After careful analysis under identical electrical stress conditions for n-p-n and p-n-p, the differences in activation energies for the damage of the oxide interfaces of the two devices is determined to be the primary cause for accelerated degradation seen in p-n-p SiGe HBTs. An analytical model has been adapted for simulating these aging differences between p-n-p and n-p-n devices. This paper has significant implications for predicting the degradation of complementary SiGe HBTs and even engineering future generations with well-matched n-p-n and p-n-p device-level reliability. [ABSTRACT FROM PUBLISHER]

This paper presents a comparison of switching performances between the in-situ oxide, gallium nitride (GaN) interlayer FET (OG-FET) and the conventional GaN metal–oxide–semiconductor FET (MOSFET), and explores the influence of the channel electron mobility on the device switching performance. GaN OG-FET is a novel structure with a pristine GaN layer grown between the gate oxide and the p-GaN enhancing the channel mobility up to 185 cm2/ $\text {V}\cdot \text {s}$ , which is over $3{\times}$ larger than that of the typical reported value (50 cm2/ $\text {V}\cdot \text {s}$) in GaN MOSFET. Owing to the high channel electron mobility, the GaN OG-FET showed a switching loss 30% lower than that of the conventional GaN trench MOSFET. Our results indicate that GaN OG-FET has the potential to attain greater efficiency, particularly at higher frequencies, showing a possible patch toward megahertz range conversions. [ABSTRACT FROM AUTHOR]

In this paper, we present a charge-based compact model for transition metal dichalcogenide (TMD)-based thin-channel field-effect transistor. In model development, first, charge densities at the source and drain terminals are calculated in terms of the applied gate and drain voltages. Calculated charge densities are then used to develop a charge-based drain-current model. Effects of interface traps, ambipolar current behavior, and negative capacitance are then included in the developed drain-current model in terms of charge densities. Predictions of the proposed model are verified by the simulation and experimental data of the TMD channel material-based n-type and p-type MOSFETs. [ABSTRACT FROM AUTHOR]

Through numerical simulations corroborated by an analytical subthreshold model considering drain coupling, this paper systematically investigates the short-channel effects in negative-capacitance FETs with 2D MoS2 channel (2D-NCFET). Our study indicates that, due to the impact of drain coupling on the negative-capacitance effect, the 2D-NCFET exhibits distinct short-channel behaviors such as improved average subthreshold swing and threshold-voltage roll-up with decreasing gate length. In addition, the fringe field through the high-k interlayer dielectric can significantly alter the subthreshold characteristics of the short-channel 2D-NCFET, and hence needs to be carefully taken into account. Our study may provide insights for device design using negative-capacitance FETs. [ABSTRACT FROM AUTHOR]

A gate engineered InGaN dopingless tunnel FET (DL-TFET) using the charge plasma concept is proposed and investigated by silvaco Atlas simulation. In0.75Ga0.25N is a direct gap semiconductor, and the effective tunneling mass of electron and hole is smaller than that of silicon, which induces that the drain current and average subthreshold swing (SSavg) of InGaN DL-TFET improve 1.3 x 10² times and 51.1% than that of Si DL-TFET at the overdrive voltage of 0.5 V, respectively. What is more, better device performances are achieved by gate engineering with appropriate "In" fraction, proper space between the gate and source (Lgs), and appropriate tunneling gate work function (ΦTG). The direct-current, RF, and energy-efficient performance studies show that SSavg of 7.9 mV/dec, an on-state current (ION) of 8.02 x 10-5 A/µm, a cutoff frequency (fT) of 119 GHz, and an energy delay product of 0.64 fJ-ps/µm can be obtained in the proposed TFET. This paper indicates that the gate engineered InGaN DL-TFET is a promising TFET for low-power RF and digital logic applications. [ABSTRACT FROM AUTHOR]

This paper utilizes electrical analyses and a study of physical mechanisms to investigate metal gate structure-dependent performance in amorphous InGaZnO (a-IGZO) thin-film transistors. The effects of different shielding areas between the IGZO layer and metal gate are investigated. In devices with shorter metal gate lengths, an abnormal rise in capacitanceat the off-state in capacitance--voltage ( C-V) characteristic curves can be observed. This can be attributed to the stronger electric field induced by the edge of themetal gate under bias sweepwhen themetal gate length is shorter than the IGZO layer length. Light illumination measurements indicate a negative shift in threshold voltage and an increase in subthreshold-leakage current regardless of relative metal gate length. Moreover, negative threshold voltage shift becomes more severe with a more obvious hump in C-V characteristic curves under backlight illumination of a shorter width device, a phenomenon which has been verified by simulation. [ABSTRACT FROM AUTHOR]

This paper describes the separation between the area and the perimeter current density components of 4H-SiC vertical p+-i-n diode with a circular Al+ implanted emitter of different diameters in the range 150-1000 µmand for temperatures of measurement in the range 30-290 °C. It is shown that before the diode series resistances become dominant, the forward current is given by the sum of an area plus a perimeter component, both of exponential trend with ideality factor 2; while toward high voltages, an area componentwith exponential trend and ideality factor 1 adds to the previous components. Moreover, this paper shows that forward area and perimeter current density components can be used for a straightforward identification of the parameters controlling the current transport, provided that they can be fit by the p-n junction equations in the frame of the abrupt junction approximation. Finally, this paper shows that the area reverse current density can be used for the identification of the electrically active defects in the drift layer. [ABSTRACT FROM AUTHOR]

Due to high surface-to-volume ratio, surface traps play crucial role in electronic properties of semiconductor nanowires and nanowire-based devices. Recently, it was experimentally demonstrated that surface traps even can induce conductivity type inversion in semiconductor nanowires. Here, we have performed theoretical and numerical analyses to investigate the influence of surface traps on semiconductor nanowire conductivity including possible inversion due to surface traps. The Poisson equation with consideration of both type of mobile charges and ionized donors was solved having surface trapped charges in Neumann boundary conditions. Different semiconductor materials and surface trap densities have been considered. Calculations were done considering single energy level of surface traps and then the results were generalized to exponential energetic distribution of surface states density. The effect of surface traps was analyzed both for low-doped and highly doped nanowires. It was shown that for moderate or lightly doped NWs, the conductivity type switching from n- to p-type can occur at small radii. The developed potential-based analytical model allows calculating the inversion charge raised due to surface traps. The accuracy of analytical calculations has been validated with TCAD simulations and qualitatively compared with published experimental data. This paper is useful for design optimization of nanowire-based photodetectors, sensors, and reconfigurable FETs. [ABSTRACT FROM AUTHOR]

In contrast to the conventional planar p-i-n photodiode and a metal-semiconductor-metal photodetector, the 3-D dual-gate photosensitive thin-film transistor (TFT) architectures presented here attain excellent photoresponse characteristics. Operating the device in the subthreshold regime further boosts the photoconductive gain as a result of light-induced decrease in the threshold voltage. This paper presents design considerations along with a performance comparison between 3-D photosensitive TFTs that have π- and FIN-shaped channels and conventional TFT with a planar channel. Our paper shows that the π-shaped structure tends to have a higher sensitivity while the FIN-shaped counterpart is more responsive with wider dynamic range. For both structures, a measured photoconductive gain of 104~106% is obtained with spectral responsivity ranging from near UV to near IR, and the photoresponse time in the range of tens of milliseconds. The 3-D dual-gate photosensitive TFT architecture appears to be very promising for large-area, low-level UV, visible, and IR detection applications. [ABSTRACT FROM AUTHOR]

With the aid of an analytical and scalable model, this paper explores the design space for negative-capacitance (NC) field-effect transistors (FETs) with a 2D semiconducting transition-metal-dichalcogenide channel. In addition, the impact of back-gate biasing on the design space and the body effect of 2D-NCFETs is also investigated. Our study indicates that, to mitigate the conflict between subthreshold swing and hysteresis and to maximize the design space for the 2D-NCFET, a thin buried oxide and an adequate reverse back-gate bias can be applied to achieve the optimum design. [ABSTRACT FROM PUBLISHER]

In this paper, a highly sensitive linear high-temperature sensor based on a 4H-SiC p-i-n diode is introduced. The sensor offers both a very high sensitivity up to 4.5 mV/°C and a high linearity (coefficient of determination R^2 up to 99.96%) for temperatures varying from room temperature up to 460 °C. Both parameters, linearity and sensitivity, are current density dependent. The best tradeoff between linearity ( R^2 of 99.96%) and sensitivity (4.3 mV/°C) was found for an applied current density of 0.7~\mu \textA /cm $^{{2}} . The proposed type of sensor is suitable for being integrated, e.g., into a smart high-voltage switch. Furthermore, the current transport mechanisms from room up to higher temperatures deduced from the I – V characteristics are discussed, leading to the conclusion that recombination currents are predominant for a wide range of applied current densities. Thus, the increase in the intrinsic carrier concentration dominates the temperature dependence of the saturation current density. If required, applications at even higher temperatures are possible from the semiconductor point of view. But in this case, further optimizations of the manufacturing process for usability for this temperature range are recommended and discussed. [ABSTRACT FROM PUBLISHER]

FETs made on 2-D semiconductors, typically without degenerate doping at the contacts, have a significant Schottky junction (SJ) resistance, which complicates transistor analysis. This paper evaluates the effect of the contact resistance on the 2-D-material FET characteristics through four-terminal (4-T) resistance measurements on WSe2 FETs, which allow studying the channel and contacts characteristics separately. Apart from showing the nonnegligibility of contact resistance, this paper enables a finer understanding of commonly observed phenomena, such as transistor performance improvement with dielectric-encapsulation is observed to have a stronger effect on the contact than the channel; the resistance of the forward-biased SJ is observed to be not negligible, but comparable to that of the reverse-biased junction; at biases commonly referred to as “low-bias,” the WSe2 FET resistance could be dominated by the contacts; and pinchoff can be observed at relatively lower current levels, being related to the channel-contact resistance ratio rather than their magnitudes. In the devices where true channel pinchoff can be verified, a correlation emerges between current saturating behavior and asymmetry in the output characteristics with respect to the drain–source bias polarity, a feature that may serve as a guide toward interpreting standard FET output characteristics in 2-D materials. [ABSTRACT FROM PUBLISHER]

The global optimization of the balanced symmetric vertical superjunction (VSJ) device is proposed based on the R-well model for the first time to realize the unique minimum specific on-resistance $R_{{\mathrm{\scriptscriptstyle ON},\mathrm {min}}}$ . The R-well model, which is originated from our previous VSJ mode theory, shows the relationship between $R_{{\mathrm{\scriptscriptstyle ON}}} and the doping concentration N under the given pillar width W and breakdown voltage VB . The global R{\mathrm{\scriptscriptstyle ON}} optimization is realized to obtain the design formulas of N and the pillar length Ld . The calculated results are in good agreement with the simulations. It is demonstrated from the comparisons with the simulations and the existing experiments that the optimization in this paper realizes the unique $R_{{on,\mathrm {min}}}$ with a relationship of $R_{{\mathrm{\scriptscriptstyle ON}}}\propto V_{B}^{1.03}$ . The R-well model is also universal for other R_{on} optimizations. [ABSTRACT FROM AUTHOR]

Foldable displays represent one of the most attractive next-generation display applications. Therefore, it is critical to analyze the effects of mechanical stress on amorphous InGaZnO (a-IGZO) thin-film-transistors (TFTs) in order to apply them to foldable displays. In foldable display applications, the dynamic mechanical stress tests are designed to be carried out using a bending radius of less than 3 mm. In this paper, dynamic mechanical bending stress tests are performed on a-IGZO TFTs using various bending radii and directions in order to examine the instability characteristics of the TFTs. In addition, the degradation mechanisms are investigated using a technology computer-aided design simulation. As a result, we have demonstrated that it is now possible to establish reliable circuit guidelines for using a-IGZO TFTs in foldable display applications. [ABSTRACT FROM PUBLISHER]

This paper presents an analytical model of drain current in a silicon tunnel FET with a circular gate (CG TFET). The method involves the bifurcation of the complete geometry into a rectangular gate conventional TFET, and the CG TFET itself based on the number of solvable regions of the CG TFET. The 2-D Poisson equation is solved on the regions of focus of each structure, and both the substructures are mathematically connected through conditions of continuity to arrive at the solution for the original geometry. The effect of the circular gate is considered by segregating the circular region into a number of rectangular segments, and solving the Poisson equation on each of them. The model takes into account the effect of drain on channel potential, bandgap narrowing, and quantum correction. The model is validated by comparing the results with outputs from a TCAD simulation tool. [ABSTRACT FROM PUBLISHER]

High-performance ambipolar chemical sensors toward electron-detonating NH3 and electron-accepting NO2 are obtained based on the solution-based films of two ambipolar (${p}$ -fluoro)phenoxy substituted tris(phthalocyaninato) rare earth semiconductors with different metal ions, named Gd2 [Pc(OPhF)8]3(1) and Tb2 [Pc(OPhF)8]3(2). Measurements over the films fabricated from 1 and 2 by a simple quasi-Langmuir–Shäfer (QLS) method reveal their ambipolar semiconductor nature, with a ${p}$ -type response in NH3 sensing and n-type response in NO2 sensing, associated with not only suitable highest occupied molecular orbital and lowest unoccupied molecular orbital energy levels but also the different electronic induction effects of the analytes. Interestingly, the devices from the QLS film of 2 with a weaker intermolecular $\pi $ – $\pi $ stacking in J-type (edge-to-edge) packing mode display much better sensing properties to both NH3 and NO2, compared to those from QLS film of 1 with a stronger intermolecular $\pi $ – $\pi $ stacking in the H-type (face-to-face) packing mode. This is mainly because of the larger specific surface area from the J-aggregate with the more uniform-sized nanoparticles for the QLS film of 2. In particular, the highly sensitive, stable, and reproducible responses to 1–20-ppm NH3 with a limit of detection of 0.15 ppm only in 1 min are obtained from the QLS film of 2 for the first time. This paper unravels, first, the effect of central metal ions of sandwich triple-deckers on molecular stacking mode, film structure, and gas sensing performances, which would be helpful for designing and preparing high-performance ambipolar gas sensor devices by combining the molecular design and the device fabrication technique. [ABSTRACT FROM AUTHOR]

The effects of the internal gain originated from the trapping of minority carriers and illumination-induced stored charges have been investigated systematically in MgZnO metal–semiconductor–metal (MSM) photodetectors (PDs) by a proposed semianalytical equivalent circuit model with the basic semiconductor equations and the external parasitic elements taken into account. To verify the accuracy and effectiveness of this model, the simulated steady and transient results are compared with the reported experimental data. It is found that a fall time of 400 ns, much longer than the response time with no internal gain, is attributed to the hole trapping process, inducing an internal gain with a value of 181. In addition, for the high input optical pulse energy (above 10 pJ), the time-delay of the response is caused by the stored charges. This paper indicates that it is very important to improve the MgZnO thin-film quality and balance the optical gain with the response speed. Meanwhile, a reasonable compromise should be found between the energy level of the optical pulse and the bias voltage to minimize the stored charges effect for practical applications. This paper is helpful for the design of high-speed and high-power MgZnO MSM PDs. [ABSTRACT FROM AUTHOR]

Polymer FETs generally have a wide subthreshold regime due to a lot of disorder, mainly originated from domain/grain boundaries. Deep state’s charge transport of polymer transistors has not been investigated due to the difficulty in determining the field-effect mobility in the subthreshold region. In this paper, the features of the charge transport in deep and shallow states of polymer transistors will be discussed in detail through an accurate modeling and an analysis of subthreshold behavior in transistors. Charge transport in shallow states can be described by multiple trap and release transport, while hopping transport models, such as variable range hopping or Gaussian disorder-based model, describe well the deeper state’s charge transport. In addition, the transition between the conduction regimes is a function of temperature and carrier density. [ABSTRACT FROM PUBLISHER]

This paper concerns superjunctions which employ oxide layers for isolating n- and p-pillars and in terminating the device. In our earlier work, we pointed out that oxide fixed charges significantly reduce the breakdown voltage of such devices. In this paper, we discuss various techniques in compensating the effects of oxide fixed charge so as to design such a device having the minimum specific on-resistance for a given breakdown voltage. The techniques include doping modification and reduction in the widths of terminating pillars and nonconducting pillars in the ON-state. We also analyze the relative contributions of oxide fixed charges and doping-related charge imbalance to breakdown reduction to highlight the significance of oxide fixed charges. [ABSTRACT FROM AUTHOR]

An aging effect in solid-state image sensors is studied: the generation of hard errors resulting in hot spots, warm pixels, or white pixels. These effects even occur in image sensors that are simply stored on the shelf. This paper describes experiments that are set up to prove that the main origin can be found with neutrons that create displacement damage in the silicon bulk. These neutrons are part of terrestrial cosmic rays. This statement is based on measurements done on devices that we stored on the shelf, that were flown around the world in airplanes, that were stored at high altitude, and that were stored in an underground laboratory. The creation of the hot spots is independent of technology, architecture, sensor type, or sensor vendor, and it is observed in charge-coupled devices as well as in complementary metal-oxide-semiconductor image sensors. In other words, it is a typical issue of the semiconductor base material: silicon! The paper is split up into two parts: this paper (part 1) describes the experiments done at room temperature, part 2 will concentrate on experiments done at higher temperatures. [ABSTRACT FROM AUTHOR]

A new Pd nanoparticle (NP)/Pd film/GaOx/GaN-based metal–oxide–semiconductor diode hydrogen sensor is fabricated and studied. In this paper, appropriate photochemical drop coating and an H2O2 surface treatment were used to form Pd NPs and a GaOx dielectric layer. The Pd NPs increased the surface area/volume ratio, and the presence of GaOx layer led to the effective dissociation of hydrogen molecules. The improved hydrogen sensing properties include a very high sensing response of $1.24 \times 10^{{7}}$ (in 1% H2/air gas at 300 K) and an extremely low detection level (${\le} 1$ ppm H2/air). Furthermore, based on a kinetic adsorption analysis, the activation energy was only 13.1 $\text {KJ}\cdot \text {mol}^{-{1}}$ that is beneficial for hydrogen sensing. The proposed device is therefore promising for high-performance hydrogen sensing applications. [ABSTRACT FROM AUTHOR]

Full-band atomistic quantum transport simulations based on first principles are employed to assess the potential of band-to-band tunneling FETs (TFETs) with a 2-D channel material as future electronic circuit components. We demonstrate that single-layer (SL) transition metal dichalcogenides are not well suited for TFET applications. There might, however, exist a great variety of 2-D semiconductors that have not even been exfoliated yet; this paper pinpoints some of the most promising candidates among them to realize highly efficient TFETs. SL SnTe, As, TiNBr, and Bi are all found to ideally deliver ON-currents larger than 100 $\mu \text{A}/\mu \text{m}$ at 0.5-V supply voltage and 0.1 nA/ $\mu \text{m}$ OFF-current value. We show that going from single to multiple layers can boost the TFET performance as long as the gain from a narrowing bandgap exceeds the loss from the deteriorating gate control. Finally, a 2-D van der Waals heterojunction TFET is revealed to perform almost as well as the best SL homojunction, paving the way for research in optimal 2-D material combinations. [ABSTRACT FROM AUTHOR]

Sub-bandgap (SBG) impact ionization (II) enables steep subthreshold slope that enable devices to overcome the thermal limit of 60 mV/decade. This phenomenon at low voltage enables various applications in logic, memory, and neuromorphic engineering. Recently, we have demonstrated sub-0.2-V II in n-i-p-i-n diode experimentally primarily based on steady-state analysis. In this paper, we present the detailed experimental transient behavior of SBG-II in n-i-p-i-n. The SBG-II generated holes are stored in the p-well. First, we extract the leakage mechanism from the p-well to show two mechanisms: 1) recombination–generation and 2) over the barrier (OTB), where OTB dominates when barrier height ${\phi }_{b}<\textsf {0.59}~\textsf {eV}$. Second, we analytically extract the SBG-II current (${I}_{\textsf {II}}$) at 300 K from the experimental results. The drain current (${I}_{D}$), electric field (${E}{-}\textsf {field}$), and ${I}_{\textsf {II}}$ are plotted in time. We observe that ${I}_{\textsf {II}}$ increase as ${E}{-}\textsf {field}$ reduces which indicates that ${E}$ -field does not primarily contribute to ${I}_{\textsf {II}}$. Furthermore, ${I}_{D}$ shows two distinct behaviors: 1) ${I}_{\textit {II}} ({I}_{D}$) is constant at the beginning and 2) eventually “universal” ${I}_{\textsf {II}} ({I}_{D}$) is linear, i.e., ${I}_{\textsf {II}}={k}\times {I}_{D}$ where ${k} = \textsf {1}\textsf {0}^{-\textsf {3}}$ ; we also show that the electrons primarily contributing to ${I}_{D}$ are directly incapable of II due to insufficient energy ($< {E}_{g}$). Fischetti’s model showed that SBG-II is primarily caused by “hot” electrons that accept energy in an Auger-like process from “cold” drain electrons to enable SBG-II. We speculate that if ${I}_{D}$ electrons “heat-up” the cold drain electrons, which would further energize the hot electrons to produce the observed ${I}_{\textsf {II}}{(}{I}_{D}$) universal dependence. [ABSTRACT FROM AUTHOR]

In this paper, we investigated the influence of both source gas and deposition temperature in plasma-enhanced chemical vapor deposition (PE-CVD) for a SiO2 passivation layer on the electrical properties and reliability of a bottom-gate In–Ga–Zn–O thin-film transistor (IGZO TFT). Two gas chemistries consisting of SiH4–N2O–N2 and tetraethoxysilane (TEOS)–O2 were utilized as the source gases for the PE-CVD SiO2 deposition, and the deposition temperature (${T}_{D}$) was adjusted from 180 °C to 380 °C. The TFT properties were basically identical for both gas chemistries at ${T}_{D}$ of 180 °C. When ${T}_{D}$ increased to 300 °C or higher, the TFTs with the SiO2 passivation deposited by SiH4–N2O–N2 gas chemistry (SiH4-SiO2) drastically changed from the transistor to the conductor. In contrast, the TFT with TEOS-SiO2 passivation maintained its TFT characteristics even at ${T}_{D}$ of 380 °C, despite the degradation of subthreshold characteristics and a negative shift of turn-on voltage were observed due to an electron injection barrier lowering as ${T}_{D}$ increased to 310 °C or higher. We also revealed that a stacked SiO2 passivation that is deposited at a different ${T}_{D}$ is an effective technique to improve the performance and reliability of the IGZO TFT. [ABSTRACT FROM AUTHOR]

Resistive random access memory is known as a type of nonvolatile memory. An abnormal volatile memory characteristic of a normal ZnSnO resistive memory is first demonstrated in this paper. Although the ${I}$ – ${V}$ curves exhibit a normal and stable resistive switching memory behavior, the resistance state is found to be only determined by the initial applied voltage along with the voltage sweep direction. It is set/reset processes free. Namely, it is volatile. The resistance states are found to be dominated by trap-assisted tunneling, trap-controlled space-charge-limited conduction, and hopping transport. Different resistance states are related to different carrier transport mechanisms. Each resistance state can independently and repeatably appear for over 1000 voltage sweeps. The ratio of the high-resistance state to the low-resistance state is $\sim 3\times 10^{2}$. [ABSTRACT FROM AUTHOR]

In this paper, design of an ultracompact bandpass filter (BPF) in GaAs technology without compromising its electrical performance is investigated by means of both theoretical analysis and electromagnetic simulation. In particular, the relationship between the external quality factor and the coupling coefficient of the second-order BPF is formulized to better understand the principle of the mutual coupling effect. To prove the concept, the designed filter is implemented in a commercial 0.1-µm GaAs technology. A step-by-step design guideline is elaborated. The BPF has not only the merits of ultracompactness, but also remarkable insertion loss (IL) compared with other state-of-the-art on-chip designs. The measurement results show that the 1-dB bandwidth of the BPF is from 28 to 36 GHz, while the IL is less than 1 dB at 29.5 GHz. In addition, more than 40-dB rejection is achieved from 56 to 69 GHz. The size of the filter is only 230 x 280 µm², excluding the pads, which is equivalent to 0.074 x 0.09 λg² at 28 GHz. To the best of our knowledge, the proposed design is known to be the most compact one in the open literature using GaAs technologies. [ABSTRACT FROM AUTHOR]

Write-once-read-many-times (WORM) characteristics of sol-gel InZnO (IZO) thin films are investigated in this paper. The Ag/IZO/n+-Si WORM memory exhibits a poor read disturb immunity. Although a postannealing process is capable of improving the performance due to formation of a thin interfacial AgxO layer, the memory window is only 5 x 10² and the resistance in high resistance state degrades dramatically during read disturb testing. By replacing the Ag electrode with an Al electrode, without the postannealing process, the Al/IZO/n+-Si WORM memory shows a superior read disturb immunity and a large memory window of 4 x 10³. The read endurance is over 104 cycles. X-ray diffraction, X-ray photoelectron spectroscopy, transmission electron microscopy, and energy dispersive spectroscopy were utilized to investigate the physical mechanisms of the WORM characteristics. The carrier conduction mechanisms were also explored. [ABSTRACT FROM AUTHOR]

An extensive investigation of fabricated AlGaN/GaN fin-shaped metal-insulator-semiconductor high-electron-mobility transistors (Fin-MISHEMTs) with Al2O3 dielectric is presented in this paper. Based on the pulsed I-V measurements and numerical simulation, the dynamic characteristics of GaN-based Fin-MISHEMTs were carried out under various quiescent bias conditions and temperatures. Moreover, the physical mechanisms of current collapse and dynamic on-resistance increase induced by trapping effects were analyzed. The results show that the observed nonmonotonic variation of current collapse with the gate quiescent bias voltage is resulted from the combination of gate leakage injection-related and hot-electron injection-related trapping effects. Compared with the conventional planar MISHEMTs, the current collapse of AlGaN/GaN Fin-MISHEMTs is smaller due to lower gate leakage and smaller threshold voltage shift, which is benefited from its enhanced gate controllability. The current collapse and dynamic on-resistance increase of Fin-MISHEMTs can be further suppressed by optimizing the device structure, such as designing the fin channels only under the gate. [ABSTRACT FROM AUTHOR]

In the last years,memristor devices have been proposed as key elements to develop a new paradigm to implement logic gates. In particular, the memristor-based material implication (IMPLY) gate has been presented as a potential powerful basis for logic applications. In the literature, the IMPLY operation has been widely simulated, but most of the efforts have been just focusedon accomplishing its truth table, only considering the initial and final states of the gate. However, a complete understanding of the time evolution between states is stillmissing and barely reported yet. In this paper, the time evolution of the memristors involved in an IMPLY gate are studied in detail for every case of the gate. Furthermore, the impact on IMPLY gate operation of the internal resistor connected in series with the memristors of the IMPLY gate is included. [ABSTRACT FROM AUTHOR]

The article discusses various reports published within the issue, including one by Koo on giga-scale on-chip global interconnect technologies, another by Kurokawa on interconnect modeling, and another by Zhao on on-chip interconnect.

Nanowire transistors are typically fabricated as geometrically symmetrical devices, with metal/semiconductor source and drain contacts rather than a graduated doping profile. While the source and drain contacts are nominally identical, contact asymmetry can arise when the gate contact is not centered over the nanowire, leaving uneven access regions with no gate coverage on one or both sides of the channel. Measuring the characteristics of devices with symmetric and asymmetric contact geometries allows contact effects to be studied. In this paper, indium arsenide nanowire transistors were fabricated with symmetric and asymmetric gate coverage. It is shown that devices with highly asymmetric gate coverage can exhibit a factor of 10 change in current and a shift in threshold of up to 0.5 V upon reversing the source–drain orientation. Devices with highly asymmetric properties show nearly identical channel-generated noise yet a significant difference in contact-generated noise levels when the contact orientation is reversed. Fully symmetric devices show higher current levels, lower threshold voltages, and lower contact-generated noise than asymmetric devices with either source or drain gated, but channel-generated noise levels are similar. [ABSTRACT FROM PUBLISHER]

In this paper, we have demonstrated an oxygen-vacancy-based bipolar RRAM on a pure logic 14-nm-node HKMG FinFET platform. A unit cell of the memory consists of a control transistor (FinFET) and a storage transistor (a second FinFET). The later performs as a bipolar RRAM. This unit cell can be integrated in an AND-type memory array. The memory cell has an ON/OFF ratio equal to 200 and 400 for the n-type and p-type FinFET RRAMs, respectively, endurance larger than 400 and 1000 times for n- and p-type devices, respectively, and the retention test for over 1 month under 125°C temperature environment. To analyze the array performance of the AND-type FinFET RRAM at the circuit level, we have further discussed the issues of the sneak path and disturbance, in which an active-fin isolation of FinFET in an AND-type array has been suggested to minimize the leakage current induced by sneak paths. The results have shown a large window with up to 103 ON/OFF ratio, 30% standby power reduction, and 90% active power reduction with reference to the conventional AND-type array. As a result, the bipolar FinFET RRAM exhibits great potential for the embedded memory applications, in particular it can be extended to 28-nm HKMG and the FinFET platform beyond 14-nm technology node, to fill the Moore's gap between the high-performance logic and the embedded memory. [ABSTRACT FROM AUTHOR]

Characteristics of deep-ultraviolet (DUV) light-emitting diodes (LEDs) are investigated. DUV LEDs possess severe electron current leakage due to insufficient carrier confinement of the active region. Simply increasing the Al composition of quantum barriers (QBs) or electron-blocking layer (EBL) to enlarge the relevant potential barrier height would arise unexpected detrimental effects, such as extra polarization effect or more obstruction for hole injection. In this paper, band-engineered composition-graded QBs and EBL are proposed to resolve this issue. Simulation results show that, with appropriate designs, the leakage current of DUV LEDs could be effectively diminished with just slight side effects. [ABSTRACT FROM AUTHOR]

This paper proposes a pull-up control scheme in the pseudo-CMOS inverter to design a low-power ring oscillator (RO) realized by only n-type transistors. For comparing 11-stages, the proposed RO and the conventional RO are both fabricated by metal-oxide thin-film transistors with the etch stop layer structure. It is measured that the power-delay product of the proposed RO is reduced by more than 50% under the same value of supply voltage. At the same oscillation frequency, the power consumption tends to be reduced by 18% as oscillation frequency increases. Furthermore, the peak-to-peak voltage of the proposed RO can almost receive a full swing at any supply voltage. [ABSTRACT FROM AUTHOR]

In this paper, an analytical model of insulated gate bipolar transistor (IGBT) on-state voltage ( V\mathrm {{ {{ON}}}} ) and turn-off loss ( E\mathrm {{ {{OFF}}}} ) is developed to find the optimum solution (minimum power loss) for a given application. With this model, it is found that IGBT on-state voltage is limited by the fact that holes can only flow from the anode to the cathode. The minimum on-state voltage for a Si IGBT with 110- \mu \textm wide drift region is found out to be around 0.835 V at 100 A/cm2 and room temperature. For a given operating frequency and chip size, a tradeoff between on-state voltage and turn-off loss that gives minimum device power loss can be achieved by manipulating the carrier profile in the drift region with an optimum structure design. This minimum device loss decreases mildly with increasing chip size, i.e., a merely 45% loss reduction when the chip size increases from 0.2 to 5 cm2. These results clearly indicate that the performance of an IGBT is not area sensitive. They are encouraging for device manufacturers who wish to reduce the device chip size to lower cost. However, the constraint comes from the device thermal dissipation capabilities which decrease quickly with decreasing chip size. These results are validated with numerical 2-D device simulations for a large variety of device structures, chip size, and operating frequencies (2 to 200 kHz). State-of-the-art IGBT product performance is compared against the theoretical limit indicating there is still substantial room for improvement at low and high frequencies. [ABSTRACT FROM PUBLISHER]

In this paper, we study for the first time the impact of the design of gate sidewall spacer on the gate-induced drain leakage (GIDL) of: 1) the conventional nanowire (NW) FETs and 2) NWFETs with a gate–source/drain extension underlap. We demonstrate that the inclusion of a high- $\kappa $ spacer over the source/drain extension region in the conventional NWFETs results in a suppressed lateral band-to-band tunneling (L-BTBT) GIDL. Furthermore, we also show that a gate–source/drain extension underlap architecture in NWFETs not only reduces the transverse BTBT GIDL but also mitigates the L-BTBT. However, the inclusion of a high- $\kappa $ spacer in the underlapped NWFET leads to an enhanced L-BTBT and an increased OFF-state current compared with the underlapped NWFET with air spacer unlike FinFETs. In addition, we also study the impact of nanowire diameter and underlap length on L-BTBT GIDL of NWFETs. Furthermore, we demonstrate that the inclusion of the high- $\kappa $ spacer increases the intrinsic delay owing to an increased fringe capacitance. Therefore, we provide the necessary design guidelines for performance optimization of NWFETs in the sub-10-nm regime. [ABSTRACT FROM PUBLISHER]

In this paper, a dielectric-pocket double-gate MOSFET is described for low-voltage low-power applications. A complete drain current model has been developed including the channel length modulation effect. The analytical results have been validated by comparing them with the simulation results using the ATLAS 3-D device simulator. This paper analyzes the impact of dielectric pillars on large-signal performance metrics in terms of linearity and digital performance. Due to high Ion/Ioff ratio, device gain, and extremely low value of intrinsic delay and power dissipation, the proposed design is a suitable candidate for low-voltage low-power digital and analog applications. [ABSTRACT FROM PUBLISHER]

Thin-film transistors (TFTs) fabricated using solution-processed zinc–tin-oxide (ZTO) semiconductor thin films as the channel layers are proposed in this paper. Effect of the ZTO annealing temperature on the TFT performance is studied. Significant reduction of oxygen-vacancy and chlorine residue contents in the ZTO semiconductor can be obtained when the annealing temperatures are 500 °C–700 °C. The ZTO semiconductor with the annealing process at 600 °C in air can give an optimal ZTO TFT having a low leakage current of 10−12 A and a high ${I}_{ \mathrm{\scriptscriptstyle ON}}/{I}_{ \mathrm{\scriptscriptstyle OFF}}$ ratio of 3 $\times \,\,10^{7}$. The subthreshold swing is 0.39 V/decade corresponding to an interface trap density of $1.2\times \,\,10^{12}\,\,$ cm−2eV−1. [ABSTRACT FROM AUTHOR]

In this paper, the electron transport properties of a C3N nanoribbon-based field-effect transistor (FET) in the ballistic regime have been simulated. Using the density-functional theory (DFT) to obtain the band structures, we found that the armchair-edged C3N nanoribbons are semiconductors, and their bandgaps are determined by their widths, while the zigzag-edged ribbons present the metallic properties. We have carried out calculations to study the transport properties of armchair-edged C3N nanoribbon by using DFT combined with the nonequilibrium Green’s function. Our simulation results revealed that both bandgap and current on/off ratio are reduced as the width increasing. Moreover, the gate length, channel length, and ribbon’s width are found to have prominent influences on the transfer characteristics. The armchair-edged C3N nanoribbon-based FETs have the highest current on/off ratio of 106 and the ideal subthreshold swing of 61.2 mV/dec, which make it promising for potential applications of FET. [ABSTRACT FROM AUTHOR]

In this paper, a tunable acid-resistant Zr-doped indium oxide (ZrInO) semiconductor material was developed. Detailed studies showed that the acid resistance of ZrInO thin films is tunable and increases with the increase in annealing temperature. Taking advantage of this special property, we successfully fabricated back-channel-etched (BCE) thin-film transistors (TFTs) based on the tunable acid-resistant ZrInO thin film. ZrInO-TFTs with BCE structure exhibited excellent electrical performance with a saturation mobility of 21.4 cm $^{\textsf {2}}\textsf {V}^{-\textsf {1}}\textsf {s}^{-\textsf {1}}$ , a subthreshold swing of 0.28 V/decade, and an ON/OFF current ratio of $1.0\times107$. These results envision that the developed ZrInO semiconductor with tunable acid resistance has a good prospect for the channel layer of BCE-TFTs. [ABSTRACT FROM AUTHOR]

Considering the demand of III–V multigate (MUG) transistors for next-generation CMOS technologies, a compact model is required to test their performance in different circuits. The low effective mass and highly confined geometry of these MUG devices demand the use of computationally expensive coupled Poisson–Schrödinger (PS) solver for terminal charges and surface potential. In this paper, we propose an approximation, which decouples the PS equations and enables the development of a computationally efficient analytical model. The surface potential and semiconductor charge equations for III–V low effective mass channel cylindrical nanowire (NW) transistors are derived using the proposed approximation. The proposed model is physics-based and does not include any empirical parameters. The accuracy of the model is verified across NWs of different sizes and materials using the data from the 2-D PS solver and found to be accurate. [ABSTRACT FROM AUTHOR]

This paper describes the difference between normal microlenses and zero-space microlenses in image sensors. The investigation of both sensitivity and crosstalk has been implemented for normal microlenses and zero-space microlenses that are fabricated on a 2.8-µm pinned photodiode array of 640 (row) by 480 (column) based on an 0.18-µm-CMOS process. The simulation results show that the zero-spacemicrolens technology increases the pixel sensitivity by about 75.61% and decreases the crosstalk by about 9.4% compared to the normal microlens technology. This paper presents the sensitivity analysis of both normal microlenses and zero-space microlenses based on the wafer test data from the Teradyne IP750, which is a special wafer test platform for CMOS sensors. The results of the statistical data of the wafer test show that the sensitivity of the zero-space microlenses has been improved by about 73.6% on the red pixel (69.6% on the green pixel and 76.3% on the blue pixel) compared with that of the normal microlenses. Using a similar statistical method, the crosstalk characteristics of both the zero-space microlenses and the normal microlenses have been measured as well. Compared with the normal microlenses, the testing results show that the crosstalk of green light in red light is reduced by about 7.244% and the crosstalk of blue light in red light is reduced by about 41.447% due to the use of the zero-space microlens technology. More importantly, this paper also provides the comparison and analysis of the real images taken by CMOS image sensors with the normal microlenses and the zero-space microlenses, respectively. From the comparison of image results, the image luminance of the zero-space microlenses is higher than that of the normal microlenses, and the image definition of the zero-spacemicrolenses is clearer than that of the normal microlenses as well. So far, the silicon results show that the zero-space microlens technology is a better choice than the normal microlens technology for CMOS image sensors of a small-size pixel. [ABSTRACT FROM AUTHOR]

The scaling analysis of phase-change memory (PCM) cells is an essential step toward validation as a competitive technology in terms of array density and current consumption. While the current scaling has been addressed in a companion paper, we focus here on the thermal crosstalk, namely, the temperature increase in 1 bit in the array while an adjacent cell is being programmed by a high-current reset pulse. This parasitic heating may lead to partial crystallization in the amorphous phase and to a consequent resistance decrease after cycling. Our analysis shows that the thermal crosstalk strongly depends on the scaling approach used, e.g., isotropic or nonisotropic scaling. A new mixed-scaling option for PCM cells is proposed, which provides the maximum decrease of programming current compatible with the reliability requirements deriving from the thermal crosstalk. The effects of this new scaling approach on the programmed volume and data retention are finally addressed. [ABSTRACT FROM AUTHOR]

This paper presents a circuit-compatible compact model for the intrinsic channel region of the MOSFET-like single-walled carbon-nanotube field-effect transistors (CNFETs). This model is valid for CNFET with a wide range of chiralities and diameters and for CNFET with either metallic or semiconducting carbon-nanotube (CNT) conducting channel. The modeled nonidealities include the quantum confinement effects on both circumferential and axial directions, the acoustical/optical phonon scattering in the channel region, and the screening effect by the parallel CNTs for CNFET with multiple CNTs. In order to be compatible with both large- (digital) and small-signal (analog) applications, a complete transcapacitance network is implemented to deliver the real-time dynamic response. This model is implemented with an HSPICE. Using this model, we project a 13 times CV/I improvement of the intrinsic CNFET with (19, 0) CNT over the bulk n-type MOSFET at the 32-nm node. The model described in this paper serves as a starting point toward the complete CNFET- device model incorporating the additional device/circuit-level nonidealities and multiple CNTs reported in the paper of Deng and Wong. [ABSTRACT FROM AUTHOR]