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Flexible, highly sensitive, easy fabricating process, low-cost pressure sensors are the trend for flexible electronic devices. Despite the tremendous progress in recent years, it is still challenging to prepare pressure sensors with high sensitivity, high stability, and fast responsiveness. In this study, we report a simple and low-cost method for the preparation of novel pressure sensors. Inspired by the pomegranate structure, a 3-D porous structure consisting of polystyrene (PS) microspheres filled with reduced graphene oxide (rGO) paper is proposed. This pressure sensor has high linear sensitivity (1.41 kPa−1 in the pressure range of 0–50 kPa), high stability (1000 cycles), and quick response time (~20 ms). Furthermore, a robotic arm interacting control system based on pressure sensor arrays is constructed, which demonstrates the far-reaching potential of pressure sensors in human–machine interaction. Therefore, this work provides a low-cost and effective method for preparing high linear sensitivity pressure sensors. [ABSTRACT FROM AUTHOR]

Technology computer-aided design (TCAD) is an integral part of the development process of semiconductor technologies and devices, a field which has become increasingly complex and heterogeneous. Processing of integrated circuits requires nowadays over 400 process steps, and the resulting devices often have an intricate 3-D structure and contain various specifically designed materials. The full device behavior can only be understood by considering effects on all length scales from atomistic (material properties, interfaces, defects, and so on), to nanometric (quantum confinement, non-bulk properties, tunneling, ballistic transport, and so on), to full-chip dimensions (strain, heat transport, and so on), and time scales from femtoseconds (scattering, ferroelectric switching time, and so on) to seconds (trapping times, degradation, and so on). Voltages, currents, and charges have been scaled to such low levels that statistical effects and process variations have a strong impact. Devices based on new materials (e.g., 2-D crystals) and physical principles (ferroelectrics, magnetic materials, qubits, and so on) challenge standard TCAD approaches. While the simulation methods developed by the physics community can describe the basic device behavior, they often lack important simulation capabilities like, for example, transient simulations or integration with other TCAD tools, and are often too slow for daily use. Due to the complexity of semiconductor technology, it becomes more and more difficult to assess the impact of a change in processing or device structure on circuit performance by looking at a single aspect of an isolated device under idealized conditions. Instead, a TCAD tool chain is required which can handle realistic device structures embedded in a chip environment. New methodologies are required for all aspects of TCAD to ensure an efficient tool chain covering from atomistic effects to circuit behavior based on flexible simulation models that can handle new materials, device principles, and the ensuing large-scale simulations and that make use of artificial intelligence for well-chosen (sub)routines to decrease the overall simulation time. This Special Issue features six invited and 18 regular papers that address these problems. [ABSTRACT FROM AUTHOR]

These instructions give guidelines for preparing papers for this publication. Presents information for authors publishing in this journal. [ABSTRACT FROM AUTHOR]

These instructions give guidelines for preparing papers for this publication. Presents information for authors publishing in this journal. [ABSTRACT FROM AUTHOR]

These instructions give guidelines for preparing papers for this publication. Presents information for authors publishing in this journal. [ABSTRACT FROM AUTHOR]

Presents the table of contents for this issue of the publication. [ABSTRACT FROM AUTHOR]

Over the past 10 years, 3-dimensional (3-D) wafer-level stacked backside Illuminated (BSI) CMOS image sensors (CISs) have undergone rapid progress in development and performance and are now in mass production. This review paper covers the key processes and technology components of 3-D integrated BSI devices, as well as results from early devices fabricated and tested in 2007 and 2008. This article is divided into three main sections. covers wafer-level bonding technology. covers the key wafer fabrication process modules for BSI 3-D wafer-level stacking. presents the device results. [ABSTRACT FROM AUTHOR]

The evolution of CMOS image sensors and their prospects using advanced imaging technologies are promising candidates to improve the quality of life. With the rapid advent of parallel analog-to-digital converters (ADCs) and back-illuminated (BI) technology, CMOS image sensors currently dominate the market for digital cameras, and stacked CMOS image sensors continue to provide enhanced functionality and user experience in mobile devices. This article reviews the latest achievements in stacked image sensors with respect to the evolution of image sensor architecture for accelerating performance improvements, extending sensing capabilities, and integrating edge computing with various stacked device technologies. [ABSTRACT FROM AUTHOR]

These instructions give guidelines for preparing papers for this publication. Presents information for authors publishing in this journal. [ABSTRACT FROM AUTHOR]

These instructions give guidelines for preparing papers for this publication. Presents information for authors publishing in this journal. [ABSTRACT FROM AUTHOR]

These instructions give guidelines for preparing papers for this publication. Presents information for authors publishing in this journal. [ABSTRACT FROM AUTHOR]

Presents the table of contents for this issue of the publication. [ABSTRACT FROM AUTHOR]

We have developed a bonded CMOS image sensor using a gallium oxide (Ga2O3)/polycrystalline selenium (c-Se)/nickel oxide photodiode and a Se–Se bonding process. These photodiodes can amplify the signal by avalanche amplification when a high electric field is applied, thus realizing a high-sensitivity image sensor. The Se–Se bonding process has many advantages, including the ability to handle high-temperature processing, no sputtering damage to the p-n junction interface, and no need for high-precision alignment. In this study, we have shown that the application of a high-temperature process to crystallize Ga2O3 improves the orientation of the c-Se, which is the photosensitive layer, and reduces the dark current. In addition, the Se–Se bonding process reduces the sputtering damage at the Ga2O3/c-Se interface, improving film quality. By applying the developed bonding process, we successfully realized a high-sensitivity CMOS image sensor with a threefold increase in magnification. [ABSTRACT FROM AUTHOR]

This article presents a low-power column-parallel $\Sigma \Delta $ analog-to-digital converter (ADC) with shared operational transconductance amplifiers (OTAs) for CMOS image sensors (CISs). Through the proposed time division multiplexing of OTAs, the power consumption of the modulator achieves a reduction of about 40%. The proposed structure alleviates the layout requirement of OTAs, enabling implementation of a high-resolution low-power image sensor in advanced CMOS technology nodes. As the coupled noise introduced by the proposed column-shared scheme is suppressed to a lower level than the inherent crosstalk of adjacent pixels, the proposed structure only contributes a negligible inter-column coupled noise from the ADCs. Moreover, a compact digital decimation filter with a single-bit-bit-wise-inversion (BWI) topology is also proposed, which can reduce chip area significantly. The prototype sensor is fabricated in a 40-nm standard CMOS technology with 256 $\times256$ pixel array and 256 proposed column-parallel $\Sigma \Delta $ ADCs. Each $\Sigma \Delta $ ADC occupies a core area of 4.5 $\mu \text{m}\,\,\times $ 310 $\mu \text{m}$ , while consuming a power of 58.8 $\mu \text{W}$. The measured differential nonlinearity (DNL) and integral nonlinearity (INL) are +0.49/−0.65 LSB and +5.1/−4.8 LSB, respectively. Measurement results show a dynamic range of 79.9 dB and an effective-number-of-bit (ENOB) of 11.4 bit. This work achieves a figure of merit (FOM) of 97.2 fJ/step. [ABSTRACT FROM AUTHOR]

The quanta image sensor (QIS) is a photon-counting image sensor that has been implemented using different electron devices, including impact ionization-gain devices, such as the single-photon avalanche detectors (SPADs), and low-capacitance, high conversion-gain devices, such as modified CMOS image sensors (CIS) with deep subelectron read noise and/or low noise readout signal chains. This article primarily focuses on CIS QIS, but recent progress of both types is addressed. Signal processing progress, such as denoising, critical to improving apparent signal-to-noise ratio, is also reviewed as an enabling coinnovation. [ABSTRACT FROM AUTHOR]

Realization of laser-induced graphene (LIG) by ablating laser on several substrates, like polyamide (PI), has gained huge attention. Generally, a CO2 laser, with a 10.6- $\mu \text{m}$ wavelength, has been reported to form LIG. However, higher build area, the requirement of a higher power, limited LIG conductivity values, infrared wavelength, and cost are several drawbacks of the CO2 laser-based process. Herein, a 3-D printer, loaded with a low-power (2.8 W) blue (450 nm) laser diode, has been demonstrated to create such LIGs with higher conductivity on PI sheets. The LIGs, with varying conductivity values, have been fabricated by diversified laser parameters achieving maximum conductivity of 2572.19 S/m, which was more than seven times higher than the one achieved by a CO2 laser. Subsequently, such LIG was transferred to a lamination sheet, named T-LIG, using a laminator. Finally, T-LIG based microfluidic device was developed with a microchannel and three integrated electrodes for electrochemical detection of folic acid, achieving a limit of detection of $10 ~\mu \text{M}$. Similarly, a microfluidic fuel cell was developed using T-LIG which provided a maximum power density of $5.06 ~\mu \text{W}$ / cm2 with a maximum open-circuit voltage of 50 mV. Overall, such T-LIG-based microfluidic devices have huge potential for diverse applications. [ABSTRACT FROM AUTHOR]

The article discusses information related to submission of a manuscript, review process, and open access for the authors of the periodical.

A year has gone by since the publication, in December 2020, of my last editorial devoted to thanking our reviewers. Another year (hopefully, the last one) where the persisting COVID pandemic has restricted our possibility to interact with people and to operate in a normal environment. I am happy to remark that, despite this, the review process of the papers submitted to the IEEE Transactions on Electron Devices (TED) was again virtually unaffected, even in the presence of an increasing submission count. [ABSTRACT FROM AUTHOR]

This article discusses complementary FET (CFET)-based static random access memory (SRAM) to achieve next-generation bitcell area scaling and performance gain in advanced CMOS technology nodes. SRAM bitcell area reduction, lower SRAM parasitic resistance, and higher drive strength are mandatory to continue SRAM scaling with technology advancement. The CFET reduces the SRAM bitcell area by folding nMOS over pMOS and making SRAM cross-coupled connections in the middle end of line (MEOL). The compact bitcell offers large area scaling combined with lowering bitline and wordline resistance. Lower parasitic resistance improves SRAM write margin and performance. The CFET SRAM cell area, write margin, read margin, and performance are evaluated and compared with FinFET (FF)-based SRAM. The CFET 111 and 122 SRAM provides up to 43.75% and 35% area gain w.r.t. FF 111 and 122 SRAM, respectively. Moreover, the CFET 122 SRAM has 11% faster read operation than FF 122 SRAM, respectively. [ABSTRACT FROM AUTHOR]

After six years on the IEEE Transactions on Electron Devices (T-ED) Editorial Board, Prof. Siddharth Rajan, Ohio State University, Columbus, OH, USA (compound semiconductor devices) has stepped down from his Editor position. [ABSTRACT FROM AUTHOR]

It is my sincere pleasure and honor to introduce the eighth Special Issue of the IEEE Transactions on Electron Devices on Solid-State Image Sensors. Previous special issues were published in February 1976, August 1985, May 1991, October 1997, January 2003, November 2009, and January 2016. In the six years since the last Special Issue, solid-state image sensors have continued to demonstrate impressive performance improvements and developments in a diverse set of technology areas. The areas include process modules, wafer-level stacking, single-photon counting, ultra-wide dynamic range, alternate detector materials, time-of-flight 3-D imaging, and device simulation. Solid-state image sensors also achieved continued growth in existing markets such as camera phones, automotive cameras, security and industrial cameras and medical/scientific cameras. New applications and markets, such as the Internet-of-Things, 3-D imaging, artificial intelligence, augmented reality, biometrics, and others, are driving further growth and technology development. Solid-state image sensors are now key components in a vast array of consumer and industrial products. [ABSTRACT FROM AUTHOR]

After nine years (the maximum three consecutive terms) on the Editorial Board of IEEE Transactions on Electron Devices (TED), Prof. Kevin Chen, Hong Kong University of Science and Technology, Hong Kong (compound semiconductor devices), and Prof. JianJang Huang, National Taiwan University, Taipei, Taiwan (optoelectronic devices), have stepped down from their Editor positions in the respective fields. [ABSTRACT FROM AUTHOR]

This article presents a new micro-light-emitting diode (LED) pixel circuit driven by the digital pulsewidth modulation (PWM) method, in which the threshold voltage compensation of the driving thin-film transistor (TFT) is included. A scan driver integrated by metal oxide (MO) TFTs is also designed to provide the scan signals for pixel circuits array. A micro-LEDs array with $76\,\, \times $ BBB $\times \,\,78$ and a scan driver with 80 stages are simultaneously fabricated by MO TFTs backplane with back-channel etch (BCE) structure. A respective micro-LED display is consequently realized by a peripheral driving system based on a field-programmable gate array (FPGA), which is used as a core control unit to synchronize the scan signals with the data signals. It is shown that the micro-LED in the pixel circuit can operate at a constant current even at the 5- $\mu \text{s}$ pulsewidth of the emission (EM) signal. The micro-LED display can achieve 256 linear grayscales with an approximately 60 Hz flash rate under the minimum pulsewidth of 40 $\mu \text{s}$ of EM signal. [ABSTRACT FROM AUTHOR]

There is a growing consensus that the physics-based model needs to be coupled with machine learning (ML) model relying on data or vice versa in order to fully exploit their combined strengths to address scientific or engineering problems that cannot be solved separately. We propose several methodologies of bridging technology computer-aided design (TCAD) simulation and artificial intelligence (AI) with its application to the tasks for which traditional TCAD faces challenges in terms of simulation runtime, coverage, and so on. AI-emulator that learns fine-grained information from rigorous TCAD enables simulation of process technologies and device in real-time as well as large-scale simulation such as full-pattern analysis of stress without high demand on computational resource. To accelerate atomistic molecular dynamics (MD) simulation, we have done a comparison study of descriptor-based and graph-based neural net potential, and also show their capability with large-scale and long-time simulation of silicon oxidation. Finally, we discuss the use of hybrid modeling of AI- and physics-based model for the case where physical equations are either fully or partially unknown. [ABSTRACT FROM AUTHOR]

Prospective authors are requested to submit new, unpublished manuscripts for inclusion in the upcoming event described in this call for papers. [ABSTRACT FROM AUTHOR]

Prospective authors are requested to submit new, unpublished manuscripts for inclusion in the upcoming event described in this call for papers. [ABSTRACT FROM AUTHOR]

Prospective authors are requested to submit new, unpublished manuscripts for inclusion in the upcoming event described in this call for papers. [ABSTRACT FROM AUTHOR]

Prospective authors are requested to submit new, unpublished manuscripts for inclusion in the upcoming event described in this call for papers. [ABSTRACT FROM AUTHOR]

Prospective authors are requested to submit new, unpublished manuscripts for inclusion in the upcoming event described in this call for papers. [ABSTRACT FROM AUTHOR]

Prospective authors are requested to submit new, unpublished manuscripts for inclusion in the upcoming event described in this call for papers. [ABSTRACT FROM AUTHOR]

Prospective authors are requested to submit new, unpublished manuscripts for inclusion in the upcoming event described in this call for papers. [ABSTRACT FROM AUTHOR]

Prospective authors are requested to submit new, unpublished manuscripts for inclusion in the upcoming event described in this call for papers. [ABSTRACT FROM AUTHOR]

Prospective authors are requested to submit new, unpublished manuscripts for inclusion in the upcoming event described in this call for papers. [ABSTRACT FROM AUTHOR]

Prospective authors are requested to submit new, unpublished manuscripts for inclusion in the upcoming event described in this call for papers. [ABSTRACT FROM AUTHOR]

Prospective authors are requested to submit new, unpublished manuscripts for inclusion in the upcoming event described in this call for papers. [ABSTRACT FROM AUTHOR]

Prospective authors are requested to submit new, unpublished manuscripts for inclusion in the upcoming event described in this call for papers. [ABSTRACT FROM AUTHOR]

Prospective authors are requested to submit new, unpublished manuscripts for inclusion in the upcoming event described in this call for papers. [ABSTRACT FROM AUTHOR]

This article presents a wide-spectral response single photon avalanche diode (SPAD) designed and fabricated in advanced 55-nm CMOS image sensor technology. SPADs with different active areas and doping profiles are simulated by Sentaurus-TCAD to optimize their electrical and optical performances. A global well-sharing technique is employed to deliver a pixel pitch of $16.4 ~\mu \text{m}$ and a fill factor of 50.96% for a device with a $6 ~\mu \text{m}$ radius. The proposed structure is based on a p+/deep n-well (DNW) multiplication junction, extending its spectral response as much as possible. Compared to the existing BSI SPADs, a triple protection method is innovatively used to suppress premature edge breakdown and to reduce the dark count rate (DCR) through a combination of a virtual retrograde DNW, p-well guard ring, and a poly gate ring located above the shallow trench isolation. Furthermore, deep trench isolation is employed to suppress crosstalk. Samples of different radii from 2 to $6 ~\mu \text{m}$ are manufactured. The SPADs exhibit a low DCR below 20 cps/ $\mu \text{m}$ 2 at room temperature and with a 2-V excess bias. The peak photon detection probability is 20.3% at 660 nm and is maintained at a high value, more than 10%, in the spectral range of 550–820 nm. [ABSTRACT FROM AUTHOR]

Lead-based organic–inorganic hybrid perovskite single crystals (OIHP SCs) offer promising opportunity for X-ray detection and imaging owing to their high X-ray attenuation coefficient, excellent optoelectronic properties, and simple fabrication processes. Nevertheless, it remains a key challenge to reduce its dark current and meanwhile maintain a high sensitivity. Herein, we developed an on-substrate method for growing methylamine lead bromide (MAPbBr3) SCs on aluminum oxide (Al2O3) layer coated indium tin oxide (ITO) glass. The photodiode based on this approach exhibits an ultralow-dark-current density of 1 nA cm−2 at an operative voltage of −5 V, a signal-to-noise ratio (SNR) more than 80 dB, and meanwhile retaining a high X-ray sensitivity of 2.02 $\times 10^{{3}}\,\, \mu \text{C}\cdot $ ${\mathrm {Gy}}_{\text {air}}^{-1} \cdot $ cm−2. Our further investigation reveals that the dark current was reduced due to two beneficial effects of the Al2O3 layer in tandem, including the interfacial defect passivation and blocking of hole injection by increased interfacial energy barrier. Our approach sheds light on advancing the fabrication of high-performance OIHP SCs-based X-ray sensors that can be potentially integrated with large-area readout panel at low temperature. [ABSTRACT FROM AUTHOR]

The extrinsic parasitics generally limit the modulation bandwidth of vertical cavity surface emitting lasers (VCSELs) for optical data links and interconnects. In this article, the extrinsic parasitics of 850-nm VCSELs are investigated by three different designs: oxide-only (design A), oxide-implant (design B), and oxide-implant with benzocyclobutene (BCB) (design C). The static and dynamic characteristics of all the designs with~7- $\mu \text{m}$ aperture are measured and compared. The maximum modulation bandwidth of design A is only about 12 GHz mainly limited by the large parasitic capacitances. With a proper proton implantation, a thick nonconducting layer is created inside the device with design B, which dramatically reduces the parasitic capacitances, and thus the bandwidth is increased to about 18 GHz. Based on design B, a 4- $\mu \text{m}$ -thick BCB layer with low dielectric constant is employed underneath the bond pad of design C to further reduce the pad capacitance, leading to the highest bandwidth about 24 GHz and the highest modulation current efficiency factor (MCEF) of 10.8 GHz/mA1/2. The microwave reflection coefficient (${S}_{{11}}$) parameters of the three designs are measured and compared. Results indicate that design C has the lowest parasitic capacitances and the highest modulation bandwidth, which is preferred for high-speed VCSELs to obtain good static and dynamic performance. [ABSTRACT FROM AUTHOR]

In this work, we report the impact of source region’s random dopant fluctuations (RDFs) induced variability on n-type silicon double gate (DG)-TFETs via 3D-device simulation. We have observed that source region’s RDF induces strong variability in the analog and RF figures of merit (FOMs) of the devices. This is the first report showing detailed impact of RDF on DG-TFET device and based circuit. The impact of RDF is analyzed by taking RDF only in source region as tunneling barrier width depends mostly on source doping and so does the ON-state current. The variation of analog and RF FOMs, such as transconductance $({g}_{m})$ , transconductance generation factor $({g}_{m}/{I}_{d})$ , output resistance $({R}_{o})$ , intrinsic gain $({g}_{m}{R}_{o})$ , capacitances $({C}_{{gs}}$ , ${C}_{{gd}}$), gate delay $({T}_{m})$ , cutoff frequency $({f}_{T})$ , and subthreshold swing (SS), is reported. We benchmark the device analog and RF performance of the RDF sample with respect to continuum one. On the basis of observed effective deviation in characteristics, common-source amplifier circuit is simulated to analyze the deviation in voltage-transfer characteristic (VTC) and gain–bandwidth product (GBWP). [ABSTRACT FROM AUTHOR]

HfO2-based FeFET is a remarkably promising candidate among emerging memory technologies. Its manifold applications range from nonvolatile memory to neuromorphic computing. However, the memory window (MW) is limited, since the ferroelectric properties of HfO2 degrade with increased ferroelectric thickness. Recent developments in asymmetric double-gate FeFET with dual port boast of a large MW when read from the back gate (BG), compared with the front gate (FG). It has been predicted that this can qualify as an excellent candidate for multi-level-cell (MLC) storage due to its high MW. However, the variability of the intermediate threshold voltage (VTH) states must be within reasonable limits to enable error-free reliable operation. In this work, we have thoroughly investigated the variability of VTH states in dual-port FeFET due to the random spatial distribution of ferroelectric domains. We have also accounted for the conventional sources of device variations, such as random dopant fluctuation (RDF), metal work-function variation (WFV), and line edge roughness (LER). We show that as MW is amplified when reading from BG compared with FG, variability is also amplified, thereby restricting its usage to accommodate a higher number of states. Nevertheless, a key benefit of BG read stems from the ability to reduce the ferroelectric thickness (tFE) from 10 nm down to merely 3 nm, still retaining an MW of 2.7 V. Notably, reducing tFE makes it possible to operate the FeFET at a lower voltage (1.8 V instead of 4 V). This creates avenues for better compatibility with the existing VLSI designs and reliability enhancements. We demonstrate that the variations in VTH are reduced for BG read on reducing tFE, which allows us to hold the same number of states even at such a scaled thickness. Finally, we predict the maximum number of states (in terms of bits) that can be stored and read reliably in dual-port FeFET for FG read and BG read at nominal and scaled tFE. We demonstrate that dual-port FeFET with BG read and scaled tFE offers MLC storage of 3 bits. [ABSTRACT FROM AUTHOR]

Flexible organic field-effect transistors (OFETs) based on solution-processed TIPS-Pentacene as semiconductor and high- ${k}$ P(VDF-TrFE) gate dielectric are successfully demonstrated on fabric for future electronic textile (e-textile) applications. These devices exhibited very high electrical performance with maximum ($\mu _{{\mathrm {max}}}$) and average ($\mu _{{\mathrm {avg}}}$) field-effect mobility values of ~1.2 and ~0.5(±0.3) ${\mathrm {cm}}^{2}\cdot {\mathrm {V}}^{-1}\cdot {\mathrm {s}}^{-1}$ , respectively, in the saturation regime and ${I}_{ \mathrm{\scriptscriptstyle ON}}/{I}_{ \mathrm{\scriptscriptstyle OFF}}$ of ~103 for a low operating voltage of −5 V, along with excellent electromechanical stability. Furthermore, these devices showed excellent environmental stability with almost unchanged electrical characteristics for 26 weeks. Moreover, devices showed high cyclic stability with stable ON/ OFF switching characterized up to 500 cycles. [ABSTRACT FROM AUTHOR]

The wideband high-power microwave systems have the advantages of wide energy spectrum, electron beam independence, compactness, and low cost. The gyromagnetic nonlinear transmission line (GNLTL) has drawn much attention for its potential as a novel solid-state, frequency-agile, and compact wideband source. The working mechanism of GNLTL is different from that of the traditional electric vacuum tubes, and the strong dispersion and nonlinear characteristics make it difficult to be accurately theoretically calculated and simulated. In this article, a 100-MW-level GNLTL system based on a Tesla-type driver was designed and constructed. A series of test experiments were then carried out to investigate the effects of different configurations, including delay line length, ferrite cores’ assembly orientation, transmission line length, bias magnetic field magnitude, and excitation voltage. The changing laws of the key parameters of the output microwaves including the peak power, modulation depth, center frequency, and percentage band are summarized and the underlying physical mechanisms are analyzed. The results may be instructive for the predesign of GNLTLs, especially for the devices operating at high power. In addition, a multiple center frequency points’ phenomenon was discovered in the output signal, which may bring new application possibilities for GNLTL. [ABSTRACT FROM AUTHOR]

Currently, the semiconductor industry requires test escape levels that approach the ppb level for application domains, such as automotive. Such quality levels, however, can only be reached if latent defects are screened out, as they have become the major bottleneck in analog and mixed-signal IC testing. Latent defects can be activated using accelerated aging, but this procedure has several drawbacks. Most notably, activation can move latent defects to the product lifetime that, otherwise, would not even have expressed themselves. Therefore, methods are needed that allow the detection of these defects without using activation. Developing such methods, however, has been hampered by the lack of compact latent defect models that allow simulating circuits affected by this type of defect. This article alleviates this problem by experimentally validating a recently presented compact model for latent defects and establishing the practical range of model values that should be used in simulations. The experiments performed on a 0.35- $\mu \text{m}$ technology consist of characterizing transistors containing latent defects that have been artificially introduced by etching pinholes in their gate. The measurement results corroborate that the drain current in transistors with defects increases with the area and depth of the defect, and that this behavior can be accurately modeled using an effective ${t}_{ox}$ value. [ABSTRACT FROM AUTHOR]

Cross-linking polymer gate dielectric is an efficient strategy to improve its intrinsic properties for high-performance flexible organic field-effect transistors (OFETs). However, the detail optimization process of the polymer films with the various cross-linking degrees is often ignored, which can bring a significant effect on the electrical performance of OFETs. In this work, the cross-linked poly (vinylalcohol) (CPVA) is introduced as the gate dielectrics for the high-performance ultraflexible OFETs. The dielectric property and the surface property of CPVA thin films with various cross-linking degrees are investigated in detail. The OFETs with a high average mobility of 7.3 cm $^{2}\cdot V^{-1}\cdot s^{-1}$ , a current ON/ OFF ratio of over 107, and a lower density of trap states of $8.7\times10$ 11 eV $^{-1}\cdot cm^{-2}$ are achieved successfully. Moreover, the ultraflexible OFET presents a high mobility of over 5.1 cm $^{2}\cdot V^{-1}\cdot s^{-1}$ even bending around a copper wire with a small radius of $400 ~\mu \text{m}$ , due to the ultrathin thickness of the device. These results demonstrate that the CPVA thin film is a promising candidate dielectric material for flexible organic transistors, presenting huge potential for the next-generation flexible electronic devices. [ABSTRACT FROM AUTHOR]

In this brief, a novel optically-reconfigurable physical unclonable function (OR-PUF) is presented for CMOS dynamic vision sensor (DVS). By utilizing the in-pixel logarithmic photoreceptor’s spatial photoresponse nonuniformity (PRNU) as the entropy source, raw physical unclonable function (PUF) bits having high reliability and randomness can be generated with monochromatic illumination in visible spectrum. In addition, the proposed OR-PUF can be reconfigured to new challenge-response-pair (CRP) spaces under the illumination with different visible wavelengths. Moreover, the proposed implementation is validated by prototype chips fabricated using a 0.18- $\mu \text{m}$ standard CMOS process. Featuring excellent randomness by passing the widely-adopted National Institute of Standards and Technology (NIST) and autocorrelation function (ACF) test tools, the fabricated PUF chips exhibit a uniqueness of 49.37% and a worst case bit error rate (BER) of 1.93% under the voltage–temperature (VT) range of 0 °C–80 °C and 1.65–2.2 V. [ABSTRACT FROM AUTHOR]

The influence of SiO2 and SiNx capping layer on threshold voltage (${V}_{t}$) for FinFET with TiAl-based metal gate (MG) is studied. After metal gate-stack formation, SiNx capping is revealed to be able to serve as a new N source, resulting in the diffusion of N into the effective work function (EWF) TiNx layer. Correspondingly, the accumulation of N in the TiNx layer is demonstrated to be able to lower the EWF for both n- and p-FinFETs. Compared to SiO2 capping, SiNx capping can induce $\sim 100$ –150 mV ${V}_{t}$ lowering for short n- and p-FinFETs. No obvious ${V}_{t}$ shift is found for long-channel devices. [ABSTRACT FROM AUTHOR]