Search

We report on investigation of the mechanical properties of paper electronics (printed and made out of paper). One key objective of such paper electronics is to achieve ultraflexibility. Therefore, it is important to understand electrical functionality and reliability of paper electronics under various physical (mechanical) deformations. Here, we show the general mechanical properties of the cellulose paper used and its electrical behavior under applied strain, tackling the main effects that need to be identified when building paper-based systems, from product performance and stability perspective. An overview of the stress–strain behavior of silver ink on paper is discussed, and then, we tackle a more specific analysis of the performance variations of paper sensors made with recyclable household materials when exposed to various mechanical conditions of tensile and compressive bending. This paper is important for developing stable wearable sensors for incorporation into Internet of Everything applications. [ABSTRACT FROM PUBLISHER]

Several miniaturized viscometers, or microviscometers, have been developed exploiting numerous rapid prototyping techniques. Among them, paper microstrips, famously known as microfluidic paper-based analytical devices ($\mu $ PADs), have become popular due to their cost-efficacy, simple fabrication, fast response, and easily disposable. Many fabrication methods are existing to develop paper microstrips. Herein, an alternative fabrication method is proposed where fused deposition modeling (FDM)-based 3-D printer (3DP) has been employed using polycaprolactone (PCL) filament. F, image processing has been utilized to measure viscosity in such microfluidic domain. Viscosity was calculated by measuring the time taken by the fluid to cover a fixed length between two spots in the microchannel based on the programed and color-coded regions-of-interest. The image processing program was developed considering the change in the gray scale in the virtual region of interests (ROIs) in the microchannel during the fluid flow in the paper microstrips. A 3-D printed handheld platform, containing raspberry pi with on-board camera and display, was developed to execute the image processing and automate the entire work flow. In the proposed device, the accuracy was measured to be >92%. [ABSTRACT FROM AUTHOR]

The electrophoretic display (EPD) is the main solution to electronic papers, but most of them can display the image or text in black and white particles only. The users may prefer the EPD showing multiple colors rather than the black/white content only. In this paper, we introduce the driving system for a color EPD, which is composed of three kinds of particles. The system aims at optimizing the visual quality based on a new driving waveform by equipping with an optimization method for color and tone reproduction. The experimental result shows that the proposed EPD driving system can display three-color pictures with promising visual quality. [ABSTRACT FROM AUTHOR]

Describes the above-named upcoming special issue or section. May include topics to be covered or calls for papers. [ABSTRACT FROM AUTHOR]

This paper provides an industry perspective on the present state of compact models for MOS transistors. It highlights the complexity of layout-dependent effects in modern transistors, reviews some common misunderstandings of MOS transistor capacitances, and introduces a new, structurally symmetric, “gate-as-input” equivalent network for these capacitances. Areas of focus for the future model developments are also proposed. [ABSTRACT FROM AUTHOR]

This paper reports an industry standard monolithic 555-timer circuit designed and fabricated in the in-house silicon carbide (SiC) low-voltage bipolar technology. This paper demonstrates the 555-timer integrated circuits (ICs) characterization in both astable and monostable modes of operation, with a supply voltage of 15 V over the wide temperature range of 25 °C–500 °C. Nonmonotonic temperature dependence was observed for the 555-timer IC frequency, rise time, fall-time, and power dissipation. [ABSTRACT FROM AUTHOR]

Describes the above-named upcoming special issue or section. May include topics to be covered or calls for papers. [ABSTRACT FROM AUTHOR]

During the past few years, we have seen an increasing number of submissions of “physics-based simulation only” papers to the IEEE TRANSACTIONS ON ELECTRON DEVICES (T-ED). The popularity of such papers may be explained by the fact that the present widespread technology computer-aided design (TCAD) tools are a significant and welcome boost to creativity in the electronic device community. In fact, TCAD tools allow researchers to explore and optimize device structures without being burdened by technology concerns in terms of availability, cost, and time delay. [ABSTRACT FROM AUTHOR]

The article offers information of Technology Computer-Aided Design (TCAD) which refers to the use of computer simulations to develop and optimize semiconductor process technologies and devices.

Prospective authors are requested to submit new, unpublished manuscripts for inclusion in the upcoming event described in this call for papers. [ABSTRACT FROM AUTHOR]

An introduction is presented in which the editor discusses articles in the issue on topics including IEEE Transactions on Electron Devices on New simulation methodologies for next-generation TCAD tools, and large-scale simulations.

Prospective authors are requested to submit new, unpublished manuscripts for inclusion in the upcoming event described in this call for papers. [ABSTRACT FROM AUTHOR]

Prospective authors are requested to submit new, unpublished manuscripts for inclusion in the upcoming event described in this call for papers. [ABSTRACT FROM AUTHOR]

Prospective authors are requested to submit new, unpublished manuscripts for inclusion in the upcoming event described in this call for papers. [ABSTRACT FROM AUTHOR]

This Special Issue of the IEEE Transactions on Electron Devices will feature the most recent developments and the state of the art in the field of ultra wide band gap semiconductors and devices for power control and conversion, including both experimental results and theoretical developments. Papers must be new and present original material that has not been copyrighted, published or accepted for publications in any other archival publications, that is not currently being considered for publications elsewhere, and that will not be submitted elsewhere while under considerations by the Transactions on Electron Devices. Topics of interest include, but are not limited to: IDtra Wide Band Gap Materials: Advances in material synthesis, defect characterization, transport and high-field properties, and material-level integration; evaluation of fundamental materials-limited figures of merit; Power Devices: Vertical and lateral MOSFETs, HEMTs and MIS-HEMTs, IGBTs, Schottky and pn junction rectifiers, and other device concepts; fabrication and device characterization; designs and device structures for controlling field profiles, edge termination; Thermal Management: Approaches to mitigate thermal effects in power devices using ultra wide band gap materials; Integration: Monolithic and heterogenous integration for system-level applications using ultra wide band gap materials. Integration with Si or other semiconductors for system-on-chip and system-in-package implementations, including heterogenous and package-level integration for high-performance power conversion applications. [ABSTRACT FROM AUTHOR]

Since 2017, the IEEE Transactions on Electron Devices (TED) has published a selection of extended versions of papers presented at the Symposia on VLSI Technology and Circuits held in the corresponding years (vol. 64, no. 10; vol. 65, no. 11; vol. 66, no. 12). Since 2018, the papers have been collected in a Special Section of TED titled “Papers from Symposium on VLSI Technology.” This initiative, which was the result of a fruitful cooperation between the Electron Device Society and the VLSI Symposium chairs and committees, has brought to TED a number of carefully selected (by the VLSI TPC first and then through the TED usual review process), high-quality submissions. We have been able to continue this cooperation also in this difficult 2020, and we are therefore happy to announce the publication in the December issue (Vol. 67, No. 12) of a Special Section on papers from the 2020 Symposium, held virtually on June 15–19, 2020. A special thanks to the Guest Editors of the section, Peide Ye, Purdue University (Publication Chair, 2020 VLSI Symposium), and Masaharu Kobayashi, The University of Tokyo, Japan (Publication Co-Chair, 2020 VLSI Symposium). [ABSTRACT FROM AUTHOR]

Describes the above-named upcoming special issue or section. May include topics to be covered or calls for papers. [ABSTRACT FROM AUTHOR]

The article highlights call for papers from Ieee Transactions on Electron Devices on several topics including advanced transistors; gate dielectrics; and power devices.

We have fabricated fully transparent high performance flexible nickel-doped zinc oxide thin-film transistors (NZO TFTs) on flexible plastic substrates using magnetron sputtering. The effects of active layer thickness on the performance of NZO TFTs was investigated. We found that the channel layer thickness has a notable influence on the characteristics of NZO TFTs. The electrical characteristics of NZO TFTs reached the optimization when the active channel layer thickness was 71 nm, with a low off-current lower than 1 pA, a high on/off drain current ratio of 2.1 \times 10^9 , a high saturation mobility of 27.5 cm ^2\cdot \mathrm V^-1\cdot \mathrm s^-1 , a steeper subthreshold swing of 67 mV/decade, and a low threshold voltage of 1.88 V. It is demonstrated that NZO is a promising active channel layer materials for future transparent flexible displays. [ABSTRACT FROM AUTHOR]

Flexible, highly sensitive, easy fabricating process, low-cost pressure sensors are the trend for flexible electronic devices. Despite the tremendous progress in recent years, it is still challenging to prepare pressure sensors with high sensitivity, high stability, and fast responsiveness. In this study, we report a simple and low-cost method for the preparation of novel pressure sensors. Inspired by the pomegranate structure, a 3-D porous structure consisting of polystyrene (PS) microspheres filled with reduced graphene oxide (rGO) paper is proposed. This pressure sensor has high linear sensitivity (1.41 kPa−1 in the pressure range of 0–50 kPa), high stability (1000 cycles), and quick response time (~20 ms). Furthermore, a robotic arm interacting control system based on pressure sensor arrays is constructed, which demonstrates the far-reaching potential of pressure sensors in human–machine interaction. Therefore, this work provides a low-cost and effective method for preparing high linear sensitivity pressure sensors. [ABSTRACT FROM AUTHOR]

The article invites, papers from authors for a special issue of the journal "IEEE Transactions on Electron Devices" on "Reliability of CMOS Logic, Memory, Power and Beyond CMOS Devices."

The article presents the invitation of the journal to interested individuals to submit papers and articles on memory, logic and CMOS devices.

Describes the above-named upcoming special issue or section. May include topics to be covered or calls for papers. [ABSTRACT FROM AUTHOR]

Describes the above-named upcoming special issue or section. May include topics to be covered or calls for papers. [ABSTRACT FROM AUTHOR]

Describes the above-named upcoming special issue or section. May include topics to be covered or calls for papers. [ABSTRACT FROM AUTHOR]

The article offers information on electronics devices, complementary metal–oxide–semiconductor (CMOS) logic, power and memory. Topics discussed include electronics devices with features related to experimental results and theoretical model; include advanced transitory with features of self-heating effect and variability; and discusses power devices like the metal–oxide–semiconductor field-effect transistor (MOSFET) and insulated-gate bipolar transistor (IGBT).

The first part of this paper presented mymargin the device-level comparison of emerging materials (In0.53Ga0.47As and 2-D materials) and device architecture (NW FETs) with s-Si FinFETs. In order to further understand the performance and energy efficiency of these device options for future technology nodes, it is required to go beyond the device-level comparison by accounting for not only intrinsic but also the extrinsic parasitic elements. In this paper, we present the comparison of s-Si, In0.53Ga0.47As, and 2-D material-based n-type MOSFETs using the circuit-level figure of merits across three successive future technology nodes. The analysis incorporates both device characteristics obtained from an advanced quantum mechanical simulation tool and circuit-level comparison, which accounts for device parasitic elements and wiring load. The results show that 2-D material DG MOSFETs present a more energy-efficient device option than s-Si and In0.53Ga0.47As FinFETs in sub-0.7-V supply voltage regime and In0.53Ga0.47As nanowire (NW) FETs can outperform s-Si multi-gate (MuG) FETs and 2-D material FETs, but when considering non-idealities, s-Si NW FETs remain both faster and more energy-efficient device option. [ABSTRACT FROM AUTHOR]

In recent years, triboelectric nanogenerators (TENGs) have been increasingly attracting attention owing to the ability for converting multiple mechanical energy into electricity. In this paper, we first propose a multifunctional conductive copper tape-based TENG (CCT-TENG) that is constructed completely using one piece of conductive copper tape. The triboelectric pairs, supporting structure, and conductive electrode were composed using bottom paper, silicone oil, and copper foil, all of which came from one roll of conductive copper tape. The approximate output power density of the CCT-TENG reached $240.1~\mu \text{W}$ /cm2. By spraying the aqueous solution of LiCl onto the surface of the bottom paper, a CCT-TENG incorporating LiCl was fabricated and used as a self-powered active sensor to detect the relative humidity (RH) of the environment. The obtained results revealed that the humidity sensor had good humidity response, response linearity, and reversibility. In addition, the RH was reflected by the brightness of light-emitting diodes (LEDs) that was driven by the humidity sensor. This paper realizes a promising, affordable, and portable integration of power supply systems and sensing systems, which can promote the application of TENG in the field of electronic detection device and environment monitoring. [ABSTRACT FROM AUTHOR]

This Special Issue is dedicated to recent research in the field of compact modeling for circuit design. The topics included all device structures, provided it was demonstrated that the presented compact modeling solutions were implementable in circuit design tools. The last Special Issue addressing compact modeling of all types of semiconductor devices was published in 2006. Since then, new device structures, and with different materials, have emerged, and significant and successful research in compact advance device modeling has been done, as well in the application of compact models to circuit design. Therefore, a new Special Issue was needed that could include high-quality papers in these topics. [ABSTRACT FROM AUTHOR]

In part I of this paper, we developed physical insights into the role and impact of acceptor and donor traps—resulting from C-doping in GaN buffer—on avalanche breakdown in AlGaN/GaN HEMT devices. It was found that the donor traps are mandatory to explain the breakdown voltage improvement. In this paper, silicon doping is proposed and explored as an alternative to independently engineer donor trap concentration and profile. Keeping in mind the acceptor and donor trap relative concentration requirement for achieving higher breakdown buffer, as depicted in part I of this paper, silicon & carbon codoping of GaN buffer is proposed and explored in this paper. The proposed improvement in breakdown voltage is supported by physical insight into the avalanche phenomena and role of acceptor/donor traps. GaN buffer design parameters and their impact on breakdown voltage as well as leakage current are presented. Finally, a modified Si-doping profile in the GaN buffer is proposed to lower the C-doping concentration near GaN channel to mitigate the adverse effects of acceptor traps in GaN buffer. [ABSTRACT FROM AUTHOR]

Describes the above-named upcoming special issue or section. May include topics to be covered or calls for papers. [ABSTRACT FROM AUTHOR]

Prospective authors are requested to submit new, unpublished manuscripts for inclusion in the upcoming event described in this call for papers. [ABSTRACT FROM AUTHOR]

The article talks about the reliability of electronic devices as an issue for technology, impact of Bias Temperature Instability on CMOS logic devices and evolving Hot Carrier Degradation and Self Heating Effect. It talks about degradation of program window, development in the field of device reliability and topics that includes Advanced Transistors, Gate Dielectrics and Memory Devices.

A high-harmonic traveling-wave tube (HHTWT) is designed, developed, and tested in this paper. This device is configured as a multiplier–amplifier with Q-band input signals and its third harmonic, i.e., D-band output power. The tested result demonstrates that 280 mW at 133.5 GHz is obtained as a result of 200 mW at 44.5-GHz input signal. The simulation and experiment validate that the high-harmonic radiation can be generated and amplified in the HHTWT. The approach described in this paper could find application in exploring high power, wideband tunable terahertz source. This paper is expanded from a conference paper on IVEC 2017. The detail design produce and tested result are added in this paper. The explanation of the simulation and tested results is also presented. [ABSTRACT FROM AUTHOR]

It is my great pleasure to introduce the Seventh Special Issue of the IEEE TRANSACTIONS ON ELECTRON DEVICES on Solid-State Image Sensors. Previous special issues were published in February 1976, August 1985, May 1991, October 1997, January 2003, and November 2009. During the six-year interval since the last special issue, significant changes have occurred in the field of solid-state image sensors. This is due, in particular, to the drive for low-power, high integration, compact imaging systems. Now that the speed of pixel shrinkage is slowing down, various new technologies are being developed to increase the functionality of the sensors, to make them more compact, to make them faster, to increase their dynamic range, etc. Papers reflecting these trends in the image sensor technology are well represented in this special issue. [ABSTRACT FROM AUTHOR]

Resistive random access memory (ReRAM) is often considered as a strong candidate for storing the weights in non-von Neumann neuromorphic computing systems. This paper studies how nonideal memory characteristics, which include programing error, read fluctuation, and retention, affect the inference accuracy of the analog ReRAM neural networks by incorporating memory characteristics extracted from 1-Mb ReRAM into a simulated inference-only neural network. This paper also shows that the different layer in the network can tolerate different amount of such imperfects. We learned four key points: 1) the conductance range of memory with less relative fluctuation is preferred for designing the weight-conductance mapping; 2) the control of programing error is essential for high inference accuracy; 3) retention-induced conductance drift can be fatal to the neuromorphic system. A compensation scheme is proposed in this paper which can effectively recover the inference accuracy; and 4) for multilayer networks, avoiding weight errors in the front layers can help to maintain the inference accuracy by reducing calculation error which may otherwise accumulate and pass down the networks. The concepts and approaches of this paper can also be applied to evaluate other types of nonvolatile memories for artificial neural networks. [ABSTRACT FROM AUTHOR]

In this paper, an analytical model has been developed to observe the recombination losses involved in a tunnel oxide passivated contact solar cell with a carrier-selective layer constituting polycrystalline silicon (poly-Si). The main focus of this paper is to observe the contribution of each component of recombination current density and its effect on open-circuit voltage, Voc. The effect of emitter saturation current density (Joe), surface recombination velocity, substrate thickness, and doping density of carrier-selective layer on Voc has been presented. The analysis indicates that Voc = 766 mV can be achieved for Joe = 2 fA/cm2, and a doping density of poly-Si > 1021cm−3 in a c-Si/SiO2/poly-Si contact for a 50- $\mu \text{m}$ -thick substrate in case of ideal surface passivation. For identical conditions, Voc attains a lower value of 750mV for a 180- $\mu \text{m}$ -thick substrate. The dependence of Voc on bandgap of tunnel layers has also been observed by considering other materials like Si3N4 and SiC. These results from the analyticalmodel have been compared with results froma simulation using automat FOR simulation of HETerostructures v2.5 and have been found to be in good agreement with each other. [ABSTRACT FROM AUTHOR]

In this paper, an inner ultrathin oxide metal–oxide–semiconductor (MOS) capacitor is fabricated with another outer MOS-gate ring as a coupling controller. Capacitance–voltage characteristics of inner MOS capacitor show that the excess minority carriers supplied from the outer MOS-gate ring can efficiently change the inner capacitance (${C} _{\text {inner}}$). It is observed that outer MOS-gate ring under the conditions at floating and at ground has quite different coupling effects on ${C} _{\text {inner}}$ when the inner MOS is biased at 1 V. Comparing to ${V} _{\text {outer}} = \text {floating}$ , ${C} _{\text {inner}}$ reduces significantly when ${V} _{\text {outer}} = {0}$ V at 1k Hz. The transient behavior of ${C} _{\text {inner}}$ as ${V} _{\text {outer}}$ changes from 0 V to floating is long enough to read, and the difference of two capacitance values can be regarded as two states. As a result, a two capacitance states operation is proposed for possible memory application. Based on the experimental results, the possible memory cell configuration is designed. Comparing to the present emerging memories, since the two states in this paper are in conditions of floating and 0 V, ultralow power is consumed, which is believed a promising concept for future memory application. [ABSTRACT FROM AUTHOR]

In this paper, for the first time, the record high-performance top-gated graphene technology platform is used for electrostatic discharge (ESD) physics exploration while investigating the implications of various design and technology options. Impact of diffusive versus ballistic carrier transport on the failure mechanism in top-gate as well as back-gate graphene FET (GFET) is investigated. A unique contact limited failure in graphene transistors is reported. Physical insights on current saturation in GFET and unique step-by-step failure in dielectric capped transistors are presented for the first time. Moreover, device degradation under ESD timescales and its implications on current saturation are revealed. Finally, the influence of various top-gate designs on the ESD performance is reported. New physical insights and matured GFET technology has eventually enabled record high ESD robustness. [ABSTRACT FROM AUTHOR]

Because of charge trapping in GaN HEMTs, dc characteristics of these devices are not representative of high-frequency operation. The advanced spice model GaN model presented in Part I of this paper is combined with a Shockley–Reed–Hall-based trap model, yielding a comprehensive FET model for GaN HEMTs which can accurately model GaN devices exhibiting trapping-related dispersion effects. Measurement results of the dc and pulsed output and transfer characteristics of a commercially available GaN HEMT are presented, trapping in the device is modeled, and excellent fit to the measured data is shown. This paper presents an accurate model of trapping which is validated for eight different quiescent bias points of pulse measurements, with quiescent drain voltage ranging from 5 to 20 V and quiescent gate voltage ranging from −2.8 to −3.8 V, and a large range of gate and drain voltages to which the device was pulsed in the pulse measurements and at which the device was measured in the dc measurements, with gate voltage ranging from −4 to 0.4 V and drain voltage ranging from 0 to 40 V. This paper also presents high-frequency (10 GHz) large-signal RF validation of the model for optimal complex load condition. [ABSTRACT FROM AUTHOR]

Thin-film transistors were fabricated using 45-nm thick ZnO deposited by pulsed laser deposition and 15-nm thick Al2O3 gate insulator deposited by atomic layer deposition. A 1-D model with a constant density of interface states above and below the conduction band edge is used to explain the current-voltage characteristic. This model does not create distortion of transconductance versus gate voltage at low gate voltage that can be created by exponential tail or Gaussian distributions of interface states. The “subthreshold” regime is at the top ZnO surface away from the bottom gate, but subthreshold swing is controlled by interface states at the ZnO/Al2O3 bottom interface. The observed increase in mobility with gate voltage is delayed by filling of the interface states above the conduction band edge. Interface state filling and a rapid increase in mobility with increased gate voltage produce an apparent large threshold voltage as extrapolated from a linear fit to current measured at large gate voltage. The difference between threshold voltage and turn-off voltage is an important figure of merit (FOM) that should be kept as small as possible. In this paper, FOM is 2.5 and 1.8 V for 0.1 and 6 V drain voltage, respectively. [ABSTRACT FROM PUBLISHER]

The physical mechanisms involved in the trapping and de-trapping processes associated with surface donor traps in gallium nitride (GaN) transistors are discussed in this paper. The paper challenges the conventional transient techniques adopted for extrapolating the trap energy level via experiments and TCAD simulations. Transient TCAD simulations were employed to reproduce the time-dependent electrical behavior of a metal-on-insulator field-effect transistor and explain the influence of the electric field and energy barrier on the transient time associated with the trapping and de-trapping mechanisms of surface traps. The comparison between three test structures and the relative variation of the trapping and de-trapping times with the bias and trap parameters leads to the suggestion of a proposed test structure and bias configuration to accurately extrapolate the energy level of surface traps in GaN transistors. [ABSTRACT FROM AUTHOR]

For the first time, considering the architecture of monolithic 3-D integration, we evaluate and benchmark the performance of 3-D logic circuits and stability/performance of 3-D 6T SRAM cells with monolayer and few-layer transition metal dichalcogenide (TMD) devices based on ITRS 2028 (5.9 nm) technology node. The impact of random variations on the cell stability is also investigated. With the possibility of adopting monolayer or few-layer TMDs for nFET- and pFET-tiers enabled by monolithic 3-D integration, this paper indicates that the trilayer TMD device may substantially degrade the performance of 3-D logic circuits in spite of its higher mobility. This paper also reveals that stacking the monolayer pFET-tier over the bilayer nFET-tier may provide better nominal stability and read/write performance for 6T superthreshold SRAM compared with the planar technology, whereas the optimum 3-D configuration for near-/sub-threshold operations appears to be the monolayer pFET-tier over the monolayer nFET-tier. Besides the 6T cell structure, 8T SRAM cells are also investigated with monolithic 3-D integration for near-threshold/subthreshold operation. The monolayer nFET-tier over the bilayer pFET-tier configuration is shown to be the optimum 3-D 8T near-threshold/subthreshold cell design. [ABSTRACT FROM AUTHOR]