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A 5.8GHz four-channel transmitter RF beamforming IC based on a vector modulator fabricated via the 130 nm RF CMOS process is presented here. The vector modulator controls the gain and phase independently by steering the tail current sources of a Gilbert-cell-based vector synthesizer. It offers 8-bit phase control for 360 ∘ and 4-bit gain control for a 20 dB dynamic range, with the size not depending on the control bits. A four-way differential RF power divider is introduced to implement the four-channel IC, in which off-chip ground bonding inductance is resonated out through the introduction of additional capacitances to a λ/4 impedance transformer of a four-way Wilkinson divider to reduce the insertion losses and errors. The measured total RMS gain error of the vector modulator is 0.312 dB and the total RMS phase error is 0.329 ∘. It shows 20 mW DC power consumption per channel, 5.19 dBm OP1dB, and a 3 dB gain overall including 6 dB of dividing loss.

A frequency-reconfigurable SP4T switch is presented, in which RON×COFF characteristics of switch transistors are enhanced with plaid metal transistors and forward body biasing. Plaid metal transistors (PMT) with forward body bias (FBB) are used for all of the transistors to enhance the FoM. The plaid patterned metal accesses of a transistor for the source and drain decrease the extrinsic resistance and capacitance. FBB increases the overdrive voltage of a transistor and decreases the on-resistance. The SP4T switch includes main switch matrices that route an input signal to four-outputs, a switched inductor (SI) network, and a mode-selection switch. The SI network connected through the mode-selection switch resonates out the off-capacitances of the main switch matrices at RF in the RF mode. The SP4T switch operates without the SI network in DC mode. The SP4T switch is implemented in a 28-nm FDSOI CMOS process. The core area occupies 0.2 mm2. The switch shows less than 2 dB insertion loss from DC to 4.4 GHz in the DC mode and from 4.4 to 5.3 GHz in the RF mode, where isolations are more than 16.8 dB and 18 dB, respectively.

This brief presents a variable-gain low-noise amplifier (VG-LNA) with a common gate (CG) cross-summing configuration, which is fabricated using a 65-nm RF CMOS process. It has a wide gain control range as well as a high input 1 dB gain compression point (IP1dB) at high-gain by introducing a split common-gate transistor (SCGT) technique. In addition, output phase compensation is achieved by adopting a tuning capacitor at the cascode node. This LNA is designed as 2-stage cascode, and the area excluding the pad is 0.2 mm2. It consumes 25.2 mW with a 1.2-V power supply. It shows a gain of 25 dB and a noise figure of 3.4 dB at 22 GHz. The measured minimum IP1dB is −27.5 dBm, and the root-mean-square phase error is 0.34° over the gain control range of 14 dB at 22 GHz.

A Ka-band variable-gain phase shifter (VGPS) using a multi-vector summation method is proposed, which represents both phase and amplitude by summing the I and Q signals of multiple vectors. The VGPS has an orthogonal phase and gain control function with a wide gain-control dynamic range because it is designed to keep the input and output impedances almost constant regardless of the control states. It shows a measured RMS phase error of 2.9 ° during 17.3 dB gain control and that of 3.5 ° during simultaneous 17.3 dB gain and 360 ° phase control without any calibration from 30 to 32.5 GHz. The measured average insertion loss ranges from −4 to −2.8 dB from 28 to 33 GHz. It is implemented in a 65-nm RF CMOS process with the size of 0.21 mm2 excluding pads.

A two-stage 24–30 GHz wideband power amplifier (PA) with an adaptive capacitance linearizer is presented, which is fabricated using a 28-nm bulk CMOS process. Staggered input gain matchings of the driver and power stages are implemented with wideband output power matchings to achieve wideband power characteristics. An adaptive capacitance linearizer is introduced at the power stage input to improve the AM-PM linearity with respect to input powers. At 24/26/28/30 GHz, it achieves 19.7/20.3/20/20 dBm $\text {P}_{\text {sat}}$ , 18.2/18.2/17.8/17.2 dBm $\text {P}_{\text {1dB}}$ , and 34.5/33.1/30/30.3% peak power added efficiency (PAE). The small-signal gain of 21.2 dB and the 3-dB bandwidth of 8.2 GHz are achieved. It has a core size of 0.189 mm2.

A dual-mode radio frequency CMOS power amplifier (PA) for Internet of Things application is presented, which is integrated with the other circuits in a 55-nm bulk CMOS process. The low-power mode is achieved by reducing the number of turn-on power transistors, which are also used for linearization. The PA has a gain control scheme that functions by controlling the transconductance ( ${g_{m}}$ ) of the driver stage. A simple body network is introduced to common gate power transistors to improve the linearity of the PA. It is measured with 802.11n 64-quadrature-amplitude-modulation (MCS7) signal and shows a maximum average power of 16 dBm with a supply current of 222 mA under an error-vector-magnitude of −27 dB, which is packaged in a QFN 5 ${\times } \,\, 5$ mm.

A fully integrated RF CMOS front-end (FE) IC (FEIC), which is fabricated with a 0.13- $\mu\text{m}$ bulk RF CMOS process for wireless local area network/Bluetooth (WLAN/BT) applications, is presented. The proposed FEIC includes a dual-mode power amplifier (PA), integrated switches, and a shared low-noise amplifier (LNA) without external matching networks. The proposed compact reconfigurable matching network satisfies the optimum matchings for a multimode PA and a shared LNA. Measurements showed a 16.2-dBm $P_{\mathrm{OUT}}$ , with a 6.7% power-added efficiency (PAE), at −34-dB error vector magnitude, with an 802.11ac signal source, with a high-power-mode WLAN PA. With a low-power-mode BT PA, it showed a 13.7-dBm $P_{\mathrm{OUT}}$ , with a 10.9% PAE, with a 2.1+EDR signal. The shared LNA has a 14.8-dB gain and a 3.6-dB noise figure. All the measurements were carried out, including integrated mode-change switches for time-division duplex operation without any digital predistortion.

This brief presents a fully integrated CMOS receiver that is capable of dual-mode frequency-modulated continuous-wave (FMCW) and ultrawideband (UWB) radar operations using the 0.13- $\mu\hbox{m}$ CMOS technology. The circuit consists of a low-noise amplifier, active mixers, an in-phase and quadrature generator, and buffers. In the proposed receiver, not only the gain but also the bandwidth of the overall receiver can be tailored by the switching of the center frequencies of stages and without lowering the quality factor of each stage. As a result, the receiver achieves a conversion gain of 36.7 dB, a 1-dB power gain compression point (P1dB) of $-$ 29.7 dBm, and a double sideband (DSB) noise figure (NF) of 6.1 dB in the narrowband FMCW mode. The receiver also achieves a conversion gain of 27.4 dB with a 3-dB bandwidth of 6.1 GHz, a P1dB of $-$ 21.6 dBm, and a DSB NF of 7.4 dB in the UWB pulse mode. Its performance is comparable with that of previously published chips that only operate in a single mode.

A low-noise ultrawideband CMOS mixer circuit for the down conversion of a K-band signal is presented. A bleeding path gm-boosting technique is proposed, which reduces the effect of noise sources of the proposed mixer. The measurement results show that the minimum noise figure is 3.61 dB at 24 GHz when consuming 2.6 mW at a 1.5-V supply voltage. The results also show a conversion gain of 9.15 dB, a of P1dB of -13 dBm, and an isolation of a local oscillator port to a radio frequency port of -40 dB. The circuit was fabricated using 0.13-μm CMOS technology with a chip area of 0.68 x 1.07 mm2.

A K-band CMOS voltage-controlled oscillator (VCO) is implemented with a 0.18- ?m radio frequency CMOS process. For low supply voltage operation, a transformer-feedback topology using a transformer is proposed. The analysis of the transformer-feedback VCO is presented. This shows that the inductance ratio of the transformer must be optimized, and asymmetric-width transformers allow the easy optimization and the high Q-factor. Based on this analysis, the transformer design consideration of the transformer feedback VCO is presented. The VCO operates at 24.27 GHz with the phase noise of -100.33 dBc/Hz at 1-MHz offset, and it consumes 7.8 mW from a 0.65-V supply voltage.