Search

This paper proposes a unified framework to describe the check node architectures of non-binary low-density parity-check (NB-LDPC) decoders. Forward–backward, syndrome-based, and pre-sorting approaches are first described. Then, they are hybridized in an effective way to reduce the amount of computation required to perform a check node. This paper is specially impacting check nodes of high degrees (or high coding rates). Results of 28-nm ASIC post-synthesis for a check node of degree 12 (i.e., a code rate of 5/6 with a degree of variable equal to 2) are provided for NB-LDPC over GF(64) and GF(256). While simulations show almost no performance loss, the new proposed hybrid implementation check node increases the hardware and the power efficiency by a factor of six compared with the classical forward–backward architecture. This leads to the first ever reported implementation of a degree 12 check node over GF(256), and these preliminary results open the road to high decoding throughput, high rate, and high-order Galois field NB-LDPC decoder with a reasonable hardware complexity.

This paper presents an innovative Through-Load element aimed at characterization applications at mm-wave frequencies. The proposed structure can behave as a Through connection or as a 50- $\Omega $ load depending on a DC control voltage. Among other potential applications, this system can be used to implement a transfer switch or an attenuator. A demonstrator was fabricated and measured in the STM 55-nm BiCMOS technology. Over a wide bandwidth, from 55 GHz up to 170 GHz, experimental measurements demonstrate a maximum 1.6-dB of insertion loss when behaving as a Through connection and a minimum 14-dB of insertion loss when behaving as a 50- $\Omega $ load. In both cases, the return loss is better than 10 dB. The insertion loss at 90 GHz is 0.6 dB for the Through connection and 20 dB for the 50- $\Omega $ load connection.

In this paper, an efficient control strategy for three-phase four-switch inverter-fed Brushless DC Motor (BLDCM) drives with trapezoidal back Electromotive Force (EMF) is proposed. In the proposed approach, the outer control loop for adjusting the motor speed is designed using Model Predictive Control (MPC) while the inner control loop based on a hysteresis controller regulates the BLDC phase currents. To effectively adjust the current of the uncontrolled phase in the four-switch inverter, efficient switching strategies for motor and generator modes are suggested. The proposed control scheme achieves favorably low torque ripples and improves the speed transient response in terms of tracking error and speed overshoot/undershoot. Therefore, it can be an ideal candidate for low-cost low-power BLDCM applications. Also, the MPC-based speed control loop is tuned by solving a suitable cost function in an offline manner to minimize the real-time computational effort. Using the foregoing technique, it is shown that the implementation of the proposed MPC-based controller becomes as simple as the PI controller while the MPC-based controller achieves superior control performance. The proposed BLDCM drive scheme is experimentally verified in a Hardware-in-the-Loop (HiL) test setup with a 1200W BLDCM and dSPACE1104 development board. The experimental results demonstrate the benefits of the proposed drive system.

This paper discusses the distributed fixed-time containment control for networked nonlinear systems via the event/self-triggered approaches over directed graphs. A distributed event-triggered control protocol without continuous control updates is first proposed. In order to relieve the chattering effect, a modified distributed event-triggered control law is developed. To further overcome the drawback of continuous state monitoring and reduce the communication frequency between neighboring agents, a distributed chattering-free self-triggered control strategy is accordingly designed. A favorable aspect of our work is that the unnecessary resource utilizations of computation, communication as well as control updates can be saved while sustaining the desired control properties and excluding the Zeno behavior. Another distinct feature of this paper lies in that the containment control objective is realized in fixed time and the estimate of settling time can be prescribed without dependence on initial states of networked agents. Finally, some simulation results are provided to illustrate the effectiveness of the theoretical control schemes.

Analysis of ac electrical systems can be performed via frame transformations in the time-domain or via harmonic transfer functions (HTFs) in the frequency-domain. The two approaches each have unique advantages but are hard to reconcile because the coupling effect in the frequency-domain leads to infinite dimensional HTF matrices that need to be truncated. This paper explores the relation between the two representations and shows that applying a frame transformation on the input-output signals creates a direct equivalence to a similarity transformation to the HTF matrix of the system. Under certain conditions, such similarity transformations have a diagonalizing effect which, essentially, reduces the HTF matrix order from infinity to two or one, making the matrix tractable mathematically without truncation or approximation. This theory is applied to a droop-controlled voltage source inverter as an illustrative example. A stability criterion is derived in the frequency-domain which agrees with the conventional state-space model but offers greater insights into the mechanism of instability in terms of the negative damping (non-passivity) under droop control. Therefore, the paper not only establishes a unified view in theory but also offers an effective practical tool for stability assessment.

International audience; The Internet of Things (IoT) entails new challenges for the development of wireless transceivers. Radio-frequency building blocks require complex design flows in order to address very different sets of specifications. This paper presents a three-step design methodology dedicated to the synthesis of RF building blocks. Based on the inversion coefficient, the proposed design methodology allows the optimization of the circuit performance for any CMOS process and any application. It is illustrated through the implementation of inductorless low-noise amplifiers (LNA) in three different CMOS nodes: 28-nm fully-depleted silicon-on-insulator (FDSOI), and 65 and 130-nm Bulk. These LNAs are dedicated to two cases of IoT applications: multi-standard and ultra low power. The proposed circuits achieve the state-of-the-art performance for all nodes and applications. Furthermore, the methodology enables an insightful comparison of the capabilities of the different CMOS nodes in terms of power consumption, noise, and bandwidth.

In this paper, we discuss the potential foundry announced integration of magnetic random access memory (MRAM) on fully depleted silicon-on-insulator (FDSOI). The spin transfer torque magnetic tunnel junction (STT-MTJ) and the next-generation voltage-controlled magnetic anisotropy MTJ are separately integrated into a 28-nm FDSOI process as the MRAM or magnetoelectric random access memory (MeRAM)-on-FDSOI integration. Micromagnetic and electrical simulations are used to evaluate the performance of hybrid circuits. Circuit-level design strategies are explored that use FDSOI leverage and spin-device characteristic to realize writing and sensing power-delay efficiency, robust, and reliable performance in the one-transistor one-MTJ MRAM/MeRAM bit-cell and sensing circuits. Reliability issues are discussed. Process variation and aging resilience strategies, e.g., step-wise back-bias, flip-well re-configuration, and write assist, are proposed to address failure and aging degradation in the MRAM/MeRAM-on-FDSOI integration. A qualitative summary demonstrates that the MRAM/MeRAM-on-FDSOI integration offers attractive performance for future non-volatile CMOS integration.

Implantable systems are nowadays being used to interface the human brain with external devices, in order to understand and potentially treat neurological disorders. The most predominant design constraints are the system’s area and power. In this paper, we implement and combine advanced compressive sampling algorithms to reduce the power requirements of wireless telemetry. Moreover, we apply variable compression, to dynamically modify the device performance, based on the actual signal need. This paper presents an area-efficient adaptive system for wireless implantable devices, which dynamically reduces the power requirements yielding compression rates from $8{\times}$ to $64{\times }$ , with a high reconstruction performance, as qualitatively demonstrated on a human data set. Two different versions of the encoder have been designed and tested, one with and the second without the adaptive compression, requiring an area of $230{\times }235\,\,\mu \text{m}$ and $200\times 190\,\,\mu \text{m}$ , respectively, while consuming only 0.47 $\mu \text{W}$ at 0.8 V. The system is powered by a 4-coil inductive link with measured power transmission efficiency of 36%, while the distance between the external and internal coils is 10 mm. Wireless data communication is established by an OOK modulated narrowband and an IR-UWB transmitter, while consuming 124.2 pJ/bit and 45.2 pJ/pulse, respectively.

openaire: EC/H2020/704947/EU//ADVANTAG5 In this paper, we show that amplitude transitions that are inherent to the multilevel outphasing radio transmitter architecture distort the transmitted signal due to time-domain discontinuities. In order to address this challenge, we propose a new transmitter architecture called tri-phasing which avoids discontinuities in signal waveforms and thus achieves significantly better linearity than multilevel outphasing. The output waveform in tri-phasing can be made continuous by representing the baseband signal with three components. One of the three components is amplified by discrete amplitude steps, whereas the other two are used to compensate the instantaneous shift in the output waveform due to the discrete amplitude step and to provide fine amplitude resolution. An implementation of the tri-phasing transmitter requires three phase modulators and additional digital signal processing. The system-level simulations performed in this paper demonstrate that the ACLR of a multilevel outphasing transmitter with 4 amplitude levels and 10-bit phase resolution is limited to -48 dBc, when simulated with a 100 MHz carrier-aggregated LTE downlink signal at 2.46 GHz carrier frequency. The proposed tri-phasing transmitter achieves -58 dBc ACLR with the same simulation parameters, indicating that continuous amplitude transitions can significantly improve the transmitter linearity.

Probabilistic gradient descent bit-flipping (PGDBF) is a hard-decision decoder for low-density parity-check (LDPC) codes, which offers a significant improvement in error correction, approaching the performance of soft-information decoders on the binary symmetric channel. However, this outstanding performance is known to come with an augmentation of the decoder complexity, compared to the non-probabilistic gradient descent bit flipping (GDBF), becoming a drawback of this decoder. This paper presents a new approach to implementing PGDBF decoding for quasi-cyclic LDPC (QC-LDPC) codes, based on the so-called variable-node-shift architecture (VNSA). In VNSA-based PGDBF implementations, the regularity of QC-LDPC connection networks is used to cyclically shift the memory of the decoder, leading to the fact that, a variable node (VN) is processed by different computing units during the decoding process. With this modification, the probabilistic effects in VN operations can be produced by implementing different types of processing units, without requirement of a probabilistic signal generator. The VNSA is shown to further improve the decoding performance of the PGDBF, with respect to other hardware implementations reported in the literature, while reducing the complexity below that of the GDBF. The efficiency of the VNSA is proven by ASIC synthesis results and by decoding simulations.

Feature extraction, such as spectral occupancy, interferer energy and type, or direction-of-arrival, from wideband radio-frequency (RF) signals finds use in a growing number of applications as it enhances RF transceivers with cognitive abilities and enables parameter tuning of traditional RF chains. In power and cost limited applications, e.g., for sensor nodes in the Internet of Things, wideband RF feature extraction with conventional, Nyquist-rate analog-to-digital converters is infeasible. However, the structure of many RF features (such as signal sparsity) enables the use of compressive sensing (CS) techniques that acquire such signals at sub-Nyquist rates; while such CS-based analog-to-information (A2I) converters have the potential to enable low-cost and energy-efficient wideband RF sensing, they suffer from a variety of real-world limitations, such as noise folding, low sensitivity, aliasing, and limited flexibility. This paper proposes a novel CS-based A2I architecture called non-uniform wavelet sampling. Our solution extracts a carefully-selected subset of wavelet coefficients directly in the RF domain, which mitigates the main issues of existing A2I converter architectures. For multi-band RF signals, we propose a specialized variant called non-uniform wavelet bandpass sampling (NUWBS), which further improves sensitivity and reduces hardware complexity by leveraging the multi-band signal structure. We use simulations to demonstrate that NUWBS approaches the theoretical performance limits of l1 -norm-based sparse signal recovery. We investigate hardware-design aspects and show ASIC measurement results for the wavelet generation stage, which highlight the efficacy of NUWBS for a broad range of RF feature extraction tasks in cost- and power-limited applications., IEEE Transactions on Circuits and Systems I: Regular Papers, 65 (2), ISSN:1549-8328, ISSN:1057-7122, ISSN:1558-0806

In this paper, we propose an asymmetrical length biasing scheme to be used in advanced nanometer technologies, which minimizes the energy per operation consumption of sub/near threshold digital CMOS circuits. Simulation results of two test circuits, a chain of inverters and a ripple carry adder, show that by using this sizing approach, the energy per operation can be reduced in more than 50% in a wide range of target performances. We use a 28-nm ultra-thin body and box fully depleted silicon-on-insulator technology and we show that the combination of supply voltage scaling, backplane biasing, and length biasing can be combined to obtain extremely robust (variability is almost halved) and energy efficient digital circuits. We also show simulation results for predictive technology models to show that the technique is also compatible with conventional bulk technologies.

This paper presents a low-power single-channel 8-bit loop-unrolled (LU) successive approximation register (SAR) analog-to-digital-converter (ADC) with a novel common-mode adaptive background comparator offset calibration scheme. LU-SAR ADCs use multiple comparators to reduce the SAR loop delay. Offset mismatch between the comparators severely degrades the effective resolution. This paper addresses the common-mode voltage variation in the LU-SAR architecture due to comparator kickback and the problems related to the common-mode dependency of the comparator offset. The proposed offset calibration scheme ensures that the comparators are calibrated at the same input common-mode voltage at which they each operate during the SAR conversion to prevent the common-mode dependent offset mismatch between them. Moreover, the proposed ADC design exploits the common-mode variation immunity of the proposed calibration scheme to optimize the figure-of-merit (FoM). The prototype ADC manufactured in 28nm FDSOI CMOS achieves 42.57dB signal-to-noise-and-distortion ratio and 22.8fJ/conv.-step FoM at 800MS/s with near Nyquist frequency input, and occupies an area of 0.0037mm(2).

This paper presents a highly sensitive phase-variation sensor for dielectric constant measurements based on a capacitively-loaded periodic slow-wave transmission line. Such line is implemented in microstrip technology, and the loading capacitors are formed by closely spaced rectangular patches. The sensing area of the device is delimited by the region occupied by the capacitive patches, where the material under test (MUT) must be located. The presence of the MUT modifies the coupling capacitance between adjacent patches, thereby producing a variation in the electrical length, or phase of the transmission line, which is the output variable. A detailed analysis of the equivalent circuit model of the unit cell, useful for design purposes, is carried out in the paper. Based on such analysis, a prototype device sensor is designed and fabricated. It is demonstrated in the paper that the sensitivity of the proposed sensor is by far superior to the one achieved in an ordinary meandered line with similar sensing area. Thus, the proposed slow-wave structure constitutes a good alternative to meandered lines for the implementation of phase-variation sensors with simultaneously high sensitivity and compact size.

This paper proposes to utilize intentional time delays as part of controllers to improve the damping of electromechanical oscillations of power systems. Through stability theory, the control parameter settings for which these delays in Power System Stabilizers (PSSs) improve the small signal stability of a power system are systematically identified, including the key parameter settings for which stability regions in the parameter plane remain connected for effective operation. The paper shows that PSSs with two control channels can be effectively designed to achieve best damping characteristics for a wide range of delays. Analytical results are presented on the One-Machine Infinite-Bus (OMIB) electromechanical power system model. To demonstrate the opportunities in more realistic dynamic models, our results are then implemented via numerical analysis on the IEEE standard 14-bus system.

This paper proposes a family of integrated multiple output isolated dc–dc converters, in which switches are hybrid utilized. Compared with the conventional separate $N$ -output isolated converter, which employs $2N$ primary switches, only $N$ +1 switches are required in the primary side of proposed converters to independently regulate $N$ secondary output voltages. Therefore, the number of switches is greatly reduced, contributing to lower cost. In this paper, detailed topology derivation is first introduced. A diversity of integrated multiple output topologies is derived with different cell connections and different cell configurations, including the asymmetrical flyback, forward as well as a half-bridge. Their performance characteristics are different and thus they are suitable for different applications. Then, in order to obtain a comprehensive insight of the proposed converters, a simplified dual-output asymmetrical flyback converter with three primary switches is taken as an example to be introduced in detail. Each output voltage in the converter is regulated with individual duty cycle, and zero-voltage-switching operation is achieved for all switches over the whole load range. Finally, experimental results based on a prototype circuit with two 12-V/3-A and 5-V/4.8-A outputs are also provided to validate converter effectiveness.

In-memory computing provides unprecedented power and area efficiency for the execution of convolutional neural networks by using memory bitcells to perform dot-product (DP) operations in the analog domain. Yet, these operators suffer from analog non-idealities (ANIs) that degrade the inference accuracy. This paper proposes design guidelines inferred from a holistic simulation-based analysis of the impact of ANIs on the accuracy-efficiency trade-off that affects current-domain DP operators based on conventional 6T-SRAM bitcell arrays. We define a custom SNR metric aware of the DP operand distribution to quantify decision errors associated with various ANIs, over ranges of input/output resolution and hardware design parameters. We find out that non-linearity and local mismatch are the dominant ANIs limiting the design space, while IR drops turn out to be critical only when targeting high parallelism. We then quantify the accuracy-efficiency trade-off related to these dominant ANIs across the design space and propose optimal design choices. We notably identify that using larger operators can either improve or worsen the SNR depending on the target output resolution. Furthermore, we show that hardware calibration techniques which mitigate mismatch help to recover a fraction of the lost SNR, with greater effectiveness when scaling down the supply voltage.

The main focus of this paper is the presentation of reliable methods for the determination of the optimum coloring of a graph, commonly known in the literature as vertex coloring problem. It has been shown that networks of capacitively coupled oscillators can be used to solve vertex coloring problems. In this paper we address the negative impact of an unbalanced number of couplings for the oscillators on the performance of the network and compensate for this non-uniform coupling structure by an adjustment in the network itself. The negative effect of the memristor device-to-device variability of the $\text {NbO}_{\text {x}}$ memristor on the array functionality will be investigated and reduced via an adaptation of the memristor operating point. The main improvement in network performance is achieved by setting up a control procedure allowing the network to bypass the local solutions and converge to the global one. Two strategies inspired by global optimization algorithms will be proposed to allow the network to overcome sub-optimal solutions, and find the solution corresponding to the absolute minimum of a performance measure function of the vertex coloring problem.

This paper presents an ultrasound rangefinder system able to find relative distances among energy-constrained sensor nodes. The nodes build a swarm that is operated in collision and multipath rich environments. A new distance measurement technique combining Wake-up and Frequency Modulated Continuous Wave (FMCW) is proposed to enable the ranging while neglecting the echoes from passive reflectors in the environment. The building blocks of the sensor nodes comprise a transmitter, a wake-up receiver, and a ranging receiver, all implemented in a 65 nm CMOS technology. The transmitter includes two switched-capacitor converters and an output multiplexer to generate a four-level driving signal and broadcast either a wake-up sequence or a digitally synthesized ultrasound Chirp. The transmitter dissipates $0.43~\mu \text{J}$ and ${0.82~\mu \text {J}}$ to broadcast the wake-up signal and the Chirp, respectively. A mixer first architecture is exploited in the wake-up receiver to reduce the always-on power consumption of the nodes. The ranging receiver uses a heterodyne architecture suited for the FMCW. The power consumption of the wake-up receiver and ranging receiver is 23.6 nW and $0.56~\mu \text{W}$ , respectively. The proposed rangefinder is experimentally characterized up to a 1 m distance in air and dissipates $1.25~\mu \text {J}$ per measurement, achieving a resolution of 18.7 mm at 0.55 m.

This paper addresses and experimentally demonstrates a programmable linear equation solver by analog computation. A set of differential equations using transconductance devices directly translated from circuit theory converges to the linear equation solution. These energy-efficient analog techniques are experimentally demonstrated in a configurable analog platform. The resulting analog linear equation solution circuits are effectively analog filters. The paper analyzes the algorithmic issues and analog numerical analysis issues, including accuracy, convergence time, and the interpretation of condition number for analog solutions.

Multi-functional grid-tied inverters (MFGTIs) have been investigated recently for improving the power quality (PQ) of microgrids (MGs) by exploiting the residual capacity (RC) of distributed generators. Several centralized and decentralized methods have been proposed to coordinate the MFGTIs. However, with the increasing number of the MFGTIs, it demands a method with improved reliability and flexibility, which are characteristics of distributed framework that has not been introduced into the PQ improvement (PQI) field before. In this paper, we propose a distributed consensus method to undertake the PQI task. The task is proportionally shared among the MFGTIs according to their instant RCs. Besides, most of the existing methods assume that the RCs of the MFGTIs are sufficient for tackling the PQ problem (PQP), which is not always true. In the case of insufficient RC, the active power output of each MFGTI is scaled down by the same factor determined by a proposed leader-follower protocol to make room for the task. In summary, the PQP is dealt with in both cases of sufficient and insufficient RC under the distributed control framework. Finally, simulations and hardware-in-the-loop experiments of an MG consisting of three 10kVA MFGTIs are presented to verify the effectiveness of the proposed methods.

International audience; We are considering the problem of controlling a DC-DC switched power converter of the Buck type. The converter involves an inherent control limitation; accordingly the control signal (duty ratio) can only take values in the interval (0, 1) . In the relevant literature, such a physical control limitation is generally not taken into account when designing the converter regulators. This is only dealt with in the control implementation stage, placing an isolated limiter between the (linear) controller and the controlled system. Furthermore, the presence of such a limiter is generally ignored when analyzing the closed-loop control system. In the present paper, the control signal limitation is dealt with using a nonlinear regulator that involves an internal limiter. The resulting closed-loop control system is shown to be equivalent to a nonlinear feedback involving a linear dynamics block in closed-loop with a nonlinear static element. Using absolute stability tools, sufficient conditions are established for the involved feedback to be L 2 -stable. If these conditions are respected when choosing the control design parameters then the regulator meets its objectives (closed-loop stability and output reference tracking). It is worth noting that, though the focus is made on a specific power converter, the paper includes an important theoretical dimension that may be of general interest.

In this paper, the finite-time sliding mode control issue is studied for a series of semi-Markov jump systems subject to actuator faults, where an asynchronous control method is adopted to overcome the non-synchronous phenomenon between the system mode and controller mode. Additionally, the event-triggered protocol, which determines whether the transmission of data should be performed according to the threshold condition, is introduced to alleviate the burden of data transmission in the communication channel. This paper aims to devise an asynchronous event-triggered sliding mode control law so as to guarantee the trajectories of the resulting closed-loop system can be forced onto the predefined sliding surface in a finite-time interval. Thence, by means of the mode-dependent Lyapunov functions and the finite-time theory, sufficient conditions are derived to assure that the closed-loop system is mean-square finite-time bounded in both reaching and sliding motion phases. Eventually, a numerical example and a tunnel diode circuit model are presented to illustrate the availability and practicability of the proposed approach.

In this paper, we present a new fast Fourier transform (FFT) hardware architecture called constant multiplier (CM) FFT. Whereas rotators in previous architectures must rotate among several different angles, the CM FFT exploits the use of constant multipliers to calculate the rotations. The paper explores the 4-parallel and 8-parallel radix-2 CM FFT, which calculates the FFT entirely by using constant multipliers. Later, radices $2^{k}$ are presented, with emphasis in radix-24 and radix-25 as the best alternatives. Experimental results for a 1024-point radix-25 CM FFT show that the proposed approach reduces the number of block random-access memories (BRAM) and digital signal processing (DSP) slices with respect to previous approaches, while achieving the highest clock frequency for a 4-parallel FFT architecture on field-programmable gate arrays (FPGAs) reported so far.

In many sensor applications, a high-resolution analog-to-digital converter (ADC) is a key block. The use of an incremental delta-sigma ADC (IADC) is often well suited for such applications. While the energy-efficiency of IADCs has improved by several orders of magnitude over the past decade, the implementation of high performance IADCs, especially in battery-powered systems, is still challenging. This paper presents a tutorial review on energy-efficient IADCs and addresses the progress in this area. This paper describes the fundamentals of IADCs and energy-efficient hybrid IADC architectures. Various design techniques for improving the energy-efficiency of the IADCs are described. This paper is intended to serve as a starting point for the development of a new energy-efficient IADC.

Truncation is one of the most commonly used approaches for circuit-level approximate computing. This paper proposes a scheme for error compensation of arithmetic circuits in which a so-called padding is utilized to compensate at the output for the truncated bits of the input operands. Compensation relies on adjusting the output results of an arithmetic circuit; the padding takes a value determined by utilizing statistical information based on profiling an arithmetic circuit to reduce the average signed difference between the inexact and exact values and so the mean square error. An extensive analysis and simulation-based evaluation of error metrics are performed on signed truncated adders, multipliers and dividers; an excellent agreement is found. Additional design metrics such as power consumption and circuit complexity are also assessed. Different applications of approximate arithmetic circuits with the proposed output error compensation scheme are presented. Matrix multiplication and image processing (changing detection) are investigated to show the effectiveness of the scheme proposed in this paper.

This paper is concerned with bipartite tracking for double-integrator networked systems with signed communication graphs, where both cooperative and antagonistic interactions coexist. A finite-time bipartite tracking framework is established, where followers track either the state or the opposite state of a leader. Different from some conventional results with convergence over an infinite time horizon, the finite-time convergence in this paper is achieved in an accurate manner. Under structurally balanced signed graphs, an integral sliding mode based finite-time bipartite tracking controller is proposed. The construction of an integral sliding mode variable is to ensure that the system dynamics is driven onto a sliding surface in finite-time. On the sliding surface, neighbouring states are used together with the homogeneous technique to guarantee that bipartite tracking is achieved in finite-time. To further realize fixed-time bipartite tracking, a controller is designed by using the integral sliding mode and the bi-limit homogeneous concept. Finally, numerical examples are provided to demonstrate the effectiveness of the proposed controllers.

Solving continuous problems on digital computers gives generally only approximations of the continuous solutions. It is therefore crucial that the error between the continuous solution and the digital approximation can effectively be controlled. This paper investigates the possibility of simulating linear, time-invariant (LTI) systems on Turing machines. It is shown that there exist elementary LTI systems for which an admissible and computable input signal results in a non-computable output signal. For these LTI systems, the paper gives sharp characterizations of input spaces such that the output is guaranteed to be computable. The second part of the paper discusses the computability of the impulse and step response of LTI systems. It is shown that the computability of the step response implies not the computability of the impulse response. Moreover, there exist impulse responses which cannot be computed from the transfer function using the inverse Laplace transform. Finally, the paper gives a stronger version of a classical non-computability result, showing that there exist admissible and computable initial values for the wave equation so that the solution cannot be computed at certain points in space and time.

This paper provides a review of design approaches towards artificial intelligence (AI) System-on-Chip. AI algorithms have progressed over the past decades from perceptron-based neural network (NN) and neuro-fuzzy (NF) system to today’s deep neural network (DNN) and neuromorphic computing. Recent DNN hardware accelerators focus on energy-efficient integration of digital circuits to realize real-time DNN operation while neuromorphic processors deploy new memory technologies with analog computation for low power consumption. However, different design approaches can be applied to such processor implementation with their pros and cons. This paper reviews from the early processor designs for NN and NF in both mixed-mode and digital implementations to the recent DNN SoC designs that we have proposed for a decade. The former content deals with NN and NF processors used as a functional building block of a machine vision SoC, while the latter concentrates on integration of the whole DNN function. We also provide a discussion on the approaches, and provide perspective on future research directions.

Modern communication standards, such as 5G new radio (5G NR), require a high speed decoder for highly irregular quasi-cyclic low density parity check (QC-LDPC) codes. A widely used approach in QC-LDPC decoders is a layered decoding schedule which processes the parity check matrix in parts, thus providing faster convergence. However, pipelined layered decoding architecture suffers from data hazards that reduce the throughput. This paper presents a novel architecture, which can facilitate any QC-LDPC decoding without stall cycles caused by pipeline hazards. The decoder conveniently incorporates both the layered and the flooding schedules in cases when hazards occur. The paper also presents the genetic algorithm based optimization of the decoding schedule for better signal-to-noise ratio (SNR) performance. The proposed architecture enables insertion of a large number of pipeline stages, thus providing high operating frequency. As a case study, the FPGA implementation for WiMAX, DVB-S2X, and 5G NR provided coded throughput of up to 1.77 Gbps, 4.32 Gbps, and 4.92 Gbps at 10 iterations, respectively. The results show a strong throughput increase of 30%–109% compared with the conventional layered decoder for 5G NR for the same SNR performance. The decoder provides highly efficient utilization of resources when compared with the state-of-the-art solutions.

In this paper, we propose a new scheme to directly power a 4.9-5.6GHz LC oscillator from a recursive switched-capacitor DC-DC converter. A finite-state machine is integrated to automatically adjust the conversion ratio and switching frequency of the converter such that its DC output voltage is within ±5% of the desired 1V across input voltage range 1.3-2.2V and < 2mA load current conditions. A gate-driver circuit is embedded in each switch of the converter to guarantee constant on-resistance across PVT variations without sacrificing device reliability. Furthermore, a spur reduction block (SRB) is embedded in the oscillator to suppress the ripple induced spurs by stabilizing its tail current. Both the converter and the oscillator are implemented in 40-nm CMOS technology. The measured peak power efficiency of the converter is 87%, while its spot noise is < 1.5nV/Hz which does not degrade the phase noise of the oscillator. The SRB suppresses the spur to

This paper presents a high-performance solar energy harvesting system with improved adaptive maximum power point tracking (AMPPT) method utilizing neural network (NN) model as assistance. Under the guidance of the negative feedback control (NFC) model, a BJT based voltage control oscillator with three off-chip reconfigurable resistors is designed in this paper to improve the reusability of the solar energy harvesting system. Meanwhile, the AMPPT accuracy has much improvement by co-simulation of MATLAB/Simulink and Virtuoso with the help of NN model of Photovoltaic (PV) Cell. The complete system with output voltage of 4.2V to power the battery is designed and fabricated in $0.18~\mu \text{m}$ CMOS technology. According to the test results, the system can track the maximum power points (MPP) successfully with average voltage tracking errors of 0.23% (0.01-0.51%) of PV cell 1 and 0.29% (0.01-0.5%) of PV cell 2 when the light intensity changes from 3000lux to 10000lux. Without power hungry current sensor or voltage sensor and other complicated control circuits, the peak efficiency is about 89.39% @ 3000lux.

This paper presents a reconfigurable delta-sigma modulation (DSM) architecture for concurrent multi-band transmission. The reconfigurability in terms of carrier spacing and the number of simultaneous carrier transmission is useful for applications such as carrier aggregation in 5G. This paper uses $4^{th}$ order reconfigurable multi-band DSM (RMB-DSM) such that the zeros of the noise transfer function can be reconfigured to fall at multiple frequencies, where the carriers are being aggregated. The quantization noise between the transmission bands is a critical issue in the case of multi-band transmission. Therefore, a multi-band additional noise shaping (ANS) function is also introduced, which generates notches around each carrier and reduces the noise level between the multiple pass-bands. The proposed scheme has been validated in simulation, as well as in experiment for aggregating up to four 15 MHz long term evolution (LTE) signals with an overall aggregated bandwidth of 60 MHz. Measurement results show a 10-25% improvement in coding efficiency and 15-35 dB improvement in noise level near the operating frequency band using the proposed multi-band augmented noise shaping technique, as compared to the standard DSM. The corresponding improvement of 8% in the overall efficiency is observed by using the proposed multi-band augmented noise shaping technique.

This paper presents the design of a low power, compact multi-channel single-shot time-to-digital converter (TDC) capable of handling multiple hits per channel. The system has 17 hit channels and 1 trigger channel and is designed to meet the requirements of the iron calorimeter detector in the India-based neutrino observatory. The TDC core consists of a delay chain stabilized by a delay-locked loop (DLL) and synchronous counters. The digital backend is programmable to allow for multiple configurations during the operation. The common core to all channels with concurrent accessibility, choice of core clock frequency optimizing the trade-offs between performance, power and area, and optimal backend logic result in a compact and low power design. It achieves a single-shot precision better than 65 ps. The $0.13\,\mathrm {\mu m}$ chip occupies an active area of 3.72mm2 and consumes 3.4mW per channel. This paper also reviews the theory on how timing precision is defined for a single-shot TDC and explains how the test plan can be devised based on the jitter in the system.

This paper describes a binary frequency shift keying (BFSK) transmitter architecture designed with a technique involving signal generation, mixing, and image rejection for low-power operation. The method enables the coherent generation of the two tones representing the BFSK symbols without changing the phase-locked loop (PLL) output frequency, which relaxes the settling time requirements of the PLL and thus reduces power consumption by design. The architecture allows programmable data rates and channel bandwidths according to application-specific needs. This paper includes analyses of the transmitter signal generation and building blocks. Key design equations are derived to give insights into circuit implementation details. The 480 MHz transmitter was designed and fabricated in a standard 130 nm CMOS technology, and the measurement results provide the first proof-of-concept for the feasibility of this architecture. The transmitter operates around 480 MHz with programmable data rates of 1 Mbps and 10 Mbps. It consumes 170 μW and 180 μW with the two data rates using 0.6 V and 1 V supplies for analog and digital blocks respectively. State-ofthe-art figures of merit for power-efficient BFSK transmission of 170 pJ/bit and 18 pJ/bit are achieved at the data rates of 1 Mbps and 10 Mbps.

DRAM devices require periodic refresh operations to preserve data integrity. Slowing down the refresh rate can reduce the energy consumption; however, it may cause a loss of data stored in the DRAM cell. This paper proposes a new memory architecture of soft approximation for deep learning applications, which reduces the refresh energy consumption while maintaining accuracy and high performance. Utilizing the error-tolerant property of deep learning applications, the proposed memory architecture avoids the accuracy drop caused by data loss by flexibly controlling the refresh operation for different bits, depending on their criticality. For data storage, the approximate DRAM architecture reorganizes the data so that these data are sorted according to their bit significance. Critical bits are stored in more frequently refreshed devices while non-critical bits are stored in less frequently refreshed devices. In addition, for further reduction of the DRAM energy consumption, this paper combines hard approximation, which reduces the number of accesses to DRAM, with soft approximation. Simulation results show that the refresh energy consumption is reduced by 69.71%, and the total energy consumption is reduced by 26.0 % for the hybrid memory with a negligible drop in both training and testing phases on state-of-the-art deep networks.

International audience; The problem of relaxed state estimation design of multi-instant fuzzy switching observer for discrete-time nonlinear systems is studied by proposing a deep division approach. Firstly,both the enhancement factor and the attenuation factor for each normalized fuzzy weighting function are for the first time introduced synchronously in order to derive much finer subdivisions of the whole spanning space constituted by all the normalized fuzzy weighting functions. Consequently, a more advanced ranking-based switching mechanism can be proposed over the previous results. Secondly, a new multi-instant fuzzy switching observer with different gain matrices for each finer subdivision is designed with the help of the given switching mechanism and thus much more freedom can be brought for reducing the conservatism of existing designs of fuzzy observers. More importantly, it is worth noting that the calculation of all the involved gain matrices belongs to a feasible off-line process. Finally, two simulation examples including tunnel diode circuits are provided to validate the progressiveness of the proposed deep division approach.

International audience; First, this paper proposes a double-node-upset (DNU)-completely-tolerant (DNUCT) latch, featuring quadruple cross-coupled dual-interlocked-storage-cells (DICEs) with a C-element. Due to the existence of sufficient feedback loops, the latch can achieve complete DNU toleration. Second, this paper proposes an improved DNUCT latch (referred to as the TNUCT latch) by inserting a redundant level of C-elements at the output stage to intercept node-upset errors accumulated in the upstream DICEs so as to completely tolerate any possible triple-node-upset (TNU). Simulation results demonstrate the robustness of the proposed latches. These innovative latches are also cost-effective due to the use of high-speed transmission paths, clock gating, and fewer transistors. Compared with the typical TNU hardened latch (TNUHL) design that can completely tolerate any TNU, the proposed TNUCT latch reduces the delay-power-area product by approximate 98%. The proposed latches have less or equivalent sensitivity to process, voltage, and temperature variation effects compared with reference latches.

IEEE Transactions on Circuits and Systems I: Regular Papers, 67 (3), ISSN:1549-8328, ISSN:1057-7122, ISSN:1558-0806

Video display processing is an indispensable module in a variety of multimedia systems. With the increase of video format to 4K $\times$ 2K@60fps, the design of efficient display processing circuit faces severe challenges. This paper presents a video display processor which supports a variety of video formats and integrates multiple advanced algorithms for perpetual image quality improvement. By leveraging algorithm and architecture co-design, this paper efficiently implements these computational and memory intensive display processing algorithms in a single chip. In particular, we describe three representative design modules in detail, including motion compensated frame rate up-conversion, content-adaptive contrast enhancement, and backlight local dimming. Extensive experiments demonstrate that the proposed design modules outperform the previous works in terms of either image quality or hardware efficiency. The overall chip is fabricated in GF 55nm CMOS technology, and can work at the maximum operating frequency of 594 MHz. The maximum input and output video formats reach up to 4K $\times$ 2K@60fps.

This paper presents the theory of a novel memcomputing paradigm based upon a memristive version of standard Cellular Nonlinear Networks. The insertion of a nonvolatile memristor in the circuit of each cell endows the dynamic array with the capability to store and retrieve data into and from the resistance switching memories, obviating the current need for extra memory blocks. Choosing the parameters of each cell circuit so that the memristors may undergo solely sharp transitions between two states, each processing element may be approximately described at any time as one of two first-order systems. Under this assumption, the classical Dynamic Route Map may be employed to synthesise and analyse the data storage and retrieval genes. A new system-theoretic methodology, called Second-Order Dynamic Route Map , is also introduced for the first time in this paper. This technique allows to study the operating principles of arrays with second-order processing elements, as is the case, in the proposed network, if the set up of cell circuit parameters induces analogue memristive dynamics. This paper shows how the novel tool may be adopted to investigate the operating mechanisms of a cellular array with second-order cells, which compute the element-wise logical OR between two binary images.

This paper proposes a high-throughput energy-efficient Successive Cancellation (SC) decoder architecture for polar codes based on combinational logic. The proposed combinational architecture operates at relatively low clock frequencies compared to sequential circuits, but takes advantage of the high degree of parallelism inherent in such architectures to provide a favorable tradeoff between throughput and energy efficiency at short to medium block lengths. At longer block lengths, the paper proposes a hybrid-logic SC decoder that combines the advantageous aspects of the combinational decoder with the low-complexity nature of sequential-logic decoders. Performance characteristics on ASIC and FPGA are presented with a detailed power consumption analysis for combinational decoders. Finally, the paper presents an analysis of the complexity and delay of combinational decoders, and of the throughput gains obtained by hybrid-logic decoders with respect to purely synchronous architectures.

International audience; The charge pump phase locked loop (CP-PLL) is widely used subsystem in modern mixed-signal electronic systems that are utilized in digital and wireless applications such as clock generation, synchronization and frequency synthesis. In the classical mode, the combination of a current switched charge pump and a digital phase and frequency detector (CP-PFD) circuits produces an ideal pulse width modulated constant current during one sampling period, which permits a suitable transient performance. Nevertheless, many commercially used CP-PLL chips (e.g., 4046 family) have a voltage switched charge pump (VSCP) because the design of the constant voltage source is easier than the constant current generator and it is a low cost solution. However, the VSCP delivers a non-constant pump current, which varies during one sampling period related to the electrical load of the loop filter (LF). This effect results in a varying gain of the control system affecting significantly its tracking ability. Furthermore, due to its hybrid structure, the simulation of the CP-PLL at high frequencies is challenging and the analysis of its transient characteristics during its non-linear acquisition procedure is not easy. In this paper, a first ever exact and nonlinear model based on the phase equations of the second order voltage switched charge pump phase locked loop (VSCP-PLL) is established by using an event driven (ED) technique. This exact model is then simplified by using a step-wise quasi-constant current approximation during one sampling period to obtain the analytical phase equations. The derived ED-model is validated at transistor level simulations using 130 nm CMOS process. Furthermore, some typical nonlinear features of the VSCP-PLL are explored and the developed ED-models are compared with the quasi-time-continuous (QTC) theory.

This paper presents simple but accurate expressions for the noise components caused by clock jitter, in the output signal of self-oscillating sigma delta modulators (SOSDM). Contrary to conventional continuous time sigma delta modulators (CTSDM), the SOSDM's loop contains a strong oscillation, whose attribution to the system's jitter caused noise has not previously been explored. In this paper, the SOSDM system is modeled, and the effect of the self oscillation, the input signal and the quantization noise on the jitter caused noise in the output signal, is calculated. Results are confirmed by system level simulations.

This paper presents a statistical model to accurately estimate post-FEC BER for high-speed wireline links using standard linear block codes, such as the RS(544,514,15) KP4 and RS(528,514,7) KR4 codes. A hierarchical approach is adopted to analyze the propagation of PAM-symbol and FEC-symbol errors through a two-layer Markov model. A series of techniques including state aggregation, time aggregation, state reduction, and dynamic programming are introduced making the time complexity to compute post-FEC BER below 10−15 reasonable. Error bounds associated with each method are found. The efficiency of the proposed model allows it to handle a larger state space, more DFE taps, and more sophisticated linear block codes than prior work. A 4-PAM 60 Gb/s wireline transceiver fabricated in a 7 nm FinFET technology is used as a test vehicle to validate this model. Measured data with two different channels reveals that the statistical model can properly predict the post-FEC error floor with standard FEC codes. While this paper demonstrates the method for capturing DFE error propagation, the method is general and can be applied to model other communication systems having memory effects. Moreover, our proposed model can be easily extended to higher-level PAM schemes and other advanced equalizer architectures to assist in making architectural choices for wireline transceivers.

Distributed arithmetic (DA)-based approximate structures are used for efficient implementation of inner-products in various error-resilient applications. In the existing literature, most of these approximate architectures are developed by truncating the least significant bits (LSBs) of the inputs and/or the multiplying coefficients. The existing works do not provide any analytical study to evaluate and design an approximate structure. To address this issue, an analytical framework is proposed in this paper. It is shown that the analytical results match very closely with the Monte Carlo simulation results. The proposed framework reveals that the truncation of the LSBs of partial inner-products is a promising alternative to design more efficient DA architectures with less error. Following these observations, a novel approach to truncate the LSBs of partial inner-products, namely, a weight-dependent truncation strategy and its two variants with a suitable error compensation function are presented in this paper. Synthesis results, accuracy analysis, and evaluation in two commonly used error-tolerant applications demonstrate the superiority of the proposed architectures over the state-of-the-art DA-based approximate structures.

This paper deals with the problem of observer-based fault estimation (FE) for discrete-time nonlinear systems via a weighted switching approach. A pair of variable weights is introduced in an efficient but straight-forward way, and thus, the space spanned by the prescribed normalized fuzzy weighting function can be divided into a set of non-overlapping subspaces. A new fuzzy switching FE observer is proposed by designing exclusive FE observer gain matrices for each non-overlapping subspaces, and thus, less conservative off-line designed conditions for the proposed fuzzy switching FE observer are obtained than the previous results by adequately taking advantage of the characteristic information of each non-overlapping subspaces. More importantly, the process of on-line deciding the current subspace’s index at each sampled point is very straightway and some previous time-consuming online operation is avoided, i.e., it can be said that the on-line computational burden also is alleviated in this paper. Finally, the proposed theoretical result is applied to a tunnel diode circuit and the advantages over existing literature are validated by means of objective comparisons.

Multiple output wireless power transfer (WPT) system has a great potential to be used in applications where multiple receivers need to be powered simultaneously, including wireless office table, logistic sorting robots, and magnetic resonant imaging (MRI) equipment. For the sake of reducing no-load losses and avoiding leakage magnetic fields, it is desirable to only switch on those transmitter coils that are covered by receivers and switch off the rests. To realize this, however, bidirectional power switches, sensors and control logic are needed, which are expensive, bloated, and lossy. This paper proposed a novel receiver-controlled coupler (RC-Coupler) that can realize switching on/off of transmitter coils without using bidirectional switches, sensors, and control. The structure, design considerations, and leakage fields of the proposed RC-coupler are researched, and its feasibility has been confirmed with a GaN-based 120 W, 6.78 MHz prototype. A power density of 2.78 W/cm³ is reached benefiting from the receiver-controlled characteristics.

The frequency-domain adaptive filter (FDAF) has been utilized in various applications where the length of the modeling filter is very long. The convergence behavior of the FDAF in the full-modeling case has been well analyzed. However, because the length of the true filter may be rather long and is unknown in practice, the length of the adaptive filter is usually less than that of the true system. In this paper, only the statistical behavior of the deficient-length constrained FDAF was analyzed for Gaussian inputs. This paper presents a unified approach to the stochastic analysis of a family of the FDAF in an under-modeling situation and for arbitrary input distributions. Specifically, the mean and mean-square convergence behaviors of FDAFs are presented, and the closed-form expression of the steady-state misalignment is given. Our theoretical results provide some new insights into the convergence property of deficient-length FDAFs. In addition, the analysis is carried out in the frequency domain directly. Computer simulations indicate an excellent agreement with our theoretical predictions.

This paper presents an energy-efficient spectral analysis method for the Internet of Things (IoT). The objective of this paper is to reduce the energy consumption of edge devices. The proposed method uses an autoregressive (AR) model for spectral analysis instead of the discrete Fourier transform, and its calculation process is distributed to the edge device and a base station by considering the energy consumption tradeoff of the data processing and the data communication. In this paper, the Yule-Walker method is employed for the AR coefficient calculation. The calculation process of Yule-Walker method can be divided into two parts: an autocorrelation calculation and an AR coefficient calculation. The autocorrelation calculation is implemented in the edge devices, and its dedicated hardware is designed using Verilog HDL. Meanwhile, the AR coefficient is calculated in the base station and is used for the spectral analysis. According to this distributed processing approach, the energy consumption of the edge device can be reduced compared with conventional DFT approaches using the fast Fourier transform (FFT). The system level energy consumption is evaluated assuming the IoT edge device, which has a wireless transceiver using Bluetooth low energy. The evaluation results show that the proposed method can reduce 79% of the edge device energy consumption for spectral analysis in a practical application.