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This paper presents an overview for low-power successive approximation register (SAR) analog-to-digital converters (ADCs). It covers the operation principle, error analysis, and practical design issues. Furthermore, this paper provides a comprehensive survey of state-of-the-art low-power design techniques for every circuit block in the SAR ADC, including comparator, capacitive digital-to-analog converter (DAC), and SAR logic. The goal of this paper is to provide a useful overview to SAR ADC designers who want to improve the energy efficiency targeting low-to-medium speed applications. [ABSTRACT FROM AUTHOR]

In this paper, aiming to systematically derive single-inductor multi-input multi-output (SI-MIMO) converters having favorable merits of high-density and low-cost, a basic model is firstly extracted from the working principle. Theoretically, by enumerating all possible connections of the basic model and one-by-one manually judging their effectiveness according to working criterions, multiple viable SI-MIMO topologies can be obtained, but with heavy workload. To simplify the topology derivation process, this paper also proposes a computer-aided method to replace the manual effort. By modelling the basic model and working criterions with graph theory, MATLAB codes can be developed to automatically screen out the effective topologies. With the proposed method, 8 three-port, 28 four-port and 115 five-port converters with single inductor are conveniently obtained, including both the existing and new topologies. Moreover, by configuring ports and switches in each derived topology, multiple specific converters can be further expanded. These converters can provide more options for practical engineering applications, and a new topology is also introduced and experimentally verified in the paper. [ABSTRACT FROM AUTHOR]

This paper presents a mixed-signal SRAM-based in-memory computing (IMC) macro for processing binarized neural networks. The IMC macro consists of $128\times 128$ (16K) SRAM-based bitcells. Each bitcell consists of a standard 6T SRAM bitcell, an XNOR-based binary multiplier, and a pseudo-differential voltage-mode driver (i.e., an accumulator unit). Multiply-and-accumulate (MAC) operations between 64 pairs of inputs and weights (stored in the first 64 SRAM bitcells) are performed in 128 rows of the macro, all in parallel. A weight-stationary architecture, which minimizes off-chip memory accesses, effectively reduces energy-hungry data communications. A row-by-row analog-to-digital converter (ADC) based on 32 replica bitcells and a sense amplifier reduces the ADC area overhead and compensates for nonlinearity and variation. The ADC converts the MAC result from each row to an N-bit digital output taking 2N-1 cycles per conversion by sweeping the reference level of 32 replica bitcells. The remaining 32 replica bitcells in the row are utilized for offset calibration. In addition, this paper presents a pseudo-differential voltage-mode accumulator to address issues in the current-mode or single-ended voltage-mode accumulator. A test chip including a 16Kbit SRAM IMC bitcell array is fabricated using a 65nm CMOS technology. The measured energy- and area-efficiency is 741-87TOPS/W with 1-5bit ADC at 0.5V supply and 3.97TOPS/mm2, respectively. [ABSTRACT FROM AUTHOR]

Instability and oscillation issues originating in high-voltage direct current (HVDC) systems comprising modular multilevel converters (MMCs) are gaining increasing interest in the research community. To detect such phenomena in advance, considerable effort has been devoted recently to developing MMC models for small-signal analysis. The derivation of such models is a challenging task due to the topology and complex control structure of MMCs, which results in them having a multi-frequency response. To address this issue, scholars developed methods based on dynamic phasors and harmonic state-space modelling, which, however, require extensive pen-and-paper computations. In this paper, the periodic small-signal analysis (PAC) is adopted to determine numerically several MMCs transfer functions. Such functions can be computed between any electrical circuit node or input/output port, without the need to recast the three-phase average MMC model to derive a linear equivalent one, possibly in the DQ-frame. We show how vector fitting allows converting these functions to equivalent algebraic representations, which can be profitably used to design MMCs and study their stability following some parameter changes. To showcase this feature, we exploit one of these transfer functions to detect DC-side instability in a point-to-point HVDC system. [ABSTRACT FROM AUTHOR]

This paper presents a high-precision bandgap voltage reference (BGR) with high-order temperature compensation. The compensation signal is generated by using both strong-inversion MOSFETs and Bipolar Junction transistors (BJTs), which cancels the high-order nonlinear term $T\ln (T)$ in the BJT base-emitter voltage (VBE), and thus a low temperature coefficient (TC) over a wide temperature range is achieved. The proposed BGR circuit is fabricated in a 0.18- $\mu \text{m}$ CMOS process with an active area of $0.256 m{m^{2}}$ and a max power consumption of 1.35 mW. A minimum TC of 0.706 ${\mathrm{ppm}}/{}^ \circ C$ from $- 25\,\,{}^ \circ C$ to 125 ${}^ \circ C$ is achieved after an 8-bit resistance trimming. The line sensitivity is 0.0146%/V operating from 3.2 V to 3.7 V. The BGR achieves a power supply rejection (PSR) of −63.4 dB and a noise spectrum density of $0.92 ~\mu \text{V}/\sqrt {Hz} $ at 10 Hz. [ABSTRACT FROM AUTHOR]

The paper discusses the relationships between electrical quantities, such as voltages, currents, and frequency, and geometrical ones, namely curvature and torsion. The proposed approach is based on the Frenet frame utilized in differential geometry and provides a general framework for the definition of the time derivative of electrical quantities in stationary as well as transient conditions. As a byproduct, the proposed approach unifies and generalizes the time- and phasor-domain frameworks. Other noteworthy results are a new interpretation of the link between frequency and the time derivatives of voltage and current; and a definition of the rate of change of frequency that includes the novel concept of “torsional frequency.” Several numerical examples based on balanced, unbalanced, harmonically-distorted and transient voltages illustrate the findings of the paper. [ABSTRACT FROM AUTHOR]

Welcome to this Special Issue, a collection of selected papers presented at the 2016 IEEE International Symposium on Circuits and Systems (ISCAS 2016), held in Montreal, QC, Canada, 22–25 May 2016. More than 1000 delegates attended the conference, where 781 papers were presented, selected from 1687 papers submitted across 15 tracks. [ABSTRACT FROM PUBLISHER]

Presents institutional listings relating to this publication. [ABSTRACT FROM PUBLISHER]

These instructions give guidelines for preparing papers for this publication. Presents information for authors publishing in this journal. [ABSTRACT FROM PUBLISHER]

These instructions give guidelines for preparing papers for this publication. Presents information for authors publishing in this journal. [ABSTRACT FROM PUBLISHER]

This paper introduces add-equalize structures for the implementation of linear-phase Nyquist (Mth-band) finite-length impulse response (FIR) filter interpolators and decimators. The paper also introduces a systematic design technique for these structures based on iteratively reweighted \ell 1-norm minimization. In the proposed structures, the polyphase components share common parts which leads to a considerably lower implementation complexity as compared to conventional single-stage converter structures. The complexity is comparable to that of multi-stage Nyquist structures. A main advantage of the proposed structures is that they work equally well for all integer conversion factors, thus including prime numbers which cannot be handled by the regular multi-stage Nyquist converters. Moreover, the paper shows how to utilize the frequency-response masking approach to further reduce the complexity for sharp-transition specifications. It also shows how the proposed structures can be used to reduce the complexity for reconfigurable sampling rate converters. Several design examples are included to demonstrate the effectiveness of the proposed structures. [ABSTRACT FROM AUTHOR]

This paper studies stability of stochastic impulsive switched systems. Different from exponential Lyapunov function and average dwell-time in the previous works, general Lyapunov function and fixed dwell-time are implemented in this paper to analyze input-to-state stability and global stability of stochastic impulsive switched systems. Two cases are investigated, that is, the case that the continuous dynamics is stable and the case that the discrete dynamics is stable. To implement multiple Lyapunov functions, there are two subcases considered in this paper: the subcase that the estimates on the derivatives of the multiple Lyapunov functions are the same and the subcase that the growths of the multiple Lyapunov functions by the jumps are the same. For aforementioned different cases, sufficient stability conditions are established for stochastic impulsive switched systems. Finally, the developed theory is illustrated through examples from networked control systems and synchronization problem of 3-D novel chaotic circuit systems. [ABSTRACT FROM PUBLISHER]

This paper proposes a hybrid dynamic model of thyristor controlled series compensators (TCSCs). The objective is to demonstrate, through advanced circuit theory tools and numerical simulations that some modeling aspects are not properly taken into account in the existing literature. In particular, we consider those related to the role of the TCSC impedance when the line current is polluted by harmonics and to the phase-locked loops (PLLs). Shooting methods and periodic small signal analyses are utilized to compute the impedance of the TCSC at sub-harmonics that are typical of the sub-synchronous resonance phenomenon. The case study focuses on the impact of sub-harmonics, on the behavior of the TCSC and on the synchronization of the firing angle through the PLL. Modeling recommendations are finally drawn based on the results presented in this paper. [ABSTRACT FROM PUBLISHER]

In this paper, we present new feedforward FFT hardware architectures based on rotator allocation. The rotator allocation approach consists in distributing the rotations of the FFT in such a way that the number of edges in the FFT that need rotators and the complexity of the rotators are reduced. Radix-2 and radix-2k feedforward architectures based on rotator allocation are presented in this paper. Experimental results show that the proposed architectures reduce the hardware cost significantly with respect to previous FFT architectures. [ABSTRACT FROM PUBLISHER]

This paper investigates the regularity, non-impulsiveness, stability and admissibility of the singular fractional-order systems with the fractional-order $\alpha \in (0,1)$. Firstly, the structure, existence and uniqueness of the time domain solutions of singular fractional-order systems are analyzed based on the Kronecker equivalent standard form. The necessary and sufficient condition for the regularity of singular fractional-order systems is proposed on the basis of the above analysis. Secondly, the necessary and sufficient conditions of non-impulsiveness as well as stability are obtained based on the proposed time domain solutions of singular fractional-order systems, respectively. Thirdly, two novel sufficient and necessary conditions for the admissibility of singular fractional-order systems are derived including the non-strict linear matrix inequality form and the linear matrix inequality form with equality constraints. Finally, two numerical examples are given to show the effectiveness of the proposed results. [ABSTRACT FROM AUTHOR]

In this paper, a novel class of quaternion-valued memristive neural networks (QVMNNs) that considers both the spatial factor and Markov jump phenomenon is proposed, the finite/fixed-time anti-synchronization (F/FTAS) of which is investigated. It is worth mentioning that the considered master and slave systems are assumed to jump along two inconsistent Markov chains, which is a first attempt at the issue of the anti-synchronization of Markovian systems and may be more realistic than most existing Markovian systems’ models. Then, a suitable feedback controller is designed, such that the error system can be finite/fixed-time stable. Moreover, by integrating algebraic inequality technologies and Lyapunov theory, a new F/FTAS theorem can be obtained for the proposed systems. Finally, this paper provides two examples, so that the rationality, superiority, and practical value of the main results can be illustrated. [ABSTRACT FROM AUTHOR]

Although the cyber-physical system stability is widely studied, scholars focus more on system stability with communication time delay. Therein, grid-connected inverters with the digital control system are regarded as one simplest and typical cyber-physical system. Meanwhile, the switching/sampling frequency of the inverter is always selected as low as possible from an efficiency viewpoint, resulting in unavoidable delay time. This delay time is apt to cause the system instability, which is more prone to severity under weak grid. To this end, this paper provides a minimum switching/sampling frequency for grid-connected inverters. Firstly, the system impedance model with equivalent delay time is constructed, which is based on padé approximate approach. This equivalent delay time consists of three parts, i.e., sampling delay time in cyber/physical level, calculation delay time in cyber level and pulsewidth modulation delay time in physical level, which reflects the cyber-physical interaction impact. Furthermore, the stability forbidden criterion is applied to make the switching/sampling frequency solving process become Hurwitz matrix identification problem through space mappings. Based on these space mappings, an adaptive step search approach is adopted to obtain the minimum switching/sampling frequency. Finally, the proposed approach can well evaluate the system stability under different frequencies through simulation and experiment. [ABSTRACT FROM AUTHOR]

In this paper, the distributed optimal containment control problem for multiple nonholonomic mobile robots (NHMRs) differential game is studied via reinforcement learning. An approximation-based optimal control strategy is developed to ensure the optimal performance index and avoid the potential collision among agents. Firstly, the collision avoidance problem considered in this paper is addressed by exploiting a consensus-like interconnection on a directed graph and an error transformation function. Then, on the basis of the optimal backstepping technique, a single critic neural network is adopted to obtain the solution of the coupled Hamilton-Jacobi (HJ) equation, in which an improved learning mechanism is constructed to relax the requirement on initial control conditions. In addition, based on the Lyapunov stability theory, it is proved that all signals in the closed-loop optimal control are uniformly ultimately bounded. Finally, the proposed control protocol is applied to NHMRs system, which verifies that the solution of the coupled HJ equation solves the containment problem of differential game. [ABSTRACT FROM AUTHOR]

This paper presents an improved correlation-based timing-skew calibration strategy with constant input impedance characteristics. A full sampling rate operating time-interleaved reference ADC (TI-RADC) whose interleaving factor is coprime with TI-ADC is introduced to replace the conventional single-channel reference ADC. This paper theoretically demonstrates that by setting an appropriate time interval between the sampling edge of TI-ADC and TI-RADC and aligning the sampling edge of each channel in TI-ADC with each other but not with the reference ADC, the skew of the TI-RADC would not affect the timing skew calibration of the TI-ADC. A prototype 13-bit 2-GS/s 8-way TI pipelined SAR ADC employing a 1-bit 3-way TI-RADC is fabricated in 28-nm process to verify the presented calibration strategy. Measurement results demonstrate the correctness of the calibration strategy and reveal that compared with using single-channel reference ADC operating at a decimated sampling rate, the spurs resulting from the time-variant input impedance are suppressed more than 20 dB. The prototype ADC achieves an SNDR of 60.36 dB with a near Nyquist rate input when operating at 2-GS/s. The power consumption of the prototype ADCis 252.6 mW (Including the 4.1 mW estimated digital calibration), which translates into a Walden FoM of 148.3-fJ/conversion-step. [ABSTRACT FROM AUTHOR]

Clock skew and component mismatches in continuous-time DACs introduce two types of error: static error and dynamic error. Both types of error typically limit the performance of practical, high-resolution, and continuous-time DACs, but most prior calibration techniques primarily reduce only static error. An exception is a recently published mismatch noise cancellation (MNC) technique that adaptively measures and cancels both types of error over the DAC’s first Nyquist band. However, a disadvantage of the technique is that it requires an oversampling ADC that operates at several times the DAC’s Nyquist rate to prevent convergence error that would otherwise be caused by aliasing. This paper presents a sub-sampling version of the MNC technique that avoids this limitation at the expense of a lower calibration convergence rate. As proven in the paper, the subsampling MNC technique allows aliasing to occur, but in such a way that convergence error is avoided. [ABSTRACT FROM AUTHOR]

In this paper, a design methodology for SiGe HBT-based low-noise amplifiers (LNAs) is proposed that can be utilized for both sub-1-dB noise figure (NF) and wide bandwidth as an alternative to the conventional simultaneous input noise and power matching technique. This paper focuses on the removal of the series base inductor and the inclusion of an output matching network as a design parameter that can be used to achieve both sub-1dB NF and wide bandwidth. The effects of the mentioned design parameters on NF and bandwidth are described and analyzed, including the comparison of results with the conventional design technique. To demonstrate the validity of the analysis and impact of utilizing base-to-collector capacitance on LNA performance metrics, two different LNAs implemented in a 0.13- $\mu \text{m}$ SiGe technology. The first LNA achieves a lower than 1-dB NF with 26-dB gain at 8.5 GHz, and the second LNA exhibits wideband operation, with a better than 10-dB return losses in the range of 8–35 GHz and lower than 3-dB NF from 6 to 20 GHz. The sub-1-dB LNA reaches −17.3 dBm of input-referred compression point (IP1dB), with a power consumption of 62 mW and an area of 0.795 mm2. The wideband LNA achieves 17.6 dB of peak gain with a 48.5-mW power consumption and 0.69-mm2 chip area. To the best of our knowledge, this paper achieves the best NF performance in the literature utilizing a SiGe technology, while the wideband LNA exhibits the best operational bandwidth, together with a reasonable low-noise performance. [ABSTRACT FROM AUTHOR]

Approximate computing is an emerging trend in digital design that trades off the requirement of exact computation for improved speed and power performance. This paper proposes novel approximate compressors and an algorithm to exploit them for the design of efficient approximate multipliers. By using the proposed approach, we have synthesized approximate multipliers for several operand lengths using a 40-nm library. Comparison with previously presented approximated multipliers shows that the proposed circuits provide better power or speed for a target precision. Applications to image filtering and to adaptive least mean squares filtering are also presented in the paper. [ABSTRACT FROM AUTHOR]

This paper presents a COordinate Rotation Digital Computer (CORDIC)-based architecture for the computation of Nth root and proves its feasibility by hardware implementation. The proposed architecture performs the task of Nth root simply by shift-add operations and enables easy tradeoff between the speed (or precision) and the area. Technically, we divide the Nth root computation into three different subtasks, and map them onto three different classes of the CORDIC accordingly. To overcome the drawback of narrow convergence range of the CORDIC algorithm, we adopt several innovative methods to yield a much improved convergence range. Subsequently, in terms of convergence range and precision, a flexible architecture is developed. The architecture is validated using MATLAB with extensive vector matching. Finally, using a pipelined structure with fixed-point input data, we implement the example circuits of the proposed architecture with radicand ranging from zero to one million, and achieve an average mean of approximately 10−7 for the relative error. The design is modeled using Verilog HDL and synthesized under the TSMC 40-nm CMOS technology. The report shows a maximum frequency of 2.083 GHz with $197421.00~{\mu }\text{m}^{2}$ area. The area decreases to $169689.98~{\mu }\text{m}^{2}$ when the frequency lowers to 1.00 GHz. [ABSTRACT FROM AUTHOR]

This paper presents a low-power and area efficient 10-bit SAR ADC with higher side-reset-and-set (HSRS) switching scheme and hybrid capacitive-MOS (CAP-MOS) DAC. The HSRS switching scheme consumes zero switching energy for the two most-significant bits and skips unnecessary switching without using any auxiliary circuit. It is further verified in this paper that the HSRS switching scheme shows lower nonlinearity compared with the conventional CDAC structure with the same unit capacitor size and matching condition. This additional advantage permits using DAC topologies with lower total capacitance under given linearity requirement. A hybrid CAP-MOS DAC is adopted to reduce the total capacitance of the DAC, which consumes lower static current and chip area than the conventional hybrid capacitive-resistive DAC under the same settling requirement. The prototype 10-bit SAR ADC is implemented in a 0.18- $\mu \text{m}$ CMOS technology, showing an SNDR/SFDR of 56.43 dB/71 dB at 90-kHz input, under a 0.6-V power supply, while consuming $1.01~\mu \text{W}$ at 200 kS/s for a figure of merit of 9.32 fJ/conv.-step. The ADC occupies only a small active area of 0.0675 mm2. [ABSTRACT FROM AUTHOR]

Provides a listing of current staff, committee members and society officers. [ABSTRACT FROM AUTHOR]

Presents a listing of the editorial board, board of governors, current staff, committee members, and/or society editors for this issue of the publication. [ABSTRACT FROM AUTHOR]

These instructions give guidelines for preparing papers for this publication. Presents information for authors publishing in this journal. [ABSTRACT FROM PUBLISHER]

These instructions give guidelines for preparing papers for this publication. Presents information for authors publishing in this journal. [ABSTRACT FROM PUBLISHER]

These instructions give guidelines for preparing papers for this publication. Presents information for authors publishing in this journal. [ABSTRACT FROM PUBLISHER]

These instructions give guidelines for preparing papers for this publication. Presents information for authors publishing in this journal. [ABSTRACT FROM AUTHOR]

The article offers informations for the authors about paper submissions to be published periodical including papers should be related electrical and electronics such as Power Systems and Electronic Circuits (POW), length of the manuscripts and guidelines for submission of graphics.

This paper presents an overview of proximity wireless communication (PWC) technologies, their principles, design guidelines and practical applications. In particular, two different applications of PWC are reviewed. One is PWC between stacked chips. Both communication distance and coupler size are several tens of microns. Area and energy efficient design techniques are introduced. Another is PWC between module boards. Both communication distance and coupler size are several millimeters. Energy and area efficient practical designs are introduced for mobile and industrial machinery applications. [ABSTRACT FROM AUTHOR]

In this paper, we propose a scheme to design the reconfigurable filtering power divider with arbitrary operating channels based on external quality factor ($Q_{\mathbf {e}}$) control. By using an input feeding line, ${n}$ resonators, and $m$ output feeding lines, the $n^{\mathbf {th}}$ -order $m$ -way filtering power divider topology can be obtained with a simple configuration. A coupled-line output feeding structure loading with multiple PIN diodes is proposed to adjust the output $Q_{\mathbf {e}}$ values. Design theories for obtaining the desired $Q_{\mathbf {e}}$ values are provided. Then, the filtering power divider can be fully reconfigured in the states with one to $m$ operating channels. Good input matching can be achieved without using an additional reconfigurable impedance matching network in all these states, resulting in a size and loss reduction. For verification, a 2nd-order 4-way reconfigurable filtering power divider is designed, fabricated, and measured. As compared to the reported reconfigurable power dividers, the proposed design shows the merits of fully reconfigurable operating channels, favorable filtering responses, low insertion losses, high isolation, and a simple structure. [ABSTRACT FROM AUTHOR]

This paper presents a high-current calibration-free analog-digital hybrid controlled LDO for large-area digital load. The proposed architecture has the advantages of an analog controller (continuous and high DC accuracy) with distributed digital power transistors (flexible and scalable for high current applications). Distinctive from the conventional digital LDOs that directly quantize the output voltage, the proposed LDO utilizes an error amplifier (EA) to pre-amplify the $\text{V}_{\mathrm {OUT}}$ error. Then, a 5-bit time-to-digital converter (TDC) quantizes the processed analog error signal subsequently transformed into a thermometer code that directly controls the distributed digital power transistors. This design can pull off high DC accuracy even without calibration. Besides, we implement an auxiliary constant current (ACC) circuit to solve reliability issues and to improve the stability under a large voltage dropout. Fabricated in a 28-nm bulk CMOS process with a 1.2-A load capability, the proposed LDO achieves 2- $\mu \text{V}$ /mA load regulation and close to 1.5% output accuracy. By employing a wide bandwidth EA and a fast TDC, the hybrid LDO can obtain a fast transient response. The measured undershoot is 70 mV with a 0.6-A load step within 10-ns edge time, and the output voltage can scale from 0.6 V to 0.9 V within 30 ns. [ABSTRACT FROM AUTHOR]

This paper presents a cycle by cycle Frequency Shift Keying (FSK) demodulator, able to demodulate a FSK signal with 1% frequency modulation index (MI), in a single cycle. Based on the proposed demodulation scheme, a high rate data transmission link can be established through a high-Q inductive coupling link, breaking the basic tradeoff between the power transfer efficiency (PTE) and data rate in single carrier wireless power and data transfer systems. Designed and simulated with $0.18\mu m$ CMOS process, the proposed FSK demodulator, detects successfully a 5Mbps data with a carrier frequency of 5MHz. A test chip is fabricated in 180nm CMOS technology. Measurement results shows that the demodulator is able to demodulate the cycle-by-cycle modulated FSK signals with low modulation index of 2.5%, with a BER of $1.24\times 10^{-5}$. [ABSTRACT FROM AUTHOR]

Phase locked loops for fractional frequency synthesis typically use Digital $\Delta \Sigma $ Modulators (DDSMs) as their divider controllers. Different types and configurations of DDSMs have been presented in the past which have distinctive characteristics in terms of spectral shaping of their quantization errors, spur immunity and implementation costs. This paper presents a family of DDSMs that have provably high spur immunity and low folded noise when used in fractional- ${N}$ frequency synthesizers with polynomial nonlinearities. [ABSTRACT FROM AUTHOR]

Most memristor-based associative memory neural networks are focused on classical conditioning and ignored operant conditioning. In this paper, a memristor-based neural network of operant conditioning accorded with biological feature is designed. The designed circuit includes a voltage control module, an operant module and synapse modules. It realizes learning, forgetting, long-term memory, reinforcement and punishment functions based on variable synapse structure and double self-protection measure. Meanwhile, the four factors that affect operant conditioning such as contingency, immediacy, magnitude and deprivation are discussed and implemented. The simulation results in PSPICE show that the circuit can be used to simulate actual conditioned reflex and complicated applications. The memristor-based neural network circuit of operant conditioning provides more references for further development of neural networks. [ABSTRACT FROM AUTHOR]

The integral nonlinearity of digital-to-analog converters manifests itself as adjacent-channel power in RF transmitters. This paper derives compact equations relating these two quantities and verifies the results by simulations. Both current-steering and switched-mode architectures are analyzed. [ABSTRACT FROM AUTHOR]

In the context of global integration, the theory of financial complex networks has made significant contributions to the establishment of stable financial systems and effective regulatory systems. This survey paper presents a systematic methodology for the multi-layer financial complex networks and their applications. Several typical financial networks in existing research are first summarized: the interbank network, the credit network, the international trade network, and the dealer network. The main methods used in the existing literature to analyze the structure of financial networks include maximum entropy methods, network characterization, community detection, and dynamic multi-layer network. Financial risk contagion as well as spillover effects are the core issues that most of the literature focuses on. Finally, this paper reviews the shortcomings of the existing literature and suggests future research directions in this area. [ABSTRACT FROM AUTHOR]

This paper focuses on speeding up NTRU - one of the lattice-based finalists of the NIST PQC competition - by improving the ring multiplication. The Number Theoretic Transform (NTT), Toom-Cook, and Karatsuba are the most commonly used algorithms for implementing NTRU. In this paper, we propose Toeplitz matrix-vector product (TMVP) based algorithms for multiplication for all parameter sets of NTRU. We implement the proposed algorithms on ARM Cortex-M4. The results show that the TMVP-based multiplication algorithms we propose are more efficient than the others in the literature in most cases. Our algorithm for ntruhps2048509 outperform the Toom-Cook and NTT methods in the literature by 25.4% and 21.5%. We also observe the impact of these improvements on the overall performance of NTRU. We speed up the key generation, encryption, decryption, encapsulation, and decapsulation algorithms of ntruhps2048509 by 12.5%, 14.3%, 17.7%, 3.9%, and 14.7%, respectively, compared to state-of-the-art implementation. Moreover, our algorithms require less stack space than the others. [ABSTRACT FROM AUTHOR]

This paper is concerned with the secure estimation problem for the state of charge of Lithium-ion batteries subject to malicious attacks during the data transmission from sensors to cloud-based battery management system terminal. First, the second-order resistance-capacitance equivalent circuit model, whose parameters are identified by Kalman filter in an off-line manner, is introduced to describe the internal dynamics of lithium-ion batteries. Then, by applying the $\chi ^{2}$ detection mechanism, real-time malicious attacks are first detected and then a secure estimator is designed to suppress the influence of attacks on the estimation performance. An upper bound of the filtering error covariance is determined by solving certain coupled Riccati-like equations, and the filter parameter is obtained by minimizing such an upper bound at each time step. Finally, the validity of the proposed attack detection approach and the effectiveness of the developed estimation scheme are verified by experiment results under Federal Urban Driving Schedule condition. [ABSTRACT FROM AUTHOR]

This paper presents a 1.5-GS/s 6-bit single-channel loop-unrolled successive approximation register (SAR) analog-to-digital converter (ADC) using speculative capacitive DAC (CDAC) switching control technique. The proposed SAR ADC achieves a high sampling rate by eliminating additional delays in typical loop-unrolled SAR ADCs related to settling time constraints in their CDACs. Specifically, the CDACs are duplicated and controlled in speculative ways so that the CDAC outputs passage to their next values before completing the regeneration operation of comparators, thereby improving timing constraints for successive approximations. The switching power overhead from the CDAC speculation is mitigated by introducing an energy-efficient CDAC control technique that produces desired voltage transients with minimal power overheads. The prototype of the proposed SAR ADC is fabricated in a 28-nm CMOS technology and occupies an active area of 0.0038-mm2. The design consumes 5.8 mW from a 1.2-V supply. The ADC achieves 1.5-GS/s sampling frequency with a 31-dB SNDR at a low input frequency and a 28.6 dB at the Nyquist frequency without applying any offset calibration techniques, achieving the highest sampling frequency among the 6-bit single-channel loop-unrolled SAR ADCs reported. [ABSTRACT FROM AUTHOR]

This paper analyzes the ability to suppress in-band noise power of a regenerative amplifier (RA) operating in the nonlinear regime in response to a continuous wave (CW) input tone. As opposed to the linear regime where a CW tone and the noise floor experience the same transfer function, it is shown that the non-linear saturation behavior of an RA yields different transfer characteristics between a CW tone and noise, ultimately leading to an improvement in the output carrier-to-noise ratio (CNR). This is all thanks to the high gain, narrow bandwidth, and the compressive third-order nonlinearity of the RA. This non-linear noise suppression is first analyzed mathematically using single tones in the frequency domain to represent the signal and the noise. Then, simulation of an RA circuit model is shown to be in excellent agreement with the analytical results. Lastly, a discrete RA has been implemented to experimentally verify the noise-suppression phenomenon. The measurement results clearly demonstrate noise suppression and show an output CNR improvement of up to 3 dB. Potential applications of the RA with noise suppression are also discussed. [ABSTRACT FROM AUTHOR]

In recent years, fast computation, low power, and small footprint are the key motivations for building SNN hardware. The unique features of SNN hardware have not been fully exploited, where the computation speed and energy efficiency of the SNN hardware can be improved according to the sparse spiking and non-uniform traffic of SNN. In this paper, we propose a 5.28-mm $^{2}~4096$ -neuron 1M-synapse energy-efficient digital SNN hardware that can achieve ultra-low energy per synaptic operation of 4.5 pJ. The proposed neuron computing unit is implemented in pipeline architecture to achieve high synaptic processing speed. The proposed spike processing unit can significantly increase the processing speed of the neuron core by $1.9\times $ and $9.4\times $ when the spike injection rate is 50% and 10%, respectively. Besides, the increase in the processing speed of the neuron core leads to a reduction in energy consumption of up to 81.5%. An event-driven clock gating circuit that can reduce the power consumption of the proposed neuron block by more than 70% is proposed in this paper. This paper proposes a supervised STDP+ algorithm for SNN training, and the classification accuracy of the MNIST digits is 89.6% with 73.6% weight sparsity of the output layer. [ABSTRACT FROM AUTHOR]

The Internet of Things (IoT) is an interface with the physical world that usually operates in random-sparse-event (RSE) scenarios. This article discusses main challenges of IoT chips: power consumption, power supply, artificial intelligence (AI), small-signal acquisition, and evaluation criteria. To overcome these challenges, many works recently aimed at IoT system design have emerged. This work reviews the architecture and circuit innovations that have contributed to IoT developments. This paper does not cover security of IoT. Event-driven architectures and nonuniform sampling ADCs significantly reduce the long-term average power. Besides, embedding AI engines in IoT nodes (AIoT) is one critical trend. The computing-in-memory technique improves the energy efficiency of the AI engine. Asynchronous spike neural networks (ASNNs) AI engines show low power potential. In addition to data processing, small-signal acquisition is also critical. The charge-domain analog-front-end (AFE) techniques such as floating inverter-based amplifiers improve energy efficiency. In addition to the above low power and high energy efficiency technologies, energy harvesting can also enhance the lifetime of AIoT devices. This article discusses recent ambient RF and natural energy harvesting approaches and high-efficiency DC-DC with a wide load range. Finally, novel evaluation criteria are introduced to establish benchmark standards for AIoT chips. [ABSTRACT FROM AUTHOR]

Inhomogeneous linear ordinary differential equations (ODEs) and systems of ODEs can be solved in a variety of ways. However, hardware circuits that can perform the efficient analog computation to solve them are rarely in the literature. To address such problems, this paper proposes a general method of using a memristor-capacitor (M-C) circuit to solve inhomogeneous linear ODEs and systems of ODEs of any order in initial value problems. The M-C circuit can match the coefficients of the equations sought by adjusting the memristor resistance value according to the coefficient formula proposed in the paper, which has higher programmability. Then, some ODEs and systems of ODEs are given in the paper as examples to evaluate the proposed method. According to the comparison results based on MATLAB software simulation and the simulation based on OrCAD software, the designed M-C circuit has an effective improvement in speed and the accuracy exceeds 99.95% in software simulation. Based on practical verification, this paper gives the actual M-C circuit experiment based on PCB. Moreover, the proposed method can be used to quickly solve the object motion state in the spring mass damping system in actual engineering, and the accuracy can reach 99.98%. [ABSTRACT FROM AUTHOR]