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In this paper, we present new feedforward FFT hardware architectures based on rotator allocation. The rotator allocation approach consists in distributing the rotations of the FFT in such a way that the number of edges in the FFT that need rotators and the complexity of the rotators are reduced. Radix-2 and radix-2k feedforward architectures based on rotator allocation are presented in this paper. Experimental results show that the proposed architectures reduce the hardware cost significantly with respect to previous FFT architectures. [ABSTRACT FROM PUBLISHER]

This paper presents a COordinate Rotation Digital Computer (CORDIC)-based architecture for the computation of Nth root and proves its feasibility by hardware implementation. The proposed architecture performs the task of Nth root simply by shift-add operations and enables easy tradeoff between the speed (or precision) and the area. Technically, we divide the Nth root computation into three different subtasks, and map them onto three different classes of the CORDIC accordingly. To overcome the drawback of narrow convergence range of the CORDIC algorithm, we adopt several innovative methods to yield a much improved convergence range. Subsequently, in terms of convergence range and precision, a flexible architecture is developed. The architecture is validated using MATLAB with extensive vector matching. Finally, using a pipelined structure with fixed-point input data, we implement the example circuits of the proposed architecture with radicand ranging from zero to one million, and achieve an average mean of approximately 10−7 for the relative error. The design is modeled using Verilog HDL and synthesized under the TSMC 40-nm CMOS technology. The report shows a maximum frequency of 2.083 GHz with $197421.00~{\mu }\text{m}^{2}$ area. The area decreases to $169689.98~{\mu }\text{m}^{2}$ when the frequency lowers to 1.00 GHz. [ABSTRACT FROM AUTHOR]

This paper is concerned with the problem of event-triggered optimized control for uncertain nonlinear Itô-type stochastic systems with time-delay and unknown dynamic. By using fuzzy logic systems to approximate two unknown nonlinear functions with the delayed state and current state, respectively. The adaptive identifier is constructed to determine the stochastic system, and the optimized control is designed by using the identifier and adaptive dynamic programming (ADP) of actor-critic architecture. Almost all of the works are concentrated on ADP-based optimal control and it will inevitably cause the complexity of computation and requirements of persistence excitation (PE) assumption. In this paper, the ADP algorithm is obtained based on the negative gradient of a simple positive function (equivalent to the HJB equation), and so the proposed optimal control is simple and can release the PE assumption. Moreover, the event-triggered control approach is proposed to reduce computing burden and communication resources. Furthermore, we prove that the states of system and FLSs parameter errors are semi-globally uniformly ultimately bounded (SGUUB) in mean square via the adaptive identifier and the Lyapunov direct method as well as identifier-actor-critic architecture-based ADP algorithm. Finally, the effectiveness of the proposed method is illustrated through two numerical examples. [ABSTRACT FROM AUTHOR]

Coordinate Rotation Digital Computer (CORDIC) is a robust iterative algorithm that computes many transcendental mathematical functions. This paper proposes a reconfigurable CORDIC hardware design and FPGA realization that includes all possible configurations of the CORDIC algorithm. The proposed architecture is introduced in two approaches: multiplier-less and single multiplier approaches, each with its advantages. Compared to recent related works, the proposed implementation overpasses them in the included number of configurations. Additionally, it demonstrates efficient hardware utilization and suitability for potential applications. Furthermore, the proposed design is applied to a memristive chaotic system with different transcendental functions computed using the proposed reconfigurable block. The memristive system design is realized on the Artix-7 FPGA board, yielding throughputs of 0.4483 and 0.3972 Gbit/s for the two approaches of reconfigurable CORDIC. [ABSTRACT FROM AUTHOR]

This paper presents an extensive study of linear and logistic regression algorithms implemented with 1T1R memristor crossbars arrays. Using a sophisticated simulation platform that wraps circuit-level simulations of 1T1R crossbars and physics-based models of RRAM (memristors), we elucidate the impact of device variability on algorithm accuracy, convergence rate and precision. Moreover, a smart pulsing strategy is proposed for practical implementation of synaptic weight updates that can accelerate training in real crossbar architectures. Stochastic multi-variable linear regression shows robustness to memristor variability in terms of prediction accuracy but reveals impact on convergence rate and precision. Similarly, the stochastic logistic regression crossbar implementation reveals immunity to memristor variability as determined by negligible effects on image classification accuracy but indicates an impact on training performance manifested as reduced convergence rate and degraded precision. [ABSTRACT FROM AUTHOR]

Conventional design and optimization of passive compensation network (PCN) for inductive power transfer (IPT) system are based on specific topologies. The demerits of this design method are: i) The topology is mostly chosen by experience; ii) The design parameters are not multi-objective optimal. Aiming at these issues, this paper proposes an optimal PCN design scheme based on evolutionary algorithm (EA) to synchronously optimize the topology and parameters of PCN for IPT system. Firstly, a unified mathematical model of the PCN is presented and derived by transmission matrix. Then, according to the mathematical model, the multi-objective functions (such as output fluctuation and efficiency) as well as the constraints (such as load and coupling coefficient) for the optimal PCN design are established. The EA based multi-objective optimal PCN design algorithm is further constructed. Six optimal results are obtained using the algorithm, and one optimized PCN having minimum output current fluctuation and high-efficiency is chosen to validate the effectiveness of the proposed design scheme in experiment. For the given IPT system with the optimized PCN, the maximum fluctuation of output current is no more than 11%, within 200% of load variation and about 77% of coupling variation. [ABSTRACT FROM AUTHOR]

Since chaotic cryptography has a long-term problem of dynamic degradation, this paper presents proof that chaotic systems resist dynamic degradation through theoretical analysis. Based on this proof, a novel one-dimensional two-parameter with a wide-range system mixed coupled map lattice model (TWMCML) is given. The evaluation of TWMCML shows that the system has the characteristics of strong chaos, high sensitivity, broader parameter ranges and wider chaos range, which helps to enhance the security of chaotic sequences. Based on the excellent performance of TWMCML, it is applied to the newly proposed encryption algorithm. The algorithm realizes double protection of private images under the premise of ensuring efficiency and safety. First, the important information of the image is extracted by edge detection technology. Then the important area is scrambled by the three-dimensional bit-level coupled XOR method. Finally, the global image is more fully confused by the dynamic index diffusion formula. The simulation experiment verified the effectiveness of the algorithm for grayscale and color images. Security tests show that the application of TWMCML makes the encryption algorithm have a better ability to overcome conventional attacks. [ABSTRACT FROM AUTHOR]

In this paper, fast and compact implementations for code-based signature are presented. Existing designs are either using enormous memory storage or suffering from slow issuing speed of signatures. A vastly optimized new design solving these problems is proposed by exploiting quasi-cyclic low-density generator matrix codes at different levels. In particular, this paper provides a new algorithmic enhancement of signature generation and gives detailed and optimized solutions for critical steps of this algorithm. The design presented in this paper is the fastest implementation of code-based signatures in open literature. It is shown, for instance, that our implementation of signature generation engine can generate approximately 60 000 signatures per second on a Xilinx Virtex-6 FPGA, requiring only 5992 slices and 60 memory blocks. In addition, a very compact implementation is also provided, producing 5438 signatures per second with only 18 memory blocks. [ABSTRACT FROM PUBLISHER]

In this paper, a unified framework is proposed to address the synchronization problem of memristor chaotic systems (MCSs) via the sliding-mode control method. By employing the presented unified framework, the finite-time and fixed-time synchronization of MCSs can be realized simultaneously. On the one hand, based on the Lyapunov stability and sliding-mode control theories, the finite-/fixed-time synchronization results are obtained. It is proved that the trajectories of error states come near and get to the designed sliding-mode surface, stay on it accordingly and approach the origin in a finite/fixed time. On the other hand, we develop an image encryption algorithm as well as its implementation process to show the application of the synchronization. Finally, the theoretical results and the corresponding image encryption application are carried out by numerical simulations and statistical performances. [ABSTRACT FROM AUTHOR]

Memristor-based memory technology is one of the emerging memory technologies, which is a potential candidate to replace traditional memories. Efficient test solutions are required to enable the quality and reliability of such products. In previous works, fault models are caused by open, short and bridge defects and parametric variations during the fabrication. However, these fault models cannot describe the bridge defects that cause the state of the faulty cell to an undefined state. In this paper, we analyze the different effects of bridge defects and aggregate their faulty behavior into new fault models, undefined coupling fault and dynamic undefined coupling fault. In addition, an enhanced March algorithm is designed to detect all the modeled faults. In one resistor crossbar with $N$ memristors, the enhanced March algorithm requires $8N$ write and $7N$ read operations with negligible hardware overhead. To reduce the test time, a March RC algorithm is proposed based on read operations with new reference currents, which requires $4N+2$ write and $6N$ read operations. Analytical results show that the proposed test algorithms can detect all the modeled faults outperforming all the previous methods. Subsequently, a Design-for-Testability scheme is proposed to implement March RC algorithm with a little area overhead. [ABSTRACT FROM AUTHOR]

This paper proposes a new optimization framework for the joint optimization of sparsity and filter order (JOSFO) for FIR filter design. Since the cost function for JOSFO involves \ell 0 and non-uniform overlapped group \ell 0 norms, which are not convex, a global optimal solution is difficult to obtain. To find an approximate solution of the non-convex problem, existing approaches repeat the following steps: 1) approximate the cost function; 2) find candidates of zero coefficients by minimizing the cost function; and 3) set them to zero. On the other hand, this paper directly solves the optimization problem, without any approximation to the cost function, by using the alternating direction method of multipliers with the pseudo-proximity operators of \ell 0 and non-uniform non-overlapped group \ell 0 norms. Experimental results show that resulting filters designed by the proposed method have sparser coefficients and lower orders, while satisfying filter specifications, such as an error from a desired frequency response. [ABSTRACT FROM PUBLISHER]

Deep Neural Networks (DNNs) are increasingly being used in a variety of applications. However, DNNs have huge computational and memory requirements. One way to reduce these requirements is to sparsify DNNs by using smoothed LASSO (Least Absolute Shrinkage and Selection Operator) functions. In this paper, we show that irrespective of error profile, the sparsity values obtained using various smoothed LASSO functions are similar, provided the maximum error of these functions with respect to the LASSO function is the same. We also propose a layer-wise DNN pruning algorithm, where the layers are pruned based on their individual allocated accuracy loss budget, determined by estimates of the reduction in number of multiply-accumulate operations (in convolutional layers) and weights (in fully connected layers). Further, the structured LASSO variants in both convolutional and fully connected layers are explored within the smoothed LASSO framework and the tradeoffs involved are discussed. The efficacy of proposed algorithm in enhancing the sparsity within the allowed degradation in DNN accuracy and results obtained on structured LASSO variants are shown on MNIST, SVHN, CIFAR-10, and Imagenette datasets and on larger networks such as ResNet-50 and Mobilenet. [ABSTRACT FROM AUTHOR]

Passively-integrated memristors are the most prospective candidates for designing high-speed, energy-efficient, and compact neuromorphic circuits. Despite all the promising properties, experimental demonstrations of passive memristive crossbars have been limited to circuits with few thousands of devices until now, which stems from the strict uniformity requirements on the IV characteristics of memristors. This paper expands upon this vital challenge and investigates how uniformity impacts the computing accuracy of analog memristive circuits, focusing on neuromorphic applications. Specifically, the paper explores the tradeoffs between computing accuracy, crossbar size, switching threshold variations, and target precision. All-embracing simulations of matrix multipliers and deep neural networks on CIFAR-10 and ImageNet datasets have been carried out to evaluate the role of uniformity on the accuracy of computing systems. Further, we study three post-fabrication methods that increase the accuracy of nonuniform 0T1R neuromorphic circuits: hardware-aware training, improved tuning algorithm, and switching threshold modification. The application of these techniques allows us to implement advanced deep neural networks with almost no accuracy drop, using current state-of-the-art analog 0T1R technology. [ABSTRACT FROM AUTHOR]

This paper aims to refine and expand the theoretical and application framework of higher-dimensional digital chaotic system (HDDCS). Topological mixing for HDDCS is strictly proved theoretically at first. Topological mixing implies Devaney’s definition of chaos in a compact space, but not vice versa. Therefore, the proof of topological mixing promotes the theoretical research of HDDCS. Then, a general design method for constructing HDDCS via loop-state contraction algorithm is given. The construction of the iterative function uncontrolled by random sequences (hereafter called iterative function) is the starting point of this research. On this basis, this paper put forward a general design method to solve the construction problem of HDDCS, and several examples illustrate the effectiveness and feasibility of this method. The adjacency matrix corresponding to the designed HDDCS is used to construct the chaotic Echo State Network (ESN) for predicting Mackey-Glass time series. Compared with other ESNs, the chaotic ESN has better prediction performance and is able to accurately predict a much longer period of time. [ABSTRACT FROM AUTHOR]

Sparse code multiple access (SCMA) is a promising technology for the development of wireless communication, which supports a large number of overloading users and enjoys high spectral efficiency. However, conventional SCMA decoders suffer very high complexity in implementations. Changing the updating scheme is a superior approach to reduce complexity, which guarantees the updated information immediately join in the following message propagating of the current iteration and accelerates the decoding convergence. In this paper, a row-layered message passing algorithm (MPA) is proposed, which offers a good trade-off between the hardware complexity and the bit error rate (BER) performance. Simulation results show that the proposed decoder saves 66.7% computation complexity compared with the original MPA with the similar BER performance. Pipelining and folding technology are adopted in VLSI implementations. The synthesis results with 45-nm CMOS technology show that the proposed decoder can achieve higher hardware efficiency and throughput under a high frequency than the existing decoders, achieving 1777.78 Mb/s throughput with 1.112 mm2 area consumption. [ABSTRACT FROM AUTHOR]

This paper proposes two kinds of algorithms to achieve privacy-preserving consensus of multi-agent systems over undirected graphs via node decomposition mechanism and homomorphic cryptography technique. Based on the number of neighboring nodes (|Ni|), every agent is decomposed into |Ni| subagents, which are connected as a chain graph. Note that every subagent connects one and only one non-homologous subagent (generated by different agents). Information interaction between non-homologous subagents is encrypted by a homomorphic cryptography algorithm, and homologous subagents exchange information directly. In this regard, the proposed node decomposition mechanism enhances the privacy of the initial values without increasing the computational complexity of encryption. The first privacy-preserving algorithm can achieve the accurate average consensus, which means that the agreement value of every subagent is consistent with the original average consensus value. The second algorithm studies the privacy-preserving scaled consensus problem without a priori knowledge about the underlying graph. Although the final convergence values of subagents do not keep exactly the same, homologous subagents can compute the original group decision value by resorting to the product of the limit value and agent’s degree. Importantly, this algorithm also guarantees the privacy of group decision value of the whole system. Besides, it is proved that the privacy of the initial value can be preserved if the agent has at least one neutral neighbor. [ABSTRACT FROM AUTHOR]

This paper focuses on the distributed consensus seeking of multi-agent systems (MASs) with discrete-time control updating and intermittent communications among agents. Compared with existing linearly coupled protocols, a nonlinear coupled Zeno-free event-triggered controller is first proposed, which is further to project the static and dynamic triggering mechanisms exploited by using the deadband control method. Then, the node-based nonlinear coupled adaptive event-triggered controller with online self-tuning of time-varying coupling weight and its corresponding to static and dynamic deadband-based event-triggered mechanisms are designed, respectively. The exploited adaptive event-triggered controller does not rely on any global information of interaction structure and is implemented in a fully distributed fashion. In addition, two dynamic proposals not only cover existing static strategies as special cases, but also show that the minimal inter-execution time of dynamic one is not smaller than that of static one. Theoretical analysis shows that the proposed static and dynamic deadband-based event-triggered mechanisms can not only ensure the average consensus with Zeno-freeness, but also achieve the data reduction of communication and control. Finally, the proposed algorithms applied to circuit implementation are corroborated to prove its practical merits and validity. [ABSTRACT FROM AUTHOR]

Provides instructions and guidelines to prospective authors who wish to submit manuscripts. [ABSTRACT FROM PUBLISHER]

This paper proposes a new fast algorithm for calculating the discrete fractional Hadamard transform for data vectors whose size $N$ is a power of two. A direct method for the calculation of the discrete fractional Hadamard transform requires $O(N^{2})$ multiplications, the last fast algorithm requires $O(N \log _{2}~N)$ , while in the proposed algorithm the number of multiplications is reduced to $O(N)$. [ABSTRACT FROM AUTHOR]

Single constant multiplication (SCM) and multiple constant multiplications (MCM) are among the most popular schemes used for low-complexity shift-add implementation of finite impulse response (FIR) filters. While SCM is used in the direct form realization of FIR filters, MCM is used in the transposed direct form structures. Very often, the hybrid form FIR filters where the sub-sections are implemented by fixed-size MCM blocks provide better area, time, and power efficiency than those of traditional MCM and SCM based implementations. To have an efficient hybrid form filter, in this paper, we have performed a detailed complexity analysis in terms of the hardware and time consumed by the hybrid form structures. We find that the existing hybrid form structures lead to an undesirable increase of complexity in the structural-adder block. Therefore, to have a more efficient implementation, a variable size partitioning approach is proposed in this paper. It is shown that the proposed approach consumes less area and provides nearly 11% reduction of critical path delay, 40% reduction of power consumption, 15% reduction of area-delay product, 52% reduction of energy-delay product, and 42% reduction of power-area product, on an average, over the state-of-the-art methods. [ABSTRACT FROM AUTHOR]

Over the last decades, the cooperative design of complex networked systems has received an increasing attention in real-world engineering practices. Traditionally, each node in the network is assumed to obtain the same signal. However, each agent often possesses different measurement due to the observability or configuration of the systems. To solve the stabilization problem in this case, we aim to establish a unified framework for the cooperative control of complex network with distributed observers. In detail, different from the traditional centralized design, this paper initiates a cooperative approach by only using the local information of the networked systems. In allusion to the three kinds of representative networks, this paper establishes some sufficient or necessary conditions for the existence of network parameters that guarantee the stabilization of the LTI plants. Moreover, some corresponding algorithms are developed to find the suitable parameters of networked observers. Last but not least, numerical simulations are also provided to verify the above theoretical results. [ABSTRACT FROM AUTHOR]

This paper provides a framework of designing distributed model predictive controller to reach consensus of a heterogeneous time-varying multi-agent system, and the dynamics of heterogeneous agents are modeled by double integrators and Euler-Lagrange (EL) equations. Firstly, a DMPC-based consensus algorithm is proposed, where the constraints in the algorithm depend on the heterogeneous dynamics. We prove that the resultant DMPC optimization problem is feasible with the designed controllers, which is stable when the system reaches consensus. To further reduce communication cost and solve the problem with asynchronous discrete-time information exchange, self-triggered mechanism is introduced into the framework. Trigger intervals are alternatively optimized with the control inputs, and the influence on the system performance is analyzed. Numerical examples are provided to verify the effectiveness and advantages of the proposed algorithms. [ABSTRACT FROM AUTHOR]

Due to non-linear factors such as the rate capacity and the recovery effect, the shape of the battery discharge curve plays a significant role in the overall lifetime of the batteries. Accordingly, this paper proposes a simple heuristic battery-aware speed scheduling policy for periodic and non-periodic real-time tasks in Dynamic Voltage Scaling (DVS) systems with non-negligible leakage/static power. A set of comprehensive analysis has been conducted to compare the battery efficiency of the proposed policies with an optimal solution, which could be derived via the Calculus of Variations (CoV). These evaluations have taken into account both periodic and non-periodic tasks in DVS-based systems. Our experiments have shown a maximum of 7% difference between the optimal solution and the simple heuristic speed scheduling for realistic settings of the battery model. By considering the calculated optimal speed scheduling for different tasks (with different utilizations), a two-phase algorithm has been proposed, in which a speed approximation function is being calculated offline based on curve fitting, while the best execution speed is applied online. The results show a maximum of 17.7% and 11.3% battery charge saving for non-periodic and periodic tasks in comparison to the baseline critical frequency method, respectively. [ABSTRACT FROM AUTHOR]

Isogeny-based cryptography is one of the promising post-quantum candidates mainly because of its smaller public key length. Due to its high computational cost, efficient implementations are significantly important. In this paper, we have proposed a high-speed FPGA implementation of the supersingular isogeny Diffie-Hellman (SIDH) and key encapsulation (SIKE). To this end, we have adapted the algorithm of finding optimal large-degree isogeny computation strategy for hardware implementations. Using this algorithm, hardware-suited strategies (HSSs) can be devised. We have also developed a tool to schedule field arithmetic operations efficiently using constraint programming. This tool enables reducing the latency of SIDH and SIKE subroutines by up to 14% at NIST’s highest security level, i.e., using the SIKEp751 parameter set. We have also improved the latency of field inversion, the most costly field operation in SIDH, by 23% using the Montgomery ladder technique. We have provided constant-time implementations of SIDH and SIKE on Virtex-7 using SIKEp751 utilizing 6 and 8 prime field multipliers to resemble the previous work. Experimental results show that using 8 multipliers SIDH and SIKE encapsulation and decapsulation can be performed in 24.66 ms and 24.10 ms, which is 1.37 and 1.12 times faster than the latest corresponding FPGA implementations, respectively. [ABSTRACT FROM AUTHOR]

The paper describes the FPGA implementation of a novel position evaluation algorithm based on the time difference of arrival (TDOA) principle that combines the characteristics of an Orthogonal Frequency Division Modulation (OFDM) symbol with the properties of the Zadoff-Chu mathematical sequences. The resulting system is highly scalable and its characteristics are easily adaptable to different operating scenarios. The algorithm has been implemented using the Stratix IV-E EP4SGX70HF35C3 FPGA, requiring about 112k bit of memory and less than 44k logic elements of which about 16k are registers. The paper describes the algorithm and its FPGA implementation along with experimental results validating the system performance even in the presence of multipath interferences and showing precision in target position estimation that is better than 2 cm. [ABSTRACT FROM AUTHOR]

Convolutional Neural Networks (CNN) are widely used in different artificial intelligence (AI) applications. Major part of the computation of a CNN involves 2D convolution. In this paper, we propose novel fast convolution algorithms for both 1D and 2D to remove the redundant multiplication operations in convolution computations at the cost of controlled increase of addition operations. For example, when the 2D processing block size is $3\times 3$ , our algorithm has multiplication saving factor as high as 3.24, compared to direct 2D convolution computation scheme. The proposed algorithm can also process input feature maps and generate output feature maps with the same flexible block sizes that are independent of convolution weight kernel size. The memory access efficiency is also largely improved by the proposed method. These structures can be applied to different CNN layers, such as convolution with stride > 1, pooling and deconvolution by exploring flexible feature map processing tile sizes. The proposed algorithm is suitable for both software and hardware implementation. [ABSTRACT FROM AUTHOR]

This paper investigates the weighted least squares (WLS) and minimax design problems for variable fractional delay (VFD) FIR filters. For the WLS design, the general case of incorporating arbitrary nonnegative weighting functions is considered. The optimal solution is characterized by two matrix equations. An efficient algorithm using conjugate gradient (CG) techniques is proposed to solve the WLS solution. The proposed algorithm is guaranteed to converge to the optimal solution in a finite number of iterations. Moreover, an iterative reweighted least squares (IRLS) algorithm that uses the proposed CG algorithm as its iteration core is developed for the minimax design problem. In both of the algorithms, the filter coefficients are arranged as matrices, achieving a great saving in computations and memory space. The associated computational complexity is analyzed. Some design examples are provided and comparisons with existing methods show that the proposed ones are either computationally more efficient or can obtain the better filter performance, or both. [ABSTRACT FROM AUTHOR]

The compressive sensing (CS) based sparse vector coding (SVC) method is one of the promising ways for the next-generation ultra-reliable and low-latency communications. In this paper, we present advanced algorithm-hardware co-optimization schemes for realizing a cost-effective SVC decoding architecture. The previous maximum a posteriori subspace pursuit (MAP-SP) algorithm is newly modified to relax the computational overheads by applying novel residual forwarding and LLR approximation schemes. A fully-pipelined parallel hardware is also developed to support the modified decoding algorithm, reducing the overall processing latency, especially at the support identification step. In addition, an advanced least-square-problem solver is presented by utilizing the parallel Cholesky decomposer design, further reducing the decoding latency with parallel updates of support values. The implementation results from a 22nm FinFET technology showed that the fully-optimized design is 9.6 times faster while improving the area efficiency by 12 times compared to the baseline realization. [ABSTRACT FROM AUTHOR]

Given a set of numbers X, finding the minimum value of X, min•1;st, is a very easy task. However, efficiently finding its second minimum value, min•2nd, requires the derivations of min•1st and finding the minimum value from the set of the remaining numbers. Efficient algorithms and cost-effective hardware of finding the two smallest of X are greatly needed for the low-density parity-check (LDPC) decoder design. The following two architectures are developed in this paper: 1) sorting-based (XS) approach and 2) tree structure (TS) approach. Experimental results show that the XS approach provides less number of comparisons, while the TS approach achieves higher speed performance at lower hardware cost. Since the hardware unit is repeatedly used in the LDPC decoder design, the proposed high-speed low-cost TS approach is strongly recommended. [ABSTRACT FROM AUTHOR]

This paper investigates the problem of factor prime factorizations for n-D polynomial matrices and presents a criterion for the existence of factor prime factorizations for an important class of n-D polynomial matrices. As a by-product, we also obtain an algebraic algorithm to check n-D factor primeness in some important cases which partially solves the long-standing open problem of recognizing n-D factor prime matrices. Some problems related to the factorization methods are also studied. Several exam- pies are given to illustrate the results. The results presented in this paper are true over any coefficient field. [ABSTRACT FROM AUTHOR]

Identifying and removing undesired operating points is one of the most important problems in analog circuit design. In this paper, a divide and contraction verification method against undesired operating points in analog circuits is proposed. Unlike traditional methods to find all operating points, this method only targets searching voltage intervals containing undesired operating points. To achieve this, a systematic approach for automatically identifying all positive and negative feedback loops in circuits is introduced. A positive feedback loop breaking method and selection of breaking nodes are discussed to determine whether a monotonic return function can be obtained. Depending on the monotonicity of the return function, two types of divide and contraction algorithms are proposed to efficiently search voltage intervals containing operating points. Simulation results show that this method is effective and efficient in identifying the presence/absence of undesired operating points in a set of commonly used benchmark circuits. [ABSTRACT FROM PUBLISHER]

Automatic synthesis of digital circuits has played a key role in obtaining high-performance designs. While considerable work has been done in the past, emerging device technologies call for a need to re-examine the synthesis approaches, so that better circuits that harness the true power of these technologies can be developed. This paper presents a methodology for synthesis applicable to devices that support ternary logic. We present an algorithm for synthesis that combines a geometrical representation with unary operators of multivalued logic. The geometric representation facilitates scanning appropriately to obtain simple sum-of-products expressions in terms of unary operators. An implementation based on Python is described. The power of the approach lies in its applicability to a wide variety of circuits. The proposed approach leads to the savings of 26% and 22% in transistor-count, respectively, for a ternary full-adder and a ternary content-addressable memory (TCAM) over the best existing designs. Furthermore, the proposed approach requires, on an average, less than 10% of the number of the transistors in comparison with a recent decoder-based design for various ternary benchmark circuits. Extensive HSPICE simulation results show roughly 92% reduction in power-delay product (PDP) for a $12\times 12$ TCAM and 60% reduction in PDP for a 24-ternary digit barrel shifter over recent designs. [ABSTRACT FROM PUBLISHER]

This paper addresses the finite-time and fixed-time bipartite average tracking (BAT) problems in multi-agent systems (MASs) subject to bounded disturbances. A novel non-smooth protocol is first constructed on the basis of utilizing the finite-time control method, which can realize the finite-time BAT with structurally balanced graph. Then, the fixed-time BAT problem is dealt with nonlinear fixed-time algorithm, the setting time of which is obtained without depending on initial states. By employing Lyapunov stability theory, some sufficient criteria are obtained to achieve the finite-time and fixed-time BAT for MASs with disturbances. Numerical examples are finally developed for illustration. [ABSTRACT FROM AUTHOR]

This paper presents a novel hardware architecture of the Tensorial Support Vector Machine (TSVM) based on Shallow Neural Networks (NN) for the Single Value Decomposition (SVD) computation. The proposed NN achieves a comparable Mean Squared Error and Cosine Similarity to the widely used one-sided Jacobi algorithm. When implemented on an FPGA, the NN offers $324\times $ faster computations than the one-sided Jacobi with reductions up to 58% and 67% in terms of hardware resources and power consumption respectively. When validated on a touch modality classification problem, the NN-based TSVM implementation has achieved a real-time operation while consuming about 88% less energy per classification than the Jacobi-based TSVM with an accuracy loss of at most 3%. Such results offer the ability to deploy intelligence on resource-limited platform for energy-constrained applications. [ABSTRACT FROM AUTHOR]

Piecewise affine (PWA) systems are attractive models that can represent various hybrid systems with local affine subsystems and polyhedral regions due to their universal approximation properties. The identification problem of PWA systems amounts to estimating the number of subsystems, parameters of each subsystem, and the corresponding polyhedral partitions via state-input vectors. In this paper, we propose a novel approach to address the online identification problem of continuous-time PWA systems in state-space form. Specifically, an online active mode recognition algorithm and a generalized integral concurrent learning identifier are presented to acquire the number of subsystems, the switching sequence, and the parameter of each subsystem. In addition, we develop the optimization problem for the polyhedral partition estimation, which is solved by using the estimated switching sequence and subsystem parameters. The effectiveness of the proposed identification approach is demonstrated via simulation results. [ABSTRACT FROM AUTHOR]

The supersingular isogeny key encapsulation (SIKE) protocol, as one of the post-quantum protocol candidates, is widely regarded as the best alternative for curve-based cryptography. However, the long latency, caused by the serial large-degree isogeny computation which is dominated by modular multiplications, has made it less competitive than most popular post-quantum candidates. In this paper, we propose a high-speed and low-latency architecture for our recently presented optimized SIKE algorithm. Firstly, we design a new field arithmetic logic unit (FALU) with many algorithmic transformations and architectural optimizations. Especially, for the FALU, an extremely low-latency modular multiplier is devised based on a modified algorithm by fully parallelizing and highly optimizing the small-size multipliers and the reduction submodules. Secondly, we develop a compact control logic and update the instructions based on the benchmark provided in the newest SIKE library, fitting well with our design. Thirdly, an efficient memory access method is proposed by scheduling the input and output of the arithmetic logic unit (ALU) in two identical RAMs, which can significantly reduce the latency. Finally, we code the proposed architectures using the Verilog language and integrate them into the SIKE library. The implementation results on a Xilinx Virtex-7 FPGA show that for SIKEp751, our design only costs 9.3 ms with a frequency of 155.8 MHz, about 2× faster than the state-of-the-art, and achieves the best area efficiency among existing works. Particularly, the modular multiplier merely needs 16 clock cycles, reducing the delay by nearly one order of magnitude with a small factor of increase in hardware resource. [ABSTRACT FROM AUTHOR]

This paper is concerned with the almost sure exponential synchronization of a multilayer network which is set up on a non-strongly connected digraph that can be classified into several layers by Tarjan’s algorithm. Note that, in the multilayer network, white-noise-based time-varying coupling and drift term coupling are proposed to simulate two kinds of coexisting distinguishable interactions between vertices. We develop a normal analytical framework for studying synchronization of the multilayer network. Firstly, via aperiodically intermittent pinning noises, synchronization of vertices situated on the first layer is achieved in the layered network. Secondly, under the impact of the white-noise-based time-varying coupling in diffusion term, synchronization of the vertices located in other layer networks is developed with the support of synchronization for the pinned vertices. Employing Lyapunov method, graph theory and stochastic analysis technique, a criterion of almost sure global exponential synchronization is obtained. By adopting the concepts of average noise control rate and average noise control period proposed recently, we lessen the conservativeness of the conditions restricted on aperiodically intermittent noise control to optimize our results. Furthermore, an application to a class of Chua’s circuits is exhibited in detail. In the end, we provide a numerical example to verify the validity of the theoretical results. [ABSTRACT FROM AUTHOR]

As convolutional neural networks (CNNs) become more and more diverse and complicated, acceleration of CNNs increasingly encounters a bottleneck of balancing performance, energy efficiency, and flexibility in a unified architecture. This paper proposed a Winograd-based highly efficient and dynamically Reconfigurable Accelerator (named WRA) for quickly evolving CNN models. A cost-effective convolution decomposition method (CDW) was proposed, and it extends the application of the fast Winograd algorithm. Based on CDW, a high-throughput and reconfigurable processing element (PE) array was designed to exploit the parallelism of Winograd. Besides, a highly compact memory structure employed four levels of data reuse schemes to achieve maximal data reuse and minimize external bandwidth requirement. Provided with dynamically reconfigurable capability, WRA implements CDW and other convolutions (e.g., standard convolution, depthwise separable convolution, and group convolution) on a unified hardware architecture. The WRA accelerator was implemented on a Xilinx XCVU9P platform running at 330 MHz clock frequency, controlled by a POWER8 processor via a coherent accelerator processor interface (CAPI) interface. At different configurations, WRA can provide 2.2–6.3 TOPS performance for different convolution shapes. The average performance and energy efficiency for VGG16/AlexNet/MobileNetV1/MobileNetV2 are 5288 GOP/s at 151.2 GOPs/W, 3478 GOP/s at 99.4 GOPs/W, 2674 GOP/s at 76.4 GOPs/W, and 2194 GOP/s at 62.7 GOPs/W. It achieves $1.7\times $ – $24\times $ speedup compared with the previous FPGA-based designs. [ABSTRACT FROM AUTHOR]

This paper presents a generic foreground calibration algorithm that estimates and corrects memoryless nonlinear impairments in both single channel and time-interleaved analog-to-digital converters (TIADCs), and which is capable of correcting for amplifier nonlinearity, comparator offsets, and capacitance mismatch for each channel. It operates by generating, and then using, a look-up table which maps raw ADC output decision vectors to linearized output. For TIADCs, the algorithm also uses information gained during the calibration phase to estimate timing and gain mismatches among the sub-ADCs. The problem of selecting an appropriate timing reference so as to relax the requirements on the time-skew correction circuitry is statistically analyzed, as is the corresponding impact on manufacturing yield. Accordingly, a new method is proposed having superior performance; for example, in the case of an eight sub-ADC TIADC system, the proposed scheme reduces the time skew correction requirement by 44% compared with conventional methods. The architecture is instrumented with some additional circuitry to facilitate built-in self-test, allowing manufacturing test time and cost reductions. Implementation aspects are discussed, and several complexity reduction techniques are presented along with synthesis results from a Verilog implementation of the calibration engine. [ABSTRACT FROM AUTHOR]

Data-intensive applications such as image processing suffer from massive data movement between memory and processing units. The severe limitations on system performance and energy efficiency imposed by this data movement are further exacerbated with any increase in the distance the data must travel. This data transfer and its associated obstacles could be eliminated by the use of emerging non-volatile resistive memory technologies (memristors) that make it possible to both store and process data within the same memory cells. In this paper, we propose four in-memory algorithms for efficient execution of fixed point multiplication using MAGIC gates. These algorithms achieve much better latency and throughput than a previous work and significantly reduce the area cost. They can thus be feasibly implemented inside the size-limited memory arrays. We use these fixed point multiplication algorithms to efficiently perform more complex in-memory operations such as image convolution and further show how to partition large images to multiple memory arrays so as to maximize the parallelism. All the proposed algorithms are evaluated and verified using a cycle-accurate and functional simulator. Our algorithms provide on average $200\times $ better performance over state-of-the-art APIM, a processing in-memory architecture for data intensive applications. [ABSTRACT FROM AUTHOR]

In this paper, we formulate and prove new results in the context of storage functions for lossless systems: we use these results to propose new algorithms to compute the storage function. The computation of the storage function for the lossless case is not possible using conventional algebraic Riccati equation-based algorithms, though the storage function itself is well-defined. This is because a certain “regularity condition” on the feedthrough term in the i/s/o representation of the lossless system does not hold. We formulate new results about the storage function matrix for the lossless case and use them to propose non-iterative and stable algorithms to compute the storage function directly from different representations of the given system, namely, a kernel representation, transfer function, and the i/s/o representation of the system. Across the methods, for randomly generated transfer functions, we compare: 1) the computational effort (in flops); 2) the computation time using numerical experiments; and 3) the computational error. [ABSTRACT FROM AUTHOR]

In a recently published paper, an estimation algorithm of carrier frequency offset (CFO) with I/Q mismatch was proposed. Errors in the derivation of the algorithm show that its precision can only be asserted in the case of relatively small I/Q mismatch. Averaging the intermediate variables among one short preamble period improves the estimation accuracy under conditions where I/Q mismatch is large. [ABSTRACT FROM PUBLISHER]

A disturbance observer-based control (DOBC) approach is proposed in this paper for control design and qualitative robustness analysis of PWM-based DC-DC buck power converters. A disturbance compensation gain is constructed for the composite control algorithm to cancel the unmatched uncertainties in the output voltage channel. Rigorous criterion is provided to show the quantitative robustness between controller parameters and circuit uncertainties. The DOBC approach delivers not only a promising disturbance rejection performance but also a superior property of tracking performance recovery. The feasibility and efficiency of the proposed approach is validated by experimental results based on LabVIEW real-time control test setup. [ABSTRACT FROM AUTHOR]

This paper proposes a high-performance bidirectional architecture for the quasi-comparison-free sorting algorithm. Our architecture improves the performance of the conventional unidirectional architecture by reducing the total number of sorting cycles via bidirectional sorting along with two auxiliary methods. Bidirectional sorting allows the sorting tasks to be conducted concurrently in the high- and low-index parts of our architecture. The first auxiliary method is boundary finding, which shortens the range for index searching by finding the boundaries of the range. The second auxiliary method is queue storing, which stores each useful index in a queue in advance to reduce the number of miss cycles during index searching. The performance of our architecture highly depends on the distribution of input data. For each set of input data to be sorted, five Gaussian distributions of the input data and four standard derivations for each distribution were adopted in our experiments. The results show that at the expense of some additional area cost, the number of sorting cycles and the energy consumption are significantly reduced by our method. [ABSTRACT FROM AUTHOR]

Existing algorithms for computing the nth-order frequency response functions of the Duffing oscillator have helped promote frequency domain analysis of nonlinear systems but still have a number of practical difficulties. A very efficient algorithm to enable the nth-order symmetric generalized frequency response functions (GFRFs) to be written down directly in terms of the coefficients of the generalized higher order Duffing oscillator model is developed in this paper. The analytical expression derived in this paper shows that the key procedure in the determination of the higher order GFRFs is the computation of the Stirling set of the second kind. This enables the structure of the higher order GFRFs to be seen more clearly. [ABSTRACT FROM AUTHOR]

This paper presents novel design procedures for class E switching circuits allowing implicit circuit equations. Because of the allowance, circuit simulators can be used in the proposed design procedures. Moreover, the proposed design procedures also allow any conditions considered until now. The proposed design algorithms are implemented by using PSpice and OPTIMUS. This paper shows the design examples of two kinds of class E switching circuits. In particular, the design example of the class E oscillator shows the benefit of the proposed design procedure eminently, i.e., it is unnecessary to make an equivalent model of the semiconductor devices for the design. These design examples show the validity and effectiveness of the proposed design procedures. [ABSTRACT FROM AUTHOR]

Reducing address arithmetic operations by optimization of address offset assignment greatly improves the performance of digital signal processor (DSP) applications. However, minimizing address operations alone may not directly reduce code size and schedule length for DSPs with multiple functional units. Little research work has been conducted on loop optimization with address offset assignment problem for architectures with multiple functional units. In this paper, we combine loop scheduling, array interleaving, and address assignment to minimize the schedule length and the number of address operations for loops on DSP architectures with multiple functional units. Array interleaving is applied to optimize address assignment for arrays in loop scheduling process. An algorithm, Address Operation Reduction Rotation Scheduling (AORRS), is proposed. The algorithm minimizes both schedule length and the number of address operations. with to list scheduling, AORRS shows an average reduction of 38.4% in schedule length and an average reduction of 31.7% in the number of address operations. Compared with rotation scheduling, AORRS shows an average reduction of 15.9% in schedule length and 33.6% in the number of address operations. [ABSTRACT FROM AUTHOR]

This paper aims at solving the bipartite containment problem for linear singular multi-agent systems (MASs) with multiple dynamic leaders over general signed digraphs, where each leader can be autonomous or dynamically evolving via interactions with its neighboring leaders. To this end, we first establish some properties for the Laplacian matrices of signed digraphs. Then, three distributed observer-based bipartite containment protocols are proposed using different local output information. Multi-step algorithms for constructing the corresponding proposed protocols are also given. It is shown that under the proposed control protocols, bipartite containment can be achieved for any admissible initial states provided that the underlying signed digraph is weakly connected. Compared to the existing related works, the major contribution of present work is that the developed results are applicable for arbitrary weakly connected signed digraphs, no matter whether they are sign-symmetric or sign-asymmetric and whether they are structurally balanced or unbalanced. Two numerical examples are finally given to demonstrate the validity of our results. [ABSTRACT FROM AUTHOR]

Active learning method (ALM) is a powerful fuzzy–based soft computing methodology suitable for various applications such as function modeling, control systems, clustering and classification. Despite considerable advantages, the main computational engine of ALM, ink drop spread (IDS), is memory-intensive, which imposes significant area overheads in the hardware realization of the ALM for real–time applications. In this paper, we propose a compressed model for ALM which greatly alleviates the storage limitations. The proposed approach employs a distinct inference algorithm, enabling a significant reduction in memory utilization from $O(N^{2})$ to $O(2N)$ for a multi–input single–output (MISO) system. Also, the computational costs in both training and inference modes are decreased to only a few additions and multiplications. Furthermore, we develop a memory–efficient digital architecture for the proposed compressed ALM algorithm that can be leveraged for various computing systems through configuring a few registers. Finally, we assess the performance of the proposed approach using various function modeling and classification applications and provide a comparison with conventional ALM and some other well-know approaches. Simulation and hardware implementation results demonstrate that the proposed approach achieves reduced noise sensitivity with $128\times $ reduction in the average memory usage while realizing comparable accuracy compared to the other approaches studied herein. [ABSTRACT FROM AUTHOR]

This paper presents an area-efficient architecture for stochastic low-density parity-check (LDPC) decoder with high throughput and excellent bit-error-rate (BER) performance. The correlation effects of a stochastic Sum-Product Algorithm (SPA) are analyzed. Based on this analysis, a variable node (VN) structure is proposed and its similarity with a correlation divider (CORDIV) is pointed out. Based on the properties of CORDIV, the area of probability tracer in the VN is reduced significantly. In order to achieve more accurate results when the check-to-variable (C2V) messages are not strong enough, the 3-3 input grouping sub-node is replaced by an adder-based 5-1 input grouping sub-node of the degree-6 VN for (2048,1723) code. An unbiased stochastic sequence generator is adopted to get more accurate results from the smaller probability tracer. Furthermore, the soft bit-flipping prior-processing and the C2V-based hard decision updating method are combined in VN to reduce the decoding latency. A (2048,1723) stochastic LDPC decoder is designed in the TSMC 65 nm process to demonstrate the proposed decoder architecture. With the aid of early termination, the decoder occupies 2.34 mm2 core area and can achieve 116.17 Gb/s at 4.4 dB and 461.99 Gb/s at 5.5 dB under 970 MHz with better decoding performance. Compared with the state-of-the-art stochastic IEEE 802.3an LDPC decoders, the proposed architecture can achieve the best throughput, throughput-to-area ratio, and BER performance. [ABSTRACT FROM AUTHOR]