Search

Monolithic three-dimensional (M3D) integration is viewed as a promising improvement over through-silicon-via-based 3-D integration due to its greater inter-tier connectivity, higher circuit density, and lower parasitic capacitance. With M3D integration, network-on-chip (NoC) communication fabric can benefit from reduced link distances and improved intra-router efficiency. However, the sequential fabrication methods utilized for M3D integration impose unique interconnect requirements for each of the possible partitioning schemes at transistor, gate, and block granularities. Further, increased cell density introduces contention of available routing resources. Prior work on M3D NoCs has focused on the benefits of reduced distances, but has not considered these process-imposed circuit complications. In this article, NoC topology decisions are analyzed in conjunction with these M3D interconnect requirements to provide an equivalent architectural comparison between M3D partitioning schemes.

Battery-less IoT devices powered through energy harvesting face a fundamental imbalance between the potential volume of collected data and the amount of energy available for processing that data locally. We explore a combination of approximate computing and intermittent computing-incidental approximate architecture to suit nonvolatile processors (NVPs).

After two decades of research effort, fine-pitched 3D integrated circuits are finally appearing in a growing range of industry products that leverage the benefits of high-bandwidth, high-density circuit integration. This article reflects on the historical development of these 3D technologies, their unique benefits over alternate 3D packaging methods, and the recent industry and research trends in 3D memories and 2.5D integration. Although die stacking is now happening, many potential benefits offered by these technologies remain to be explored, providing an opportunity for researchers and developers to solve these remaining challenges in architecture, methodology, and business.

Designers making deep learning computing more efficient cannot rely solely on hardware. Incorporating software-optimization techniques such as model compression leads to significant power savings and performance improvement. This article provides an overview of DeePhi's technology flow, including compression, compilation, and hardware acceleration. Two accelerators, named Aristotle and Descartes, are designed to achieve extremely high energy efficiency for both client and datacenter applications with convolutional neural network and recurrent neural network, respectively.

Nonvolatile processors (NVPs) have integrated nonvolatile memory to preserve task-intermediate on-chip state during power emergencies. NVPs hide data backup and restoration from the executing software to provide an execution mode that will always eventually complete the current task. NVPs are emerging as a promising solution for energy-harvesting scenarios, in which the available power supply is unstable and intermittent, because of their ability to ensure that even short periods of sufficient power, on the order of tens of instructions, will result in net forward progress. This article explores the design space for an NVP across different architectures, input power sources, and policies for maximizing forward progress in a framework calibrated using measured results from a fabricated NVP. The authors propose a heterogeneous microarchitecture solution that more efficiently capitalizes on ephemeral power surpluses.

This article provides insights into the design of nonvolatile processors (NVPs) for batteryless applications in the Internet of Things (IoT), in which ambient energy-harvesting techniques provide the power. Achieving reliable, continuous, forward computation with an unstable, intermittent power supply motivates the transition from conventional volatile processors to emerging NVPs. The authors discuss the various design factors and tradeoffs involved in optimizing this forward progress. This article provides a guide for future IoT applications, revealing inherent features of energy-harvesting NVP design.