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This article presents a 150-GHz regenerative low-power miniature two-way radio integrated with on-chip antennas. The low-power radio is based on a reconfigurable fundamental oscillator array that can be used as a sub-terahertz (THz) source in the transmitter (Tx) mode and a sub-THz super-regenerative detector in the receiver (Rx) mode supporting ON–OFF keying (OOK) modulation. The oscillators are coupled through a low-loss integrated Marchand balun-based coupling network that guarantees far-field constructive interference at the Rx side. A 2 $\times $ 2 on-chip patch antenna array is designed with a new adaptive metal-fill placement methodology that largely reduces antenna losses and off-tuning present in sub-THz/THz frequency antenna designs without the need for bulky silicon lenses. Our proof-of-concept prototype achieves a maximum EIRP of 8.52 dBm at a frequency of 149 GHz, an Rx sensitivity of −70 dBm, and a dc-to-EIRP efficiency of 30.7% with no silicon lens, which is the highest efficiency reported of all the silicon-based sub-THz transceivers (TRxs) in the 150-GHz range. The moderate 2 $\times $ 2 array size with no silicon lens offers a large field of view (FoV) of ±40°, which eases node finding and link establishment in deployment. Our miniature low-power radio prototype consumes 11.6 mW in the Tx mode and 10 mW in the Rx mode after duty cycling. Wireless peer-to-peer network measurements with OOK modulation using a 10-Mb/s data rate demonstrate a chip-to-chip communication distance of 70 cm and BER $\le $ 10 $^{-5}$ at/above −55-dBm received power and a BER of 6 $\times $ 10 $^{-3}$ at −70-dBm received power. The prototype chip was designed using the GlobalFoundries 45-nm silicon-on-insulator (SOI) process, and it occupies a total chip area of 2.1 mm $\times $ 2.1 mm, including the antenna array, making it particularly apt for ultra-miniaturized, high-security, and stealth Internet-of-Things (IoT) nodes for intelligent edge networks and wearable devices. [ABSTRACT FROM AUTHOR]

In this article, a 22.9–38.2-GHz dual-path noise-canceling low noise amplifier (LNA) is proposed, which can achieve a low noise figure (NF) by reducing the noise of both paths. Such LNA consists of one common gate (CG) amplifier with one three-stage transformer, one resistive feedback common-source (CS) amplifier, and two amplitude-adjusting amplifiers. The three-stage transformer is used in the CG amplifier to provide gain-boosting, noise-reducing, and wideband inter-stage matching operation, simultaneously. Meanwhile, amplitude-adjusting amplifiers with reconfigurable phase-tuning lines are utilized in both paths to optimize the noise-canceling performance. To verify the aforementioned principle, a dual-path noise-canceling LNA is implemented and fabricated using a conventional 28-nm CMOS technology. The proposed LNA consumed 18.9 mW under a 0.9-V supply. The measured NF is 2.65–4.62 dB within the operating frequency range of 22.9–38.2 GHz, while the peak gain is 14.5 dB. The in-band input 1-dB compression point (IP1 dB) and input third-order intercept point (IIP3) are −13.2 to −6.6 and −3.6 to 3.2 dBm, respectively. [ABSTRACT FROM AUTHOR]

This article reports the concept of a double maximum achievable gain (double- $G_{\mathrm{ max}}$) core for the implementation of sub-terahertz high-gain amplifier design. The double- $G_{\mathrm{ max}}$ core is a $G_{\mathrm{ max}}$ core that adopts another linear, lossless, and reciprocal network that satisfies the $G_{\mathrm{ max}}$ condition onto an even number of cascaded transistor-level $G_{\mathrm{ max}}$ cores. It is shown that the double- $G_{\mathrm{ max}}$ core, due to its regenerative nature, can achieve much higher gain per stage than that of the same number of cascaded $G_{\mathrm{ max}}$ cores while satisfying the unconditional stability. Implemented in a 65-nm CMOS process, by adopting the proposed double- $G_{\mathrm{ max}}$ core, 247- and 272-GHz two-stage amplifiers achieve the peak gain of 18 and 15 dB, the gain per stage of 9 and 7.5 dB, and the PAE of 4.44% and 2.37%, respectively, while dissipating 21.5 mW. [ABSTRACT FROM AUTHOR]

Recently, mm-wave multi-in multi-out (MIMO) arrays are garnering significant attention because of their ability to form multiple spatial beams, achieving significantly higher data rates compared to traditional phased array-based approaches. Furthermore, scalable MIMO arrays can provide many other functionalities, such as full digital beamforming and per-power amplifier (PA) digital pre-distortion. In this work, an MIMO four-element TX array architecture is presented with a frequency-domain multiplexing-based single-wire interface (SWI), breaking the tradeoff between channel-to-channel isolation and single wire (SW) bandwidth (BW). The concept of harmonic-rejection mixing (HRM) is used to de-multiplex the four modulated signals simultaneously from the SW using a single passive mixer driven by a multi-phase local oscillator (LO). The two-stage harmonic recombination circuits are implemented in baseband and, hence, achieve high channel-to-channel isolation with a low power overhead. A 60-GHz four-element TX prototype demonstrates the proposed architecture in 45-nm RF silicon-on-insulator (RFSOI) CMOS. The frequency-division-multiplexed (FDM)-based SWI can support 8-GHz total intermediate frequency (IF) BW across the four channels with 30–40-dB channel-to-channel isolation. Each TX element in the array achieves 20–35-dB conversion gain and +8.8–10.9-dBm OP1dB while consuming 225 mW/element. [ABSTRACT FROM AUTHOR]

An automotive 77-GHz long-range radar (LRR) with an 8-channel receiver (RX) and a 3-channel transmitter (TX) in 40-nm CMOS technology is presented. It integrates a 38.5-GHz phase-locked loop (PLL), a transmitter power detector (DET) and power calibration loop, a crystal oscillator (XO), built-in-self-test (BIST) circuits, an SRAM, an eFuse, a temperature compensation calibration loop with a lookup table (LUT) and a temperature sensor, a serial peripheral interface (SPI), and a multiple-input multiple-output (MIMO) control logic. The receiver shows a noise figure (NF) of 8.7 dB and input-referred 1-dB compression point (IP1-dB) of −7.4 dBm. The NF and IP1-dB under the worst conditions are 14 dB and −10 dBm, respectively. The transmitter shows output power of 14.1 dBm and phase noise of −116 dBc/Hz at a 12.5-MHz offset frequency, which corresponds to the frequency of 250-m objects for the fast-chirp frequency-modulated continuous wave (FMCW) radar. The proposed radar module utilizes two transmitter channels for horizontal detection. A 2 $\times $ 8 time-division-multiplexing MIMO (TDM-MIMO) technique provides a detection range of 250 m. [ABSTRACT FROM AUTHOR]

Massive multiple-input multiple-output (MIMO) wireless communication systems mandate strict power and area requirements for receiver (RX) front ends, while noise performance can be relaxed due to averaging over the array. To address these needs at mm-waves, we propose an integrated mixer-first RX, leveraging frequency-translational feedback and passive voltage gain, to minimize the RX power consumption. An analytical model is developed, thus providing useful intuition on optimal design choices. A 28-nm CMOS prototype achieves S11< −10 dB, NF < 10 dB, and ~20-dB conversion gain over all the mm-wave $E$ -band (71–95 GHz), while consuming only 12 mW including the local oscillator buffers. The power can be further reduced to 8 mW, with similar performance over a 74–94-GHz RF bandwidth. [ABSTRACT FROM AUTHOR]

A CMOS 170-GHz fundamental-frequency transmitter (TX) realizing the 8PSK modulation scheme directly in the RF domain is presented. The use of direct RF modulation obviates the need for high-resolution high-speed mixed-signal blocks. The proposed architecture extends the conventional quadrature modulation by performing additional phase modulation on I and Q components of the LO signal, which helps increase modulation order. The TX employs high-speed switchable phase shifters to achieve LO phase modulation and fundamental-frequency over-neutralized power amplifiers to drive an integrated two-element tapered dipole antenna array. Fabricated in a 65-nm CMOS process ($f_{T}/f_{\text {max}} = 230$ /260 GHz), the RF-8PSK TX prototype occupies $3.2 \times 2.8$ mm2 of die area. The free-space wireless measurement of the TX over a 10-cm link range yields 15 Gb/s data rate at an error vector magnitude (EVM) of −14.8 dB. The TX achieves an EIRP of 4 dBm while consuming 560-mW power. [ABSTRACT FROM AUTHOR]

This paper presents the analysis and design of wideband I/Q CMOS modulators and transmitters. Non-idealities and performance limitations of Cartesian transmitter and modulator systems are discussed, and circuit design techniques and analyses are shown. A DC-60 GHz I/Q modulator/transmitter chip in 45-nm SOI CMOS is presented as a critical building block for next-generation multi-standard and high-capacity wireless backhaul links. The modulator consists of a wideband quadrature signal generator, wideband buffers, and two current-combined DC-100 GHz low-noise double-balanced mixers driven in quadrature. The 1.4 mm2 modulator chip achieves 60 dB of dynamic range in a 1-GHz bandwidth, with an OP1dB of ~ −10 dBm, thus enabling spectrally efficient high-order modulation schemes such as 256-QAM. The I/Q modulator achieves 200 Gb/s in 16-QAM (50 Gbaud/s) while consuming 200 mW, resulting in record 1-pJ/bit modulation efficiency. In addition to backhaul links, the modulator is an attractive and cost-effective alternative to short-range optical links for data center interconnects (DCI) and for chip-to-chip communications. [ABSTRACT FROM AUTHOR]

There is a lower bound on the size of a planar inductor below which significant $Q$ -degradation occurs. While this bound can limit the absolute performance of an $LC$ oscillator at any frequency, it is usually only encountered when designing at mm-wave and above. The classic way to mitigate the issue is through the use of NMOS-only and/or multi-core designs. Such techniques, however, are often not suitable for mm-wave commercialization; NMOS-only designs require thick-oxide devices, while multi-core designs need to be carefully controlled at startup to avoid unwanted oscillation modes. The circular geometry topology, first proposed in 2004, appears to overcome these issues, but, surprisingly, it has not yet been adapted to mm-wave frequencies. In this paper, we show how the topology is well suited to high-frequency applications. A quad-core 27-GHz $LC$ oscillator is presented that has a single high- $Q$ mode. The suppression of the three unwanted modes removes any mode ambiguity and enhances the $Q$ of the wanted mode. The design is fully complementary and, so, is compatible with the use of high $f_{T}$ thin-oxide devices. The near mm-wave prototype achieves a figure of merit of 187 dBc/Hz and a tuning range of 26%. The measured phase noise is −110 dBc/Hz@1 MHz, which is among the lowest reported for a fully complementary near mm-wave design. [ABSTRACT FROM AUTHOR]

This paper describes a general technique for reducing oscillator phase noise in LC voltage-controlled oscillators (VCOs). Phase noise is reduced using a circuit topology that decouples the LC tank from the active devices using capacitive transformers, thereby achieving a higher amplitude of oscillation not limited by the transistor breakdown voltage. Moreover, the proposed VCO topology reduces active device noise injection into the tank by further improving phase noise. As proof of concept, two VCOs operating at 16–19 GHz and 31.8–39.6 GHz, respectively, are implemented in the Global Foundries (GF) 130-nm SiGe BiCMOS 8HP technology ($f_{T}/f_{\text {MAX}}$ of 200/280 GHz). The lower frequency VCO achieves a phase noise of −110 dBc/Hz at a 1-MHz offset from a 17-GHz carrier while the higher frequency VCO achieves a phase noise of −103.2 dBc/Hz at a 1-MHz offset from a 36-GHz carrier. The higher frequency VCO was also implemented in a second, more advanced GF 130-nm SiGe BiCMOS 8XP technology ($f_{T}/f_{\text {MAX}}$ of 260/320 GHz), yielding a further average phase noise improvement of 1.9 dB over the 8HP version. [ABSTRACT FROM AUTHOR]

A ${D}$ -band I/Q RF-DAC featuring two 6-bit DAC elements driven in quadrature, each with its own on-die antenna, and a total effective isotropic radiated power (EIRP) of 13.2 dBm, is demonstrated in a 45-nm SOI-CMOS technology. The carrier signal is first amplified by the 30-dB gain LO path and is directly modulated by the 12 baseband bit streams, without linear upconversion or power amplification. QPSK, 8-PSK, 16-QAM, 32-QAM, and 64-QAM single-carrier (SC) and OFDM constellations are formed in free space and measured above the die at data rates up to 12 Gb/s and at distances over 15 cm. The large-signal bandwidth—from the carrier input pad to the output of the transmitter above the antennas—is 130–142 GHz and was obtained by sweeping the frequency of the ${D}$ -band external carrier, modulating it on die at 0.4 Gb/s using 16-QAM format, and measuring the error vector magnitude (EVM) with an instrumentation receiver. The highest data rate of 12 Gb/s was measured for QPSK SC modulation with a corresponding EVM of −12.2 dB. Lower maximum data rates of 7 Gb/s with −14.3-dB EVM and 3.6 Gb/s with −19-dB EVM were observed for 16-QAM and 64-QAM formats, respectively. Spectral shaping and OFDM transmission were also demonstrated at up to 2.5 Gb/s. The prototype consumes a total of 1.25 W, with an energy efficiency of 104 pJ/b. [ABSTRACT FROM AUTHOR]

This paper describes a 28-GHz CMOS direct conversion transceiver with packaged $2 \times 4$ patch antenna array for 5G communication. Beamforming antenna and reconfigurable transceiver architecture are used for high effective isotropic radiated power (EIRP). For low error vector magnitude (EVM), switchless matching transmitter (Tx)/receiver (Rx) to antenna and 28-GHz injection-locked local oscillator (LO) generator are employed. Test chip was fabricated in 28-nm RF CMOS process. Measurement results show Tx EIRPsat of 31.5 dBm ( $P_{\mathrm {sat}}$ of 10.5 dBm in one power amplifier (PA)), EIRPmax 24 dBm ( $P_{\mathrm {max}}$ of 2 dBm with backoff of 7.5 dB in one PA), Rx noise figure of 6.7 dB, and integrated LO phase noise of −38.7 dBc (0.67°). After IQ mismatch calibration, Tx LO leakage and image power are less than −35 dBc. Rx and Tx EVM show 2.2% (−33 dB) at medium RF power (Rx $P_{\mathrm {in}}$ of −60 dBm and Tx EIRP of 0 dBm) with well-fit beam control capability. [ABSTRACT FROM AUTHOR]

This paper presents a scalable 28-GHz phased-array architecture suitable for fifth-generation (5G) communication links based on four-channel ( $2\times 2$ ) transmit/receive (TRX) quad-core chips in SiGe BiCMOS with flip-chip packaging. Each channel of the quad-core beamformer chip has 4.6-dB noise figure (NF) in the receive (RX) mode and 10.5-dBm output 1-dB compression point (OP1dB) in the transmit (TX) mode with 6-bit phase control and 14-dB gain control. The phase change with gain control is only ±3°, allowing orthogonality between the variable gain amplifier and the phase shifter. The chip has high RX linearity (IP1dB = −22 dBm/channel) and consumes 130 mW in the RX mode and 200 mW in the TX mode at P1dB per channel. Advantages of the scalable all-RF beamforming architecture and circuit design techniques are discussed in detail. 4- and 32-element phased-arrays are demonstrated with detailed data link measurements using a single or eight of the four-channel TRX core chips on a low-cost printed circuit board with microstrip antennas. The 32-element array achieves an effective isotropic radiated power (EIRP) of 43 dBm at P1dB, a 45-dBm saturated EIRP, and a record-level system NF of 5.2 dB when the beamformer loss and transceiver NF are taken into account and can scan to ±50° in azimuth and ±25° in elevation with < −12-dB sidelobes and without any phase or amplitude calibration. A wireless link is demonstrated using two 32-element phased-arrays with a state-of-the-art data rate of 1.0–1.6 Gb/s in a single beam using 16-QAM waveforms over all scan angles at a link distance of 300 m. [ABSTRACT FROM AUTHOR]

Signal sources at mm-wave and (sub-)terahertz frequencies in CMOS can be classified into two broad categories: harmonic oscillators and oscillators that are based on the frequency multiplication of fundamental sources. This paper shows that frequency-multiplier-based sources potentially have a higher dc-to-RF efficiency than do the popular harmonic oscillators in 65-nm CMOS. To improve the power efficiency of CMOS signal sources that operate near or above the cutoff frequency of the device, design factors including the harmonic current efficiency, the effective output conductance, and the passive losses should be carefully tailored. An architecture is proposed in which: 1) the core voltage-controlled oscillator is optimized to efficiently generate a strong fundamental harmonic; 2) separate class-C frequency doublers are utilized to decouple fundamental signal generation and harmonic extraction and to reduce conductance loss; and 3) doubler circuits are separately optimized to simplify the output matching and power combining network, and hence avoid long and lossy transmission lines. A circuit prototype shows a measured peak output power and dc-to-RF efficiency of 3 dBm and 2.95%, respectively. [ABSTRACT FROM AUTHOR]

This paper presents Gb/s-speed circuit building blocks in 32-nm CMOS SOI, for a > 20-Gb/s Cartesian direct-modulation W -band transmitter. Transmitter systems non-idealities and performance limitations are discussed, and circuit design techniques and analyses are presented. The transmitter employs two 2-b high-speed RF digital-to-analog converters driven in quadrature, 20-dB gain W -band LO drivers, and 30-Gb/s high-speed digital retimers and deserializers, and is capable of supporting BPSK/PAM4/QPSK/16-QAM modulation schemes, at a saturated output power P\mathrm{ sat} of +4 dBm. A maximum data rate of 20 Gb/s was achieved when operating in QPSK mode, 4 Gb/s in 16-QAM mode, and 12 Gb/s in both BPSK and PAM4 modes. The chip occupies 1.40.8 mm2 and consumes 110 mW in BPSK/PAM4 modes and 220 mW in QPSK and 16-QAM modes, resulting in the state-of-the-art 9-, 11-, and 55-pJ/b peak efficiencies, respectively. A mixer-first wideband W -band receiver that includes a passive mixer and a wideband transimpedance amplifier is also presented. Measurements of the receiver chip demonstrated its capability to downconvert and amplify highly complex modulated waveforms (> 256-QAM), and at high data rates, up to 60 Gb/s in 64-QAM, which proves the feasibility of building high dynamic-range mm-wave receivers with bandwidth greater than 30 GHz. The receiver chip was also built in 32-nm CMOS SOI, occupying a core area of 0.180.1 mm2 [ABSTRACT FROM AUTHOR]

In this paper, we present a scalable architecture in silicon that allows synthesis and dynamic waveform shaping of periodic mm-wave signals, either generated on-chip or quasi-optically through radiation in free space capable of producing pulse trains with picosecond time signatures. This is achieved through an architecture that allows extraction of multiple harmonics above f\mathrm {max} with simultaneous amplitude and phase control. Signal synthesis is achieved through controlled interference of multiple traveling waves with rich harmonic components and delays. The first example, presented in this paper, is where the signal synthesis is achieved on-chip demonstrating a pulse train at the output with a measured pulsewidth of 2.6 ps and a 0.46-mW output power. The second example is a four-element array with integrated antennas, which allows signal synthesis in space and is demonstrated to show reconfigurable radiation of pulse trains with a 2.6-ps pulsewidth, pure tones at a fundamental frequency of 107.5 GHz with an effective isotropic radiated power (EIRP) of 4.6 dBm and a second harmonic of 215 GHz with EIRP of 5.0 dBm, as well as any combination of these two harmonics with arbitrary amplitudes and delays. To the best of the authors’ knowledge, this paper demonstrates the sharpest on-chip and radiated pulses with dynamic waveform shaping in any integrated circuit technology. This can open the door to innovations in broadband terahertz imaging, sensing, and spectroscopy. [ABSTRACT FROM AUTHOR]

This work presents a highly integrated 57–64 GHz 4-channel receiver 2-channel transmitter chip targeting short range sensing and large bandwidth communications. The chip is housed in an embedded wafer level ball grid array package. The package includes 6 integrated patch antennas realized with a metal redistribution layer. The receiver patch antennas have a combined antenna gain of $\approx 10$ dBi while each transmitter antenna has a gain of $\approx ~6$ dBi. The chip features a wide tuning range integrated VCO with a measured phase noise lower than −80 dBc/Hz at 100 kHz offset. Each of the differential transmitter channels shows a measured output power of 2–5 dBm over the complete frequency range. In addition, one transmitter channel features a modulator that can be digitally programmed to operate in either radar or communication mode. Each of the receiver channels has a measured conversion gain of 19 dB, a single-sideband noise figure of less than 10 dB and an input referred 1 dB compression point of less than 10 dBm. With all channels turned on the chip consumes a current of 300 mA from a 3.3 V supply. The functionality of the chip is demonstrated for both sensing and short range wireless communications. [ABSTRACT FROM AUTHOR]

This paper describes a novel low-noise input-termination-less cascode distributed amplifier (DA) monolithic microwave integrated circuit (MMIC) design. The design was implemented with a 0.15 \mu \textm gate gallium nitride on silicon carbide GaN-SiC high electron mobility transistor (HEMT) 6 inch wafer process technology. The GaN MMIC achieves a bandwidth from 100 MHz–45 GHz with greater than 10 dB gain and previously benchmarked the first published mm-wave MMIC results produced on a 6 inch GaN on SiC wafer process technology. The unique input-gate-termination-less DA topology reduces the low-frequency noise figure (NF) of the conventional resistive-terminated DA without compromising the third order intercept point (IP3) linearity. The new design achieves 1.6 dB NF at 250 MHz and a NF improvement of at least 1 dB and as much as 4 dB or greater for frequencies below 5 GHz compared to the conventional DA approach. The GaN MMIC also achieves an average mid-band NF of 2.5–3 dB, a saturated output power (\mathrm P\mathrm {sat}) of 1 Watt, and a mid-band output IP3 of 38 dBm. The new design architecture combined with the inherent device characteristics of GaN-SiC technology can provide performance benefits for next-generation coherent fiber optic, instrumentation and advanced broadband radio architecture applications. [ABSTRACT FROM AUTHOR]

This paper proposes a mm-wave frequency generation technique that improves its phase noise (PN) performance and power efficiency. The main idea is that a fundamental 20 GHz signal and its sufficiently strong third harmonic at 60 GHz are generated simultaneously in a single oscillator. The desired 60 GHz local oscillator (LO) signal is delivered to the output, whereas the 20 GHz signal can be fed back for phase detection in a phase-locked loop. Third-harmonic boosting and extraction techniques are proposed and applied to the frequency generator. A prototype of the proposed frequency generator is implemented in digital 40 nm CMOS. It exhibits a PN of -100\;\textdBc/Hz at 1 MHz offset from 57.8 GHz and provides 25% frequency tuning range (TR). The achieved figure-of-merit (FoM) is between 179 and 182 dBc/Hz. [ABSTRACT FROM PUBLISHER]

Frequency synthesis at mm-wave range suffers from a severe tradeoff between phase noise (PN) and frequency tuning range (FTR). This work presents the analysis and compares the performance of fundamental-mode voltage-controlled oscillators (F-VCOs) to harmonic-mode VCOs (H-VCOs). It is shown that unlike a mm-wave F-VCO, an H-VCO can simultaneously achieve higher FTR and lower PN. An H-VCO architecture, denoted as self-mixing VCO (SMV), is presented where the VCO core generates both the first (f_0) and second harmonic (2f_0) and then mixes them together to obtain the desired mm-wave third-harmonic (3f_0). Use of a Class-C push–push topology as the VCO core enhances the second-harmonic content to improve mixing efficiency, decreases parasitic capacitance, and improves PN. Compared to an F-VCO operating in a mm-wave band at a fundamental frequency that equals 3f_0, the proposed SMV architecture achieves about 2\times CMOS process. Measurement results show that the VCO achieves an FTR of 16.8% with a PN of -100.6\text dBc/Hz at 1 MHz offset—resulting in an FTR-inclusive figure-of-merit (\textFoM_\textT) of -190.85\text dBc/Hz while consuming 7.6 mW from a 1.2 V supply. [ABSTRACT FROM PUBLISHER]

This paper presents a low-power low-noise 60 GHz frequency synthesizer using a 20 GHz subsampling phase-locked loop (SS-PLL) and a 60 GHz tail-coupling quadrature injection-locked oscillator (QILO) which results in a lower in-band phase noise and out-of-band phase noise, respectively. To save battery life, dual-step-mixing injection-locked frequency divider (ILFD) enhances locking range for high division ratio. Moreover, tail cross-coupling technique in a QILO helps boost negative transconductance $({{-g}}_{m}) of the 60 GHz QILO which allows the use of larger inductance for power reduction. Implemented in 65 nm CMOS, it can cover required channels from 58.32 to 64.80 GHz with quadrature outputs. It consumes 24.2 and 7.8 mW from 20 GHz SS-PLL and QILO, respectively. The proposed synthesizer achieves -78.5\; \textdBc/Hz at 100 kHz offset, -122\textdBc/Hz at 10 MHz offset, and a figure-of-merit (FoM) of -236\textdB. [ABSTRACT FROM PUBLISHER]

A fully integrated 802.11ad/WiGig compliant 60 GHz transceiver is presented in a 130 nm SiGe BiCMOS technology. Encompassing an area of 2.3 mm\, \times \,2.16 mm = 4.97 mm^2, the transceiver covers the entire 60 GHz band, from 57 to 66 GHz. Within this span, the RX NF, TX OP1dB, and PLL RMS jitter is better than 5.5 dB, + 13.5 dBm, and 7^\circ, respectively. The transceiver is packaged in 1) a system-in-package substrate with industry standard WR-15 transition providing an approximate 1 dB insertion loss, and 2) a cost-effective 7\, \times \,7 mm^2 organic BGA package with integrated transmit and receive antennas providing 8 dBi gain. In system-level testing, the transceiver is fully compliant with all TX EVM and RX sensitivity requirements of the WiGig standard up to the top-rate 16-QAM operating mode and across all standard channel frequencies. Link testing over the air with the antenna-integrated package shows a range of 5.9 m at 4.6 Gbps and over 20 m at 2.5 Gbps. This system achieves the highest performance 802.11ad/WiGig compliant wireless links of any reported single-element transceiver. [ABSTRACT FROM PUBLISHER]

This paper introduces a 2nd harmonic extraction technique and its implementation in a 46.4–58.1 GHz frequency synthesizer. The frequency doubling approach is based on tapping second harmonic signals at the VCO supply and tail nodes and amplifying them to provide a differential output. Since the amplifiers do not load the VCO outputs, the proposed technique does not affect either the tuning range or the frequency of the VCO. Moreover, a novel noise bypass technique is utilized to ensure that the amplifiers do not degrade the VCO phase noise. As a result, the frequency synthesizer achieves 22.4% tuning range (46.4–58.1 GHz) and phase noise below –118 dBc/Hz while consuming 66 mW from a 1 V supply. The stacked common gate amplifier can also be utilized for voltage regulation, providing a relatively constant FOM performance over a 2X power dissipation range. The synthesizer occupies 0.6 mm \times 1 mm in IBM 32 nm SOI CMOS. [ABSTRACT FROM AUTHOR]

This paper studies the maximum Baud rate and the scalability to the W-Band of the mm-wave power-DAC transmitter architecture. Proof-of-concept implementations of a single DAC lane and of a 2×2 IQ transmitter array are reported in 45 nm SOI CMOS. The DAC cell achieved 29 GHz OOK and 29 GHz BPSK modulation bandwidth and 2×44 Gb/s BPSK+OOK data rates for carriers in the 100–110 GHz range. The corresponding energy efficiency is 7.5 pJ/bit at an output power of 12 dBm. For the 2×2 IQ array, an EVM of 9.0% is estimated over a 12 GHz bandwidth, from large signal power and S-parameter phase measurements. [ABSTRACT FROM AUTHOR]

We present a new millimeter-wave power-combining technique using transmission-line baluns which both connect transistor outputs in series and inductively tune the transistor output capacitances. The baluns are much shorter than a quarter-wavelength (\lambda/4), hence are more compact and have less insertion loss than a \lambda/4 balun. We introduce one topology providing an even number of series connections, including 2:1 and 4:1, and a second topology providing either an even or odd number of series connections. We then analyze segmented transformer power-combiners as a set of multi-conductor transmission-lines, and explore the relationship between transformer and transmission-line balun power-combiners. We demonstrate the technique with 2:1 and 4:1 series-connected designs implemented in a 0.25 \mum InP HBT process. At 86 GHz, a single-stage power amplifier (PA) using the 2:1 baluns exhibits 30.4% peak PAE, 20.37 dBm output power (Pout) and 23 GHz 3-dB bandwidth from a 448\, \times \,816 \mum^2 die. A two-stage PA using the 2:1 baluns exhibits 30.2% PAE, and 23.14 dBm Pout from an 824\,\times\,816 \mum^2 die. At 81 GHz, a two-stage PA with 4:1 series output power-combining exhibits 23.4% PAE, and 26.7 dBm (470 mW) Pout from a 1,080\,\times\,980 \mum^2 die. [ABSTRACT FROM AUTHOR]

This paper presents a 160 GHz center frequency pulsed 65 nm CMOS transceiver for short range radar applications. Four phased array transceivers were implemented in a single chip with antennas implemented in a BGA package. The implemented transmitter is capable of producing pulses of 100 ps widths (>20 GHz RF bandwidth) at a 160 GHz carrier frequency. The measured effective isotropic radiated power (EIRP) is 18.8 dBm for continuous wave outputs. The analog beam forming receiver achieves an overall gain of 42.5 dB, -14 dBm IP1dB, 7 GHz bandwidth, and a noise figure of 22.5 dB. The sliding window time-dilation baseband relaxes the output data rate and subsequent digital processing requirements. Fine grained duty cycling reduces power dissipation. The entire chip consumes 2.2 W from 1.2/1.4 V supplies in a 65 nm digital CMOS process. [ABSTRACT FROM PUBLISHER]

This paper presents a chipset aiming at high resolution imaging systems for real-time people screening applications operating near the W-band. The frequency of operation ranges from 70 GHz to 82 GHz for optimal image resolution and depth of focus. The frequency generation for both receiver and transmitter chips consists of a mixer based frequency quadrupler with an input amplifier requiring -20 dBm of input power. The receiver RFIC contains 4 channels including LO generation and distribution. The measured receiver conversion gain is 23 dB with a SSB NF around 10 dB over a wide frequency range from 70 GHz up to 82 GHz. The transmitter RFIC includes LO generation, distribution and 4 output amplifiers with an output power of more than 0 dBm in a frequency range from 70 GHz to 82 GHz. Both ICs are supplied from a single 3.3 V supply voltage and the power consumption is 180 mW/channel for the receiver and 145 mW/channel for the transmitter. [ABSTRACT FROM PUBLISHER]

A low phase noise, wideband, mm-wave, integer-N PLL that is capable of supporting an 802.15.3c heterodyne transceiver is reported. The PLL can generate 6 equally spaced tones from 43.2 GHz to 51.84 GHz, which is suitable for a heterodyne architecture with FLO=(4/5)\timesFTRX. Phase noise is measured directly at the FLO frequency and is better than -97.5~dBc/Hz@1 MHz across the entire band. The reported frequency synthesizer is smaller, exhibits less phase noise, and consumes less power than prior art. In addition, the FLO tone corresponds to the fundamental of the VCO as opposed to a higher harmonic. [ABSTRACT FROM AUTHOR]

High-rate communications technology leveraging the unlicensed spectrum around 60 GHz is almost ready for deployment with several demonstrations of successful wireless links. [ABSTRACT FROM PUBLISHER]

We present a 4.4-mm^2 single-chip synthesized signal source with 125 MHz to 32 GHz continuous frequency coverage with a minimum frequency step smaller than 10 Hz. The chip is fabricated in a 0.18-μm SiGe BiCMOS 1P6M technology. A core fractional-N synthesizer using a 20-MHz reference frequency has four LC-VCOs and a 4- to 8-GHz synthesizable range. Post-synthesis blocks extend the frequency coverage up to 32 GHz and down to 125 MHz through frequency multiplication and division. In different operation modes, the chip, including a balanced 50-ohm load driver, consumes from 284 to 498 mW. The phase noise performance achieves -117.6 dBc/Hz at 1-MHz offset from a 6-GHz output frequency and -83 dBc/Hz in-band noise. The integrated phase noise is -28 dBc and the absolute jitter is 1.05 psRMS at 6-GHz output. The jitter is maintained nearly constant (between 0.9 and 1.2 psRMS) across the whole output frequency range. [ABSTRACT FROM PUBLISHER]

This paper presents the design of a 60 GHz phase shifter integrated with a low-noise amplifier (LNA) and power amplifier (PA) in a 65 nm CMOS technology for phased array systems. The 4-bit digitally controlled RF phase shifter is based on programmable weighted combinations of I/Q paths using digitally controlled variable gain amplifiers (VGAs). With the combination of an LNA, a phase shifter and part of a combiner, each receiver path achieves 7.2 dB noise figure, a 360^\circ phase shift range in steps of approximately 22.5^\circ, an average insertion gain of 12~dB at 61~GHz, a 3 dB-bandwidth of 5.5 GHz and dissipates 78 mW. Consisting of a phase shifter and a PA, one transmitter path achieves a maximum output power of higher than +8.3 dBm, a 360^\circ phase shift range in 22.5^\circ steps, an average insertion gain of 7.7 dB at 62 GHz, a 3 dB-bandwidth of 6.5 GHz and dissipates 168 mW. [ABSTRACT FROM PUBLISHER]

This work discusses the design methodologies for efficient power generation at mm-wave frequencies in CMOS. Passive elements play an important role in PA design, as they determine both the output power and power gain of the circuit. In this work, we have developed a methodology for design of transformer-coupled power amplifiers. A distributed model of on-chip transformers has been developed that can predict the performance up to very high frequencies, is length scalable and uses only a few parameters, compared to a complete lumped model. Using the model, a two-stage transformer-coupled PA has been designed in 90 nm CMOS. The prototype has one of the highest output powers reported for a 60 GHz CMOS PA. A three-stage improved design with higher gain and efficiency is reported, stressing the importance of driver stage design at these frequencies. The PA has been integrated into a complete transmitter and tested with 10 Gb/s QPSK modulated data. [ABSTRACT FROM AUTHOR]

The commercial potential of the 60 GHz band, in combination with the scaling of CMOS, has resulted in a lot of plain digital CMOS circuits and systems for millimeter-wave application. This work presents a 90 nm digital CMOS two-path 52 GHz phased-array receiver, based on LO phase shifting. The system uses unmatched cascading of RF building blocks and features gain selection. A QVCO with a wide tuning range of 8 GHz is demonstrated. The receiver achieves 30 dB of maximum gain and 7.1 dB of minimum noise figure per path around 52 GHz, for a low area and power consumption of respectively 0.1 mm2 and 65 mW. The presented receiver targets 60 GHz communication where beam-forming is required. [ABSTRACT FROM AUTHOR]

A +20 dBm power amplifier (PA) for applications in the 60 GHz industrial scientific medical (ISM) band is presented. The PA is fabricated in a 0.13-µm SiGe BiCMOS process technology and features a fully-integrated on-chip RMS power detector for automatic level control (ALC), build-in self test and voltage standing wave ratio (VSWR) protection. The single-stage push-pull amplifier uses center-tapped microstrips for a highly efficient and compact layout with a core area of 0.075 mm². The PA can deliver up to 20 dBm, which to date, is the highest reported output power at mm-wave frequencies in silicon without the need for power combining. At 60 GHz it achieves a peak power gain of 18 dB, a 1-dB compression (P1dB) of 13.1 dBm, and a peak power-added efficiency (PAE) of 12.7%. The amplifier is programmable through a three-wire serial digital interface enabeling an adaptive bias control from a 4-V supply. [ABSTRACT FROM AUTHOR]

Integration of mm-wave multiple-antenna systems on silicon-based processes enables complex, low-cost systems for high- frequency communication and sensing applications. In this paper, the transmitter and LO-path phase-shifting sections of the first fully integrated 77-GHz phased-array transceiver are presented. The SiGe transceiver utilizes a local LO-path phase-shifting architecture to achieve beam steering and includes four transmit and receive elements, along with the LO frequency generation and distribution circuitry. The local LO-path phase-shifting scheme enables a robust distribution network that scales well with increasing frequency and/or number of elements while providing high-resolution phase shifts. Each element of the heterodyne transmitter generates +12.5 dBm of output power at 77 GHz with a band- width of 2.5 GHz leading to a 4-element effective isotropic radiated power (EIRP) of 24.5 dBm. Each on-chip PA has a maximum saturated power of +17.5 dBm at 77 GHz. The phased-array performance is measured using an internal test option and achieves 12-dB peak-to-null ratio with two transmit and receive elements active. [ABSTRACT FROM AUTHOR]