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Microwave-induced thermoacoustic (TA) imaging, combining high microwave contrast with high ultrasonic resolution has the potential to revolutionize applications such as continuous healthcare monitoring, point-of-care imaging, and biometric authentication. However, the size, cost, and integration of a high-power microwave transmitter is a key bottleneck in making TA imaging truly portable, affordable, and ubiquitous. Toward that end, this work presents a compact 4.9-GHz pulsed power amplifier (PA) with a 4.87-mm2 active area implemented in a 55-nm BiCMOS technology, operating in a duty-cycled mode and achieving 37.3-dBm peak output power—the highest demonstrated peak power in PAs fabricated on a silicon substrate with deep submicron CMOS integration. We also reconstruct the first known high-fidelity TA images of tissue phantoms using an integrated silicon PA. [ABSTRACT FROM AUTHOR]

This article describes the design and performance of a 140-GHz SiGe and a 100-GHz InP triple-stacked HBT distributed amplifier with active bias terminations. The active bias network is configured to extend the practical low-frequency operation while maintaining gain flatness and linearity. Triple-stacked HBTs are used to increase the gain–bandwidth and linear output capability. The SiGe design is based on HBTs with a peak ƒT/ƒmax of 300/350 GHz and achieves 11.7 dB of gain and a bandwidth from baseband to 140 GHz. The InP HBT design is based on DHBTs with a peak ƒT/ƒmax of 250/250 GHz and obtains a gain of 10.8 dB and a bandwidth of 100 GHz. Although the SiGe design achieves 1.5 times higher gain–bandwidth, the InP DHBT design achieves ~3–4.5 dB greater IP3, P1~dB, and P3 ~dB while consuming only ~23% higher dc power. These results represent the first broadband performance comparison of near-identical (apples–apples) DA designs implemented in SiGe and InP HBT device technologies. Although there are previous reports of larger bandwidth distributed amplifiers in both InP and SiGe technologies demonstrated up through 200 GHz, the InP and SiGe monolithic microwave integrated circuits (MMICs) described in this article are believed to represent the highest bandwidths reported for HBT DAs using practical on-chip active bias terminations. [ABSTRACT FROM AUTHOR]

Effect of silicon technology limitations, including transistor nonidealities, layout parasitics, and low-quality factor on-chip passive components on millimeter wave stacked switching power amplifiers operating at the W -band frequencies (75–110 GHz), is presented in this paper. To mitigate the performance degradation in output power and PAE arising from such causes, high-breakdown voltage, high- f\mathrm{ max} multiport stacked-transistor topologies are proposed for realizing power amplifiers with high output power and high efficiency at 75–110 GHz. A 90-nm silicon germanium (SiGe) BiCMOS process is used to propose active structures comprising of two and three stacked transistors with integrated layout parasitics that achieve f\mathrm{ max} and breakdown voltage of 295 GHz and 8 V and 260 GHz and 11 V, respectively. Functionality of such multiport transistor topologies is demonstrated in proof-of-concept implementations, including a five-stage two-stacked switching power amplifier (PA) that achieves peak output power and PAE of 22 dBm and 19% at 85 GHz, and a six-stage three-stacked PA that achieves peak output power and PAE of 23.3 dBm and 17% at 83 GHz, respectively. For comparison with conventional switching PA designs using native transistor footprints, a five-stage W -band nonstacked Class-E amplifiers is also fabricated in the same 90-nm SiGe BiCMOS process with output power and PAE of 19.5 dBm and 16% at 88 GHz. The superior performance of output power and PAE in designs using the multiport transistor topologies highlights the benefit of the proposed approach. [ABSTRACT FROM AUTHOR]

Performance limits and design techniques for Watt-level power amplification at millimeter-wave (mm-wave) frequencies using silicon germanium (SiGe) HBT Class-E power amplifiers (PAs) is presented in this paper. A Class-E power modulator architecture is proposed for demonstrating high-speed data transmission using ASK modulation at mm-wave frequencies. Several of these 1-b power modulators are power combined to realize a Watt-level digital PA with several levels of output amplitude at mm-wave frequencies. A dynamic load modulation concept is proposed to mitigate the effect of load pulling in the digital PA at power back-off. A tunable transmission line architecture with variable characteristic impedance is proposed to realize this dynamic load modulation network and enable efficiency enhancement at power back-off levels in the Watt-level digital PA. Watt-level power generation at mm-waves was demonstrated in a eight-way combined digital PA with dynamic load modulation, fabricated in a 0.13- \mu \textm SiGe BiCMOS process with $\approx $ 29 dBm (0.8 W) measured output power at 46 GHz, 18.4% peak power-added-efficiency, and 60% of the peak efficiency at 6-dB power back-off. [ABSTRACT FROM AUTHOR]

This paper presents a room-temperature operating superresolution terahertz (THz) planar near-field solid-state sensor breaking the diffraction limit. Contrary to classical superresolution imagers implemented in the optical domain, the sensor features inbuilt illumination, evanescent-field sensing, and detection on a single chip, eliminating the need for any external optics. Both metallic and dielectric objects can be imaged with the sensor and mapped into a monotonic sensor response. It is operated around 533–555 GHz in 130 nm SiGe HBT technology and is capable of resolving structural details with a \mu \textm -range resolution and a high response of up to 21.7 \mu \textA with no amplification stages in the readout path. Here, the stop-band characteristic of a differentially driven 3-D split-ring resonator with high spatial confinement of evanescent surface fields is exploited as an object-tunable transmission modulator inserted in-plane between a tunable 3-push Colpitts oscillator and a broadband power detector. A separate antenna-coupled oscillator breakout provides a radiated power of up to 45 \mu \textW (−13.4 dBm). This paper further demonstrates the 2-D scanned superresolution image with a remarkable SNR of up to 40 dB for the sensor operating at dc. [ABSTRACT FROM AUTHOR]

Design equations and performance limits of Class-E power amplifiers at mm-waves, including the limitations imposed by active and passive devices in a given technology, are presented in this paper. A beyond nominal breakdown voltage Class-E design methodology for SiGe HBT power amplifiers is proposed to generate high output power while maintaining high Class-E efficiency. A mm-wave SiGe stacked Class-E architecture is also introduced to increase the overall voltage swing, with each series stacked device operating in the beyond nominal breakdown mode. The mm-wave beyond BVCEO operation of SiGe HBTs has been demonstrated experimentally in an integrated 45 GHz Class-E power amplifier fabricated in a 0.13 µm SiGe BiCMOS process with 20 dBm measured output power at 31.5% peak power-added efficiency (PAE). The series stacking of mm-wave Class-E power amplifier concept is also verified by fabricating double-stacked and triple-stacked SiGe HBT power amplifiers in 0.13 µm SiGe BiCMOS process which demonstrate a measured output power of 23.4 dBm at 41 GHz with peak PAE of 34.9%. High power, highly efficient, switching power amplifier unit cells presented in this paper can facilitate realization of efficient Watt-level mm-wave digital polar transmitters. [ABSTRACT FROM AUTHOR]

This paper presents HBT terahertz power detectors implemented in an experimental 0.25-\mu\m SiGe process technology with a peak fT/f\max of 280/435 GHz. Based on the nonlinearity of the HBT base-emitter junction, the detector operates as a square-law down converter, mixing terahertz frequencies directly to dc. Fifteen detectors have been arranged in a 3 \times 5-pixel array with differential on-chip ring antennas. The array has been assembled with a hyper-hemispherical silicon lens. Referred to the collecting aperture of the lens, a maximum optical current responsivity RI of 1 A/W and a minimum noise equivalent power (NEP) of about 50 \pW/\sqrtHz have been measured at 0.7 THz with a 125-kHz chopping frequency. The detectors have been characterized from 0.65 to 1 THz. [ABSTRACT FROM PUBLISHER]

Static frequency dividers are widely used technology performance benchmark circuits. Using a 0.25\,\mu\ m 530\,GHz f T/600\,GHz+ f \max InP DHBT process, a static frequency divider circuit has been designed, fabricated, and measured to operate up to 200.6 GHz refid="ref1"/ . The divide-by-two core flip-flop dissipates 228 mW. Techniques used for the divider design optimization and for selecting variants to maximize performance across process changes are also discussed. [ABSTRACT FROM PUBLISHER]

We have successfully designed and fabricated a high-bit-rate low-power decision circuit using InP-InGaAs heterojunction bipolar transistors (HBTs). Its main design feature is the use of a novel master-slave D-type flip-flop (MS-DFF) as the decision circuit core to boost the operating speed. We achieved error-free operation at a data rate of up to 60 Gb/s using an undoped-emitter InP-InGaAs HBT with a cutoff frequency fT of approximately 150 GHz and a maximum oscillation frequency fmax of approximately 200 GHz. Our decision circuit operates approximately 15% faster than one with a conventional MS-DFF core. We also achieved 90-Gb/s operation with low power consumption of 0.5 W using an InP-InGaAs DHBT exhibiting fT and fmax of 232 and 360 GHz, respectively. These results demonstrate that InP-based HBTs and our novel MS-DFF are attractive for making ultrahigh-performance ICs for future optical communications systems operating at bit rates of 100 Gb/s or more. [ABSTRACT FROM AUTHOR]

We describe a quasi-planar HBT process using a patterned implanted subcollector with a regrown MBE device layer. Using this process, we have demonstrated discrete SHBT with ft > 250 GHz and DHBT with ft > 230 GHz. The process eliminates the need to trade base resistance for extrinsic base/collector capacitance. Base/collector capacitance was reduced by a factor of 2 over the standard mesa device with a full overlap between the heavily doped base and subcollector regions. The low proportion of extrinsic base/collector capacitance enables further vertical scaling of the collector even in deep submicrometer emitters, thus allowing for higher current density operation. Demonstration ring oscillators fabricated with this process had excellent uniformity and yield with gate delay as low as 7 ps and power dissipation of 6 mW/CML gate. At lower bias current, the power delay product was as low as 20 fJ. To our knowledge, this is the first demonstration of high-performance HBTs and integrated circuits using a patterned implant on InP. [ABSTRACT FROM AUTHOR]

We describe a 40-Gbit/s-class clock and data recovery (CDR) circuit with an extremely wide pull-in range. A Darlington-type voltage-controlled oscillator (VCO) is newly designed to cover the STM-256/OC-768 full-rate-clock frequencies with a wide frequency margin. We also describe a new lock detector using an exclusive-NOR gate. The CDR IC was fabricated using InP/InGaAs HBTs. Error-free operation and wide eye opening were confirmed for 40-, 43-, and 45-Gbit/s PRBS with a word length of 231 -1. We attached a frequency search and phase control (FSPC) circuit to the chip as a new frequency acquisition aid, and this allows the CDR circuit to pull in throughout a 39–45-Gbit/s range. The peak-to-peak and rms jitter of the recovered clock were 3.6 and 0.48 ps, respectively. [ABSTRACT FROM AUTHOR]

We describe a 40-Gbit/s-class clock and data recovery (CDR) circuit with an extremely wide pull-in range. A Darlington-type voltage \-controlled oscillator (VCO) is newly designed to cover the STM-256/OC-768 full-rate-clock frequencies with a a wide frequency margin. We also describe a new lock detector using an exclusive-NOR gate. The CDR IC was fabricated using InP/InGaAs HBTs. Error-free operation and wide eye opening were confirmed for 40-, 43-, and 45-Gbit/s PRBS with a word length of 231- 1. We attached a frequency search and phase control (FSPC) circuit to ther chip as we new frequency acquisition aid, and this allows the CDR circuit to pull in throughout a 39—45-Gbit/s range. The peak-to-peak and rms jitter of he recovered clock were 3.6 and 0.48 ps, respectively. [ABSTRACT FROM AUTHOR]