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The designs of resistive RAM (ReRAM) macros are limited by 1) a small sensing margin, limited read-VDDmin, and slow read access time (T AC) caused by a high cell-resistance and small cell-resistance-ratio (R-ratio) and 2) poor power integrity and increased energy waste attributable to a large SET dc-current (I DC-SET) resulting from the wide distribution of write (SET)-times (T SET). This study proposes a swing-sample-and-couple (SSC) voltage-mode sense amplifier (VSA) to enable an approximately 1.8+x greater sensing margin for lower VDDmin and a 1.7+x faster read speed across a wide VDD range, compared with conventional VSAs. A 4T self-boost-write-termination (SBWT) scheme is proposed to cut off the I DC-SET of devices with a rapid T SET. The SBWT scheme reduces \99+\% of the I DC-SET with an area penalty below 0.5%. A fabricated 512 row 28 nm 1 Mb ReRAM macro achieved T AC =\404 ns when VDD=\0.27 V and confirmed the I DC-SET cutoff by the SBWT. [ABSTRACT FROM PUBLISHER]

A 128 Mb 0.07 \mu\m^2 6T high-density SRAM bitcell with write-assist circuitry has been successfully implemented using 16 nm high-k metal gate FinFET technology. This study proposes two write-assist techniques: 1) suppressed coupling signal negative bit-line (SCS-NBL) technique and 2) write recovery enhanced lower cell-VDD (WRE-LCV) technique to reduce the SRAM minimal supply voltage. The area overheads of these two techniques are 2% and 3%, respectively. The silicon data show that both of these techniques can improve overall SRAM VMIN performance by more than 300 mV at the 95th percentile. [ABSTRACT FROM PUBLISHER]

This paper describes a dual-core 64-b Xeon MP processor implemented in a 65-nm eight-metal process. The 435-mm² die has 1.328-B transistors. Each core has two threads and a unified 1-MB L2 cache. The 16-MB shared, 16-way set-associative L3 cache implements both sleep and shut-off leakage reduction modes. Long channel transistors are used to reduce subthreshold leakage in cores and uncore (all portions of the die that are outside the cores) control logic. Multiple voltage and clock domains are employed to reduce power. [ABSTRACT FROM AUTHOR]

The 18-way set-associative, single-ported 9 MB cache for the Itanium® 2 Processor uses 210 identical 48-kB sub-arrays with a 2.21-µm² cell in a 130-nm 6-metal technology. The processor runs at 1.7 GHz at 1.35 V and dissipates 130 W. The 432-mm² die contains 592 M transistors, the largest transistor count reported for a microprocessor. This paper reviews circuit design and implementation details for the L3 cache data and tag arrays. The staged mode ECC scheme avoids a latency increase in the L3 Tag. A high Vt implant improves the read stability and reduces the subthreshold leakage. [ABSTRACT FROM AUTHOR]