Search

In this work, we report the concept and experimentally demonstrate the first tunable ferroelectric (Fe) junctionless (JL) transistor (Fe-JLFET), capable of emulating the functionality of biological tri-partite synapses, which is an artificial three-terminal synapse with unique back gate high tuning of the post-synaptic current (PSC). Our device consists of a double-gate 11nm-thin film Fe-JLFET with 10nm Si-doped HfO2 ferroelectric, mimicking the functionality of a tripartite synapse. The gradual ferroelectric switching is exploited to fully reproduce the synaptic plasticity. The back-gate voltage emulates the function of an astrocyte, being used to tune the synaptic weight by more than 400x. Compared to other implementations, the newly proposed tripartite Fe-JLFET synapse device shows simplicity in fabrication, extended programmability, and robustness. We report plasticity until 2000 cycles of operation. Overall, this device concept is promising for CMOS-compatible energy-efficient implementation of future neuromorphic ICs.

In this work, we demonstrate vertical Ge gate-all-around (GAA) nanowire pMOSFETs fabricated with a CMOS compatible top-down approach. Vertical Ge nanowires with diameters down to 20 nm and an aspect ratio of ~11 were achieved by optimized Cl2-based dry etching and self-limiting digital etching. Employing a GAA architecture, post-oxidation passivation and NiGe contacts, high performance Ge nanowire pMOSFETs exhibit low SS of 66 mV/dec, small DIBL of 35 mV/V and a high $\text {I}_{ \mathrm{\scriptscriptstyle ON}}/\text{I}_{ \mathrm{\scriptscriptstyle OFF}}$ ratio of ${2.1}\times {10}^{{6}}$ . The electrical behavior was also studied with temperature-dependent measurements. The deviation between the experimental SS and the ideal kT/q $\cdot $ ln10 values stems from the density of interface traps $(\text {D}_{\text {it}})$ . Our measurements suggest that lowering the top contact resistance is a key to further performance improvement of vertical Ge GAA nanowire transistors.

In-plane-gate transparent SnO2 nanowire transistors gated by SnO2-based solid electrolytes are fabricated on glass substrate at room temperature. Low-voltage (1.0 V) operation of such device is realized due to the large electric-double-layer capacitance of 0.75 μF/cm2 at 20 Hz. The subthreshold slope, current on/off ratio, and field-effect mobility of the in-plane-gate transparent nanowire transistors are estimated to be 92 mV/decade, >; 105, and 106.8 cm2/V · s, respectively. Such low-voltage in-plane-gate transparent nanowire transistors are promising for portable invisible sensors.