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We measured and analyzed the subthreshold degradation of the gate-all-around (GAA) silicon nanowire field-effect transistors with the length of 300/500 nm and the radius of 5 nm. An analytical model incorporating the effect of interface traps quantitatively explained the measured subthreshold swing (SS) degradation. A simple electrostatic argument showed that the GAA device had smaller degradation of SS values than planar devices for the same interface trap densities.

The mobility-degradation factor and the series resistance of cylindrical gate-all-around silicon nanowire field-effect transistors are extracted using the same mobility-degradation model as in the case of planar MOSFETs. The extraction is done by defining an asymptotic voltage as a function of the saturation current measured from devices with various lengths. The extracted mobility-degradation factor is an order of magnitude larger than those of other planar MOSFETs. This result suggests that, while the all-around gate can turn off the electron channel effectively, it creates more interface scattering in the strong inversion condition. The extracted series resistance is mostly due to the crowding of the electron flow along the sidewall of the n+ contact region making an abrupt joint with the nanowire.

This letter reports the statistical analysis of circuit-level FET high-speed performance in 65-nm silicon-on-insulator CMOS technology. Practical performance metrics are derived from full 300-mm wafer measurements. The proposed circuit-level layout wiring parasitics-aware FET reflects realistic FET that is placed in circuits. Its measurement and model are directly applicable to circuit design in conjunction with multiple layers of yield and manufacturability considerations. A stretched gate-pitch NFET design shows an average current gain cutoff frequency fT of 250 GHz, with 7.6% standard deviation, 6.7% mismatch standard deviation, and maximum fT of 307 GHz. The proposed characterization methodology will become more relevant to technologies beyond 65 nm.

This letter presents the first demonstration of a silicon-germanium heterojunction bipolar transistor (SiGe HBT) capable of operation above the one-half terahertz (500 GHz) frequency. An extracted peak unity gain cutoff frequency (f/sub T/) of 510 GHz at 4.5 K was measured for a 0.12/spl times/1.0 /spl mu/m/sup 2/ SiGe HBT (352 GHz at 300 K) at a breakdown voltage BV/sub CEO/ of 1.36 V (1.47 V at 300 K), yielding an f/sub T//spl times/BV/sub CEO/ product of 693.6 GHz-V at 4.5 K (517.4 GHz-V at 300 K).

We show empirical results that demonstrate the effect of high performance SiGe HBT design parameters on the minimum gate delay of an ECL ring oscillator. SiGe HBT devices with a high f/sub MAX/ (338 GHz) and a low f/sub T/ (180 GHz) achieve a minimum delay of 3.9 ps, which to our knowledge is the lowest reported delay for a silicon based logic gate. Compared to the extracted (extrapolated) f/sub T/ and f/sub MAX/, a simple figure of merit proportional to /spl radic/f/sub T//R/sub B/C/sub CB/ with R/sub B/ and C/sub CB/ extracted from S-parameter measurement is best correlated to the minimum gate delay.

This paper reports on SiGe NPN HBTs with unity gain cutoff frequency (f/sub T/) of 207 GHz and an f/sub MAX/ extrapolated from Mason's unilateral gain of 285 GHz. f/sub MAX/ extrapolated from maximum available gain is 194 GHz. Transistors sized 0.12/spl times/2.5 /spl mu/m/sup 2/ have these characteristics at a linear current of 1.0 mA//spl mu/m (8.3 mA//spl mu/m/sup 2/). Smaller transistors (0.12/spl times/0.5 /spl mu/m/sup 2/) have an f/sub T/ of 180 GHz at 800 /spl mu/A current. The devices have a pinched base sheet resistance of 2.5 k/spl Omega//sq. and an open-base breakdown voltage BV/sub CEO/ of 1.7 V. The improved performance is a result of a new self-aligned device structure that minimizes parasitic resistance and capacitance without affecting f/sub T/ at small lateral dimensions.

A record 210-GHz f/sub T/ SiGe heterojunction bipolar transistor at a collector current density of 6-9 mA//spl mu/m/sup 2/ is fabricated with a new nonself-aligned (NSA) structure based on 0.18 /spl mu/m technology. This NSA structure has a low-complexity emitter and extrinsic base process which reduces overall thermal cycle and minimizes transient enhanced diffusion. A low-power performance has been achieved which requires only 1 mA collector current to reach 200-GHz f/sub T/. The performance is a result of narrow base width and reduced parasitics in the device. Detailed comparison is made to a 120-GHz self-aligned production device.