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3.9 ps SiGe HBT ECL Ring Oscillator and Transistor Design for Minimum Gate Delay.

3.9 ps SiGe HBT ECL Ring Oscillator and Transistor Design for Minimum Gate Delay.

Authors :
Jagannathan, Basanth
Meghelli, Mounir
Chan, Kevin
Jae-Sung Rieh
Schonenberg, Kathryn
Ahlgren, David
Subbanna, Seshadri
Freeman, Greg
Source :
IEEE Electron Device Letters; May2003, Vol. 24 Issue 5, p324, 3p, 4 Graphs
Publication Year :
2003

Abstract

We show empirical results that demonstrate the effect of high performance SiGe HBT design parameters on the minimum gate delay of an ECL ring oscillator. SiGe HBT devices with a high f[sub MAX] (338 GHz) and a low f[sub T] (180 GHz) achieve a minimum delay of 3.9 ps, which to our knowledge is the lowest reported delay for a silicon based logic gate. Compared to the extracted (extrapolated) f[sub T] and f[sub MAX], a simple figure of merit proportional to √f[sub T]/R[sub B]C[sub CB] with R[sub B] and C[sub CB] extracted from S-parameter measurement is best correlated to the minimum gate delay. [ABSTRACT FROM AUTHOR]

Details

Language :
English
ISSN :
07413106
Volume :
24
Issue :
5
Database :
Complementary Index
Journal :
IEEE Electron Device Letters
Publication Type :
Academic Journal
Accession number :
10344992
Full Text :
https://doi.org/10.1109/LED.2003.812568