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An optical non-destructive method to check the existence of the parasitic Ge0.94Si0.06 channel underneath vertically stacked Ge0.91 Sn0.09 channels by infrared illumination is investigated. The 1310-nm and 1550-nm infrared light excite the electron-hole pairs in both the stacked floating channels and parasitic channel. On the other hand, the 2000-nm infrared light generates photo-excited carriers in the floating GeSn channels, but not in the parasitic GeSi channel since the photon energy is lower than the bandgap of Ge0.94 Si0.06. The main infrared responses of the floating channels and parasitic channel are the threshold voltage shift and the photocurrent, respectively. In addition, the distinct photoresponses of the stacked channels and parasitic channel are further confirmed by transistors without floating channels. The mechanisms behind the infrared responses are proposed. The existence of the parasitic channel can be detected by the infrared response for the advanced technology nodes, where the presence of the parasitic channel is not desired for performance enhancement and power reduction.

Fully compressively strained GeSn quantum-well channels sandwiched by Ge sacrificial layers on 200-mm silicon-on-insulator (SOI) wafers are grown using chemical vapor deposition. The transmission electron microscopy images indicate that dislocations are confined near the relaxed Ge buffer/SOI interface, resulting in low defect densities in the stacked GeSn channels. The top Ge cap is essential to ensure that the top GeSn channel matches the other two channels during the Ge etching. Channel release is obtained by etching of the Ge sacrificial layers with optimum ultrasonic-assisted H2O2. The low thermal budget gate-stack (400 °C) and S/D parasitic resistance reduction are achieved. The first stacked 3-Ge0.93Sn0.07-channel p-gate-all-around FET with ${L} _{\text {CH}}= 60$ nm has a record high ${I}_{ \mathrm{\scriptscriptstyle ON}}=1975~\mu \text{A}/\mu \text{m}$ (per channel width) at ${V}_{\text {OV}}={V}_{\text {DS}}=-1$ V, among all GeSn pFETs. The junctionless device structure is used to simplify the process.

The phosphorus incorporation by chemical vapor deposition and activation by laser annealing reaches the electron concentration of $\sim 3\times 10^{20}$ cm $^{-3}$ . The pulsed laser not only activates the phosphorus but also produces the biaxial tensile strain of 0.35%. With the nickel germanide contact, the specific contact resistivity reaches as low as $1.5\times 10^{-8}~\Omega $ -cm2 by greatly reducing the tunneling distance. Due to 4% misfit between Ge and Si, there are still misfit dislocations near the Ge/Si interface. The misfit dislocations at the Ge/Si interface lead to the ideality factor of 1.6 for the Ge/Si hetero-junction diode with ON/OFF ratio of $\sim 1\times 10^{5}$ .