107 results on '"Integrated circuits -- Intellectual property"'
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52. Researchers Submit Patent Application, 'Flex Circuit And Electrical Communication Assemblies Related To Same', for Approval (USPTO 20220140514)
53. Patent Issued for Apparatus for an inductor disposed in a band for method of heat dispersion (USPTO 11317545)
54. 'Crystal Resonator, And Integrated Structure Of Control Circuit And Integration Method Therefor' in Patent Application Approval Process (USPTO 20220085785)
55. Researchers Submit Patent Application, 'Probes For Testing Integrated Electronic Circuits And Corresponding Production Method', for Approval (USPTO 20220026466)
56. Patent Application Titled 'Substrate and Method for Producing the Substrate' Published Online (USPTO 20220024188)
57. 'Semiconductor Package Including Semiconductor Chips And Dummy Pad' in Patent Application Approval Process (USPTO 20220013497)
58. Patent Issued for Multi-chip packaging of integrated circuits and flow cells for nanopore sequencing (USPTO 11193922)
59. Patent Application Titled 'Integrated Circuit Device' Published Online (USPTO 20210384093)
60. Patent Issued for Integrated circuit including clubfoot structure conductive patterns (USPTO 11152392)
61. 'Integrated Biplane Optical Sensing Core Chip' in Patent Application Approval Process (USPTO 20210325602)
62. Researchers Submit Patent Application, 'Semiconductor Package With Barrier Layer', for Approval (USPTO 20210225772)
63. 'Integrated circuit substrate having a recess for receiving a solder fillet' in Patent Application Approval Process (USPTO 20210195734)
64. Patent Issued for Inductive Connection Structure For Use In An Integrated Circuit (USPTO 10,991,654)
65. Researchers Submit Patent Application, 'Cooling Structural Body, Cooling System, Heat Generator And Construction', for Approval (USPTO 20210108868)
66. Patent Application Titled 'Intelligent Power Module Containing Igbt And Super-Junction Mosfet' Published Online (USPTO 20210098448)
67. Patent Issued for Privacy-Preserving, Mutual PUF-Based Authentication Protocol (USPTO 10,956,557)
68. Patent Application Titled 'High-Voltage Analog Circuit Pulser And Pulse Generator Discharge Circuit' Published Online (USPTO 20210038282)
69. Patent Issued for Hybrid Silicon Lasers On Bulk Silicon Substrates (USPTO 10,910,792)
70. Researchers Submit Patent Application, 'Integrated Circuit Including Clubfoot Structure Conductive Patterns', for Approval (USPTO 20210013230)
71. Patent Issued for Semiconductor Integrated Circuit Device (USPTO 10,886,220)
72. Patent Application Titled 'Semiconductor Device Having Asymmetrical Source/Drain' Published Online (USPTO 20200279919)
73. Patent Issued for Integrated Thermoplastic Chip For Rapid PCR And HRMA (USPTO 10,710,083)
74. Patent Issued for Semiconductor Device Having Asymmetrical Source/Drain (USPTO 10,658,463)
75. Patent Issued for IC Die Having Patterned Seal Rings (USPTO 10,622,317)
76. 'Semiconductor Integrated Circuit Device' in Patent Application Approval Process (USPTO 20190385945)
77. Patent Issued for Integrated Circuit Physically Unclonable Function (USPTO 10,103,733)
78. 'Integrated Circuit Comprising Adjustable Back Biasing of One Or More Logic Circuit Regions' in Patent Application Approval Process (USPTO 20180183440)
79. Researchers Submit Patent Application, 'Self-Aligned Silicon Germanium Finfet with Relaxed Channel Region', for Approval (USPTO 20180158945)
80. 'Gate All around Vacuum Channel Transistor' in Patent Application Approval Process (USPTO 20180097118)
81. Patent Application Titled 'Semiconductor Chip and Stacked Semiconductor Package Having the Same' Published Online (USPTO 20180040588)
82. Researchers Submit Patent Application, 'Reliability Enhancement Methods for Physically Unclonable Function Bitstring Generation', for Approval (USPTO 20170364709)
83. 'Semiconductor Integrated Circuit Device' in Patent Application Approval Process (USPTO 20170317065)
84. 'Extracorporeal Circuit Blood Chamber Having an Integrated Deaeration Device' in Patent Application Approval Process (USPTO 20170173243)
85. Patent Application Titled 'Layered Structure of a P-Tfet' Published Online (USPTO 20160104769)
86. Patent Issued for Conductive Bump, Semiconductor Chip and Stacked Semiconductor Package Using the Same (USPTO 9312232)
87. Researchers Submit Patent Application, 'Semiconductor Device', for Approval (USPTO 20150348946)
88. Researchers Submit Patent Application, 'placement of Monolithic Inter-tier Vias (MIVs) within Monolithic Three Dimensional (3d) Integrated Circuits (ICs) (3DICs) Using Clustering to Increase Usable Whitespac', for Approval (uspto 20150333005)
89. 'Conducted Type Current Probe' in Patent Application Approval Process (USPTO 20150268272)
90. Patent Application Titled 'Conductive Bump, Semiconductor Chip and Stacked Semiconductor Package Using the Same' Published Online (USPTO 20150243619)
91. Patent Application Titled 'Integrated Circuit for Satellite Signal Reception' Published Online
92. 'Semiconductor Device' in Patent Application Approval Process
93. Patent Issued for Semiconductor Chip and Stacked Semiconductor Package Having the Same
94. Patent Application Titled 'Integrated Circuit Packaging System with Routable Grid Array Lead Frame' Published Online
95. 'Integrated Circuit Packaging System with Transferable Trace Lead Frame' in Patent Application Approval Process
96. Patent Issued for Interface Circuit and Main Device
97. Patent Issued for Structure for MOSFET Sensor
98. Patent Application Titled 'Conductive Bump, Semiconductor Chip and Stacked Semiconductor Package Using the Same' Published Online
99. Agency Reviews Patent Application Approval Request for 'Interface Circuit and Main Device'
100. Researchers Submit Patent Application, 'Semiconductor Chip and Stacked Semiconductor Package Having the Same', for Approval
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