3,819 results on '"Integrated circuits -- Intellectual property"'
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2. Researchers Submit Patent Application, 'Integrated Circuit Workload, Temperature, And/Or Sub-Threshold Leakage Sensor', for Approval (USPTO 20240418770)
3. Researchers Submit Patent Application, 'Inverted Gate Cut Region', for Approval (USPTO 20240420959)
4. Researchers Submit Patent Application, 'Integrated Thermal Bridges On Wirebond Assembled Integrated Circuits For Heat Spreading', for Approval (USPTO 20240421092)
5. Patent Issued for Surge protection in semiconductor integrated circuit and semiconductor memory device (USPTO 12170440)
6. Patent Issued for Microprocessor with a time counter for statically dispatching extended instructions (USPTO 12169716)
7. Patent Application Titled 'Semiconductor Devices With Different Gate Dielectric Thicknesses' Published Online (USPTO 20240421209)
8. Patent Application Titled 'Reduction of Air Gaps in FinFET Structures' Published Online (USPTO 20240420998)
9. 'Semiconductor Package' in Patent Application Approval Process (USPTO 20240421143)
10. 'Recess Poly Esd Diode For Power Mosfet' in Patent Application Approval Process (USPTO 20240421147)
11. Researchers Submit Patent Application, 'Multilayer Moisture Repelling Films For Front End Fet Applications', for Approval (USPTO 20240413098)
12. Researchers Submit Patent Application, 'Heat Radiation Devices', for Approval (USPTO 20240413053)
13. Researchers Submit Patent Application, 'Memory Structure', for Approval (USPTO 20240412772)
14. Patent Application Titled 'Semiconductor Memory Devices Having Enhanced Sub-Word Line Drivers Therein' Published Online (USPTO 20240412773)
15. 'Contact Assembly For Power Semiconductor Chips And Power Electronics Module' in Patent Application Approval Process (USPTO 20240413119)
16. Researchers Submit Patent Application, 'Integrated Circuit With Supply Voltage Detector', for Approval (USPTO 20240405538)
17. Patent Application Titled 'Semiconductor Integrated Circuit, System On Chip And Electronic Device To Implement Them' Published Online (USPTO 20240405011)
18. Researchers Submit Patent Application, 'Structure To Reduce Chip Shift During Assembly', for Approval (USPTO 20240395758)
19. Patent Application Titled 'Stacked Hybrid Tfet And Mosfet' Published Online (USPTO 20240395814)
20. Patent Application Titled 'Semiconductor Chip And Semiconductor Package Including Same' Published Online (USPTO 20240395672)
21. Patent Application Titled 'Integrated Circuit' Published Online (USPTO 20240397709)
22. 'Semiconductor Chip' in Patent Application Approval Process (USPTO 20240395944)
23. Patent Issued for Semiconductor device (USPTO 12148716)
24. Patent Application Titled 'Bellows For Immersion Cooling' Published Online (USPTO 20240389268)
25. Patent Application Titled 'Integrated Circuit Device And Electronic System Including The Same' Published Online (USPTO 20240389325)
26. Researchers Submit Patent Application, 'Photonic Waveguide Power And Phase Monitor', for Approval (USPTO 20240385243)
27. 'Clustering Clock Chain Data For Test-Time Reduction' in Patent Application Approval Process (USPTO 20240385241)
28. Researchers Submit Patent Application, 'Semiconductor Device', for Approval (USPTO 20240381617)
29. Researchers Submit Patent Application, 'Four-Terminal Resistance Testing Structure', for Approval (USPTO 20240379472)
30. Patent Application Titled 'Wafer Chip Scale Package' Published Online (USPTO 20240379597)
31. Patent Application Titled 'Semiconductor Package' Published Online (USPTO 20240379575)
32. Patent Application Titled 'Semiconductor Device Including Buried Word Line' Published Online (USPTO 20240381614)
33. Patent Application Titled 'Integrated Circuit Metal Gate Structure' Published Online (USPTO 20240379811)
34. 'Semiconductor Packages And Substrates For Packages' in Patent Application Approval Process (USPTO 20240379524)
35. 'Semiconductor Device Including Buried Word Line' in Patent Application Approval Process (USPTO 20240381615)
36. 'Heat-Dissipating Wirebonded Members On Package Surfaces' in Patent Application Approval Process (USPTO 20240379509)
37. 'Electronic Component Appliques' in Patent Application Approval Process (USPTO 20240381536)
38. Patent Application Titled 'Compact Balanced Integrated Circuit Amplifier' Published Online (USPTO 20240372518)
39. 'Multi-Node, Multi-Stream Photonic Integrated Circuit-Based Free-Space Optical Communication Device' in Patent Application Approval Process (USPTO 20240372623)
40. Researchers Submit Patent Application, 'Treatment Of Sidewall Of Tunnel Barrier Junction', for Approval (USPTO 20240365673)
41. Researchers Submit Patent Application, 'Semiconductor Processing Using a Two-Dimensional Polymer', for Approval (USPTO 20240363333)
42. Researchers Submit Patent Application, 'Semiconductor Devices', for Approval (USPTO 20240363712)
43. Researchers Submit Patent Application, 'Interface circuit and memory controller', for Approval (USPTO 20240361919)
44. Researchers Submit Patent Application, 'Integrated Circuits With Conductive Posts Having Rough Sidewalls', for Approval (USPTO 20240363570)
45. Researchers Submit Patent Application, 'Integrated Circuit With Improved Isolation', for Approval (USPTO 20240363394)
46. Patent Issued for Semiconductor device (USPTO 12132013)
47. Patent Application Titled 'Transfer Printing Micro-Components From Carrier Substrates' Published Online (USPTO 20240363800)
48. Patent Application Titled 'Mram With Asymmetric Structure' Published Online (USPTO 20240365675)
49. Patent Application Titled 'Efficient Redistribution Layer Topology For High-Power Semiconductor Packages' Published Online (USPTO 20240363462)
50. Researchers Submit Patent Application, 'Integrated Circuit Degradation Estimation And Time-Of-Failure Prediction Using Workload And Margin Sensing', for Approval (USPTO 20240353476)
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