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A new approach to reducing the source resistance in InP-based InAlAs-InGaAs enhancement-mode HEMTs is developed using Pt-based buried-gate technology. Source resistance as small as 0.2 Omega mm is obtained, which results in an excellent transconductance of 1170 mS/mm for a 0.5 mu m long gate enhancement-mode HEMT.

A tapered slot antenna, the taper section of which is shaped according to a hyperbolic tangent (tanh) function, is proposed. Characteristics of the antenna are experimentally compared with those of a conventional linearly tapered slot antenna (LTSA). The radiation patterns of the proposed antenna measured at 125 GHz exhibit lower sidelobe levels than those of the LTSA in both the E- and H-planes.

A single-pole four-throw (SP4T) switch IC with a 3 dB bandwidth of over 50 GHz, which is believed to be the highest among cold-FET SP4T switches, is presented. A miniature and ideal divergence structure with an advanced four-level interconnect provides highly uniform performance in different paths.

Record extrinsic transconductance (g/sub m//sup ext/) of 3 S/mm at room temperature for an InP-based high electron mobility transistor with an In/sub 0.53/Ga/sub 0.47/As/InAs composite channel is reported. Markedly enhanced g/sub m//sup ext/ was achieved by reducing a gate-to-channel distance for improving intrinsic transconductance and a gate-to-ohmic distance for minimising series source resistance.

A high-speed low-power decision circuit using InP/InGaAs double-heterojunction bipolar transistors (DHBTs) has been successfully designed and fabricated. The DHBTs exhibit a cutoff frequency fT and maximum oscillation frequency fmax of 232 and 360 GHz, respectively, at a collector current density of 2.5 mA/µm2. To boost the operating speed, a novel master–slave D-type flip-flop (MS-DFF) was used. Up to 90 Gbit/s operation was achieved with low power consumption of 0.5 W. These results demonstrate that InP-based DHBTs are attractive for making ultra-high-performance ICs for future optical communications systems operating at bit rates of 100 Gbit/s or more.

An InAlAs/InGaAs/InP HEMT distributed baseband amplifier IC that uses a new loss compensation technique for the drain artificial line is described. The amplifier IC has a gain of 10 dB with a 0-90 GHz bandwidth. This is the widest bandwidth among all reported baseband ICs to date.< >

A series-connected voltage-balancing circuit can output more than twice the voltage amplitude that can be output by a single transistor. This circuit makes it possible to apply high-speed low-breakdown-voltage transistors to large-voltage-amplitude pulse drivers. The first operation of this type of driver at 10 Gbit/s is reported.

An InP HBT 1:4 demultiplexer IC with a multiphase clock architecture is described that reduces the number of circuit elements and power consumption while maintaining operating speed. The IC operated at 50 Gbit/s with 1.17 W power consumption at a supply voltage of −4.5 V. Compared to an IC with a conventional tree-type architecture using the same InP HBTs, the power consumption is less than half while the operating speed of 50 Gbit/s is maintained.

A low-power 16:1 multiplexer (MUX) IC using undoped-emitter InP/InGaAs heterojunction bipolar transistors (HBTs) has been successfully designed and fabricated. To minimise power consumption, the collector current density of each HBT was optimised taking into account the required operating speed and the number of fan-outs. Up to 47 Gbit/s error-free operation was confirmed with low power consumption of about 3.2 W. These results demonstrate that InP/InGaAs HBT technology is attractive for fabricating over 40 Gbit/s, low-power medium-scale-integration (MSI) circuits.

A new low-jitter dynamic decision circuit is designed and fabricated using InP/InGaAs HBTs. Cbc compensation transistors and semi-feed forward loads are adopted to eliminate waveform distortion and residual double trace, respectively. A fabricated decision IC achieves error-free operation and wide eye opening for 50 Gbit/s 231−1 PRBS with 0.68 W power dissipation. Its RMS and peak-to-peak jitter of output data are 0.59 and 4.1 ps, respectively.

The 100 Gbit/s multiplexing operation of a selector IC and the demultiplexing operation of a D-type flip-flop (D-FF) using a production-level 0.1 /spl mu/m-gate InP HEMT IC technology is described. Eye-openings of the selector IC at 100 Gbit/s and its error-free operation were confirmed using a test chip containing the selector and the D-FF. To the authors' best knowledge, this is the first report of 100 Gbit/s operation of a transistor-based integrated circuit.

A high-input-sensitivity, low-power decision circuit for 40 Gbit/s-class optical communications systems using InP/InGaAs double-heterojunction bipolar transistors (DHBTs) has been designed and fabricated. These DHBTs exhibit an fT of 131 GHz and an fmax of 191 GHz at a collector current density of 0.5 mA/µm2 and a collector-to-emitter voltage of 1.2 V. The decision circuit was operated at a data rate of up to 43 Gbit/s with a low power consumption of 0.7 W. A high input sensitivity of 50 mV and a wide clock phase margin of 201° at 43 Gbit/s were achieved.

A selector integrated circuit (IC) as a benchmark to assess the performances of new undoped-emitter InP/InGaAs heterojunction bipolar transistors (HBTs) has been designed and fabricated. Operation of the selector gate at 86 Gbit/s has been achieved using an HBT developed by the authors, which exhibits the fT of 140 GHz and fmax of 200 GHz at a collector current density of 50 kA/cm2. This indicates that InP/InGaAs HBTs have excellent speed performance for making ultra-high-speed ICs with data rates approaching 100 Gbit/s.

The authors describe an exclusive OR/NOR (XOR) IC which uses 0.1 /spl mu/m InAlAs-InGaAs-InP HEMTs for >40 Gbit/s optical transmission systems. To obtain high speed operation with small timing jitter, an inductor peaking technique is applied to a symmetrical XOR gate. The IC can operate at up to 80 Gbit/s, and can be used as a 40 GHz timing extraction circuit.

It is shown that the threshold-voltage uniformity of 0.1 µm InAlAs/InGaAs-based modulation-doped field-effect transistors with different numbers of gate fingers and different gate widths can be improved when a thin cap-layer structure is employed. This improvement is based on the reduction of the recess time. This reduction suppresses the difference in etching that results from the different etching rates caused by the different electrochemical effects that occur because of the varied gate layouts.

The RF performance of InP-based lattice-matched high electron mobility transistors (HEMTs) is improved by using a two-step-recess process. 0.07 µm gate HEMTs show a cutoff frequency (fT) of 300 GHz, a value previously achievable only with a gate length of 0.05 µm in the conventional gate structure, and a maximum frequency of oscillation fmax of 400 GHz. The high fT indicates that the effective gate length is successfully suppressed by the two-step-recessed gate structure. Moreover, owing to the selective etching property, this gate recess process provides high uniformity of the threshold voltage and the cutoff frequency of the HEMTs on a 3 in wafer.

The authors describe a 46 Gbits super-dynamic type decision circuit module that uses InAlAs/InGaAs HEMTs. At a data rate of 40 Gbit/s, the module shows an input data sensitivity of 104 mV/sub pp/ and a clock phase margin of 212.

The authors report a 2–46.5 GHz quasi-static frequency divider IC using InAlAs/InGaAs/InP HEMTs. Wideband clock/data buffers and an HLO (high-speed latching operation)-type T-FF were incorporated to enhance the operating range. The IC was mounted on a dedicated IC package and operated up to 45.2 GHz.

A 64 Gbit/s 2:1 selector-type multiplexer IC using InAlAs/InGaAs/InP HEMTs is reported. The record operating data rate was measured on a wafer. The IC was mounted on a dedicated IC package and operated beyond 52 Gbit/s.

A 40 Gbit/s, fully-integrated 1:2 demultiplexer IC using InAlAs/InGaAs/InP HEMTs is reported. The IC integrates the full functionality for 40 Gbit/s data and 40 GHz regenerated clock inputs, including output bit alignment.