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Ge has been considered as a promising candidate for the active region in optical interconnect applications such as lasers and photodetectors, since its band gap corresponds to a wavelength with less loss in SiO2 waveguides. However, to increase the efficiency of these applications, a direct band gap material is required. Incorporation of Sn into Ge has been considered to obtain a direct band gap material [1,2]. According to theoretical calculations [3], the critical Sn content to achieve the direct transition depends on the strain. When the GeSn layer is fully relaxed, around 11% of Sn is required. On the other hand, when the layer experiences compressive strain, the critical Sn content increases. One option to obtain highly strain-relaxed GeSn with high Sn content is to increase the thickness of the GeSn layer. In addition, the active region of the optical devices has to be thick to obtain a high efficiency. However, it is well known that Sn segregation to the surface easily occurs [4], which results in Sn precipitation/agglomeration on the surface when a thick layer is grown. The Sn agglomeration is the result of the collision among Sn atoms on the surface. Therefore, we focused on the freezing of Sn atoms during GeSn growth. GeSn layers were grown with Ge2H6 and SnCl4 precursors on Ge(001) substrates at 320°C by atmospheric CVD in an Epsilon like equipment from ASM. The target thickness of the GeSn layers is 200 nm. N2 and H2 with different flows ranging from 10 to 40 slm were used as carrier gases to study the impact of the partial pressure of the precursors on Sn agglomeration. It is expected that using low carrier gas flows enhances the Sn freezing due to the higher Ge2H6 and SnCl4 partial pressures. In addition, it is expected that switching the carrier gas from N2 to H2suppresses the Sn migration on the surface due to the resulting surface H-termination. We found opposite tendencies for the surface Sn agglomeration as a function of the H2 and N2 carrier gas flow. A lower N2 suppresses the surface Sn agglomeration. As we expected, a high partial pressure of the precursors enhances the freezing of Sn atoms into the subsurface. On the other hand, when H2 is used as a carrier gas, a higher H2 flow suppresses the surface Sn agglomeration. The growth temperature (320°C) is close to the temperature at which adsorbed H starts to desorb thermally from the Ge surface (340°C) [5, 6]. However, a high H2 partial pressure may suppress the desorption of surface H which is provided by the deposition by Ge2H6. The Sn segregation should be suppressed by the surfactant effect of surface H [6]. The different behavior of these two carrier gases will be discussed in detail. [1] D. W. Jenkins and J. D. Dow, Phys. Rev. B, 36, 7994 (1987). [2] M. R. Bauer, et al., Solid State Commun. 127, 355 (2003). [3] Y. Shimura, et al., J. Appl. Phys. submitted. [4] E. Kasper, et al., Thin Solid Films, 520, 3195 (2012). [5] L. Surnev and M. Tikhov, Surf. Sci. 138, 40 (1984). [6] A. Sakai and T. Tatsumi, Appl. Phys. Lett. 64, 52 (1994).

The effective passivation of germanium surfaces and interfaces has been claimed to be the key to a substantial progress in developing Ge-based microelectronic devices. This paper compares the currently most promising passivation routes, i.e. oxidation and sulfidation, focusing on the underlying atomic scale processes and highlighting similarities and discrepancies between both approaches. The effect of oxidation and sulfidation on electrically active defects is addressed, and the chemical and structural properties of the passivated surfaces are described in detail.

In this paper, we reports our recent studies of the electrical and crystalline properties of heteroepitaxial Ge1-xSnx layers with various Sn content of 0~25%. We examined Ga-doping in strained Ge1-xSnx layers for developing source/drain stressor in CMOS applications and investigated the effect of Sn on the doping profile. The impact of Sn on carrier properties has been also studied with the Hall measurement of Ge1-xSnx/SOI structures. Also, we achieved the epitaxial growth of Ge1-xSnx layers with a Sn content as high as 25% on InP considering misfit between the epitaxial layer and substrate.

In this paper, we propose the fabrication of whole strained Ge complementary metal-oxide-semiconductor (CMOS) with Ge1-xSnx materials as embedded stressors to outperform the state-of-the-art strained Si CMOS. Ge1-xSnx materials have larger lattice constant than that of Ge, which can apply the strain into Ge channel region. Compatibility of Ge1-xSnx (with 2-8% Sn) materials with source/drain engineering processes (B implantation and activation, in situ Ga doping, and Ni(Ge1-ySny) formation) is characterized. A low thermal budget has been determined for those processes on Ge1-xSnx alloys: temperatures must be lower than 600{degree sign}C for B activation and lower than 450{degree sign}C for Ni(Ge1-ySny) formation.

High mobility channels are currently being explored to replace the Si channel in future technology nodes. However, until now the promising bulk properties are very difficult to translate into reality due to a bad passivation of the interface between the gate stack and the substrate. In this paper we want to emphasize that gate stack passivation is the result of a complex interplay between the surface treatment and the ALD deposition. During ALD deposition on GaAs, the removal of surface oxides is observed. However, this effect does not lead to a good passivation. For Ge, the S-passivation of the interface is studied in combination with different high-κ. It is clear that the Ge/S/Al2O3 interface is superior to the Ge/S/ZrO2 interface.

A new passivation approach integrating the III-V/Ge MOSFET gate stack processes for a complete CMOS solution is proposed. We explore the In0.53Ga0.47As and Ge MOS electrical properties and present the common gate stack (CGS) concept based on the complementary nature of the asymmetric oxide-In0.53Ga0.47As and the oxide-Ge interface state distributions. In addition, this approach requires neither the interfacial passivation layer (IPL) such as Si, nor the native oxide such as the GeO2, between the gate dielectric and the channels. The oxide-semiconductor interface properties of the common gate stack III-V/Ge MOS system have been carefully investigated and MOS transistors have been fabricated to validate the proposed common gate stack concept. It has been demonstrated that the above common gate stack MOS system can achieve high-performance n-channel operation on In0.53Ga0.47As substrates and p-channel operation on Ge substrates.

Using complementary surface analysis techniques, we have studied the chemical and structural properties of the S/Ge(100) passivation layer formed upon sulfidation in an aqueous (NH4)2S solution. Our experiments have revealed that only S-Ge bonds are formed upon the adsorption of S and that the surface is essentially free of other S-containing species (i.e. Sn or SOx). The passivation treatment was found to reduce, but not to fully inhibit Ge-O bonds on the surface. Moreover, we have shown that the top-layer of the passivated surface shows a high degree of disorder even though it is associated with a spotty (1x1) RHEED pattern. Based on our experimental findings, we conclude that the passivation layer can be best described as a thin amorphous GeSxOy film atop a partially ordered interfacial layer, a surface model that has been proposed previously in literature.