40 results on '"Martonosi A"'
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2. Modeling, Simulation, and Measurement
3. Optimizing Capacitance and Switching Activity to Reduce Dynamic Power
4. Conclusions
5. Introduction
6. Using Voltage and Frequency Adjustments to Manage Dynamic Power
7. Bibliography.
8. CHAPTER 5: Managing Static (Leakage) Power: 5.4 ARCHITECTURAL TECHNIQUES BASED ON VT.
9. CHAPTER 5: Managing Static (Leakage) Power: 5.3 ARCHITECTURAL TECHNIQUES USING THE DROWSY EFFECT.
10. CHAPTER 5: Managing Static (Leakage) Power: 5.2 ARCHITECTURAL TECHNIQUES USING THE STACKING EFFECT.
11. CHAPTER 5: Managing Static (Leakage) Power: 5.1 A QUICK PRIMERON LEAKAGE POWER.
12. CHAPTER 4: Optimizing Capacitance and Switching Activity to Reduce Dynamic Power: 4.13 DYNAMIC WORK STEERING.
13. CHAPTER 4: Optimizing Capacitance and Switching Activity to Reduce Dynamic Power: 4.12 VALUE-DEPENDENT SWITCHING ACTIVITY: BUS ENCODINGS.
14. CHAPTER 4: Optimizing Capacitance and Switching Activity to Reduce Dynamic Power: 4.11 SPECULATIVE ACTIVITY.
15. CHAPTER 4: Optimizing Capacitance and Switching Activity to Reduce Dynamic Power: 4.10 CACHEABLE SWITCHING ACTIVITY.
16. CHAPTER 4: Optimizing Capacitance and Switching Activity to Reduce Dynamic Power: 4.9 PARALLEL SWITCHING-ACTIVITY INSET-ASSOCIATIVE CACHES.
17. CHAPTER 4: Optimizing Capacitance and Switching Activity to Reduce Dynamic Power: 4.8 IDLE-CAPACITY SWITCHING ACTIVITY: CACHES.
18. CHAPTER 4: Optimizing Capacitance and Switching Activity to Reduce Dynamic Power: 4.6 IDLE-CAPACITY SWITCHING ACTIVITY: INSTRUCTION QUEUE.
19. CHAPTER 4: Optimizing Capacitance and Switching Activity to Reduce Dynamic Power: 4.4 IDLE-WIDTH SWITCHING ACTIVITY: CACHES.
20. CHAPTER 4: Optimizing Capacitance and Switching Activity to Reduce Dynamic Power: 4.2 IDLE-UNIT SWITCHING ACTIVITY: CLOCK GATING.
21. CHAPTER 4: Optimizing Capacitance and Switching Activity to Reduce Dynamic Power: 4.1 A ROAD MAP FOR EFFECTIVE SWITCHED CAPACITANCE.
22. CHAPTER 3: Using Voltage and Frequency Adjustments to Manage Dynamic Power: 3.5 HARDWARE-LEVEL DVFS.
23. CHAPTER 3: Using Voltage and Frequency Adjustments to Manage Dynamic Power: 3.4 PROGRAM-LEVEL DVFS FOR MULTIPLE-CLOCK DOMAINS.
24. CHAPTER 3: Using Voltage and Frequency Adjustments to Manage Dynamic Power: 3.2 SYSTEM-LEVEL DVFS.
25. CHAPTER 3: Using Voltage and Frequency Adjustments to Manage Dynamic Power: 3.1 DYNAMIC VOLTAGE AND FREQUENCY SCALING: MOTIVATION AND OVERVIEW.
26. CHAPTER 2: Modeling, Simulation, and Measurement: 2.4 MEASUREMENT.
27. Glossary.
28. CHAPTER 6: Conclusions: 6.2 DYNAMIC POWER REDUCTIONS BASED ON EFFECTIVE CAPACITANCE AND ACTIVITY FACTOR: STATUS AND FUTURE TRENDS.
29. CHAPTER 1: Introduction: 1.2 CMOS POWER CONSUMPTION: AQUICK PRIMER.
30. CHAPTER 1: Introduction: 1.4 THIS BOOK.
31. CHAPTER 6: Conclusions: 6.4 FINAL SUMMARY.
32. CHAPTER 6: Conclusions: 6.1 DYNAMIC POWER MANAGEMENT VIA VOLTAGE AND FREQUENCY ADJUSTMENT: STATUS AND FUTURE TRENDS.
33. CHAPTER 2: Modeling, Simulation, and Measurement: 2.3 POWER SIMULATION.
34. CHAPTER 1: Introduction: 1.3 POWER-AWARE COMPUTING TODAY.
35. CHAPTER 1: Introduction: 1.1 BRIEF HISTORY OF THE "POWER PROBLEM".
36. CHAPTER 6: Conclusions: 6.3 LEAKAGE POWER REDUCTIONS: STATUS AND FUTURE TRENDS.
37. CHAPTER 6: Conclusions.
38. CHAPTER 2: Modeling, Simulation, and Measurement: 2.5 SUMMARY.
39. CHAPTER 1: Introduction.
40. Acknowledgements.
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