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CHAPTER 4: Optimizing Capacitance and Switching Activity to Reduce Dynamic Power: 4.2 IDLE-UNIT SWITCHING ACTIVITY: CLOCK GATING.
- Source :
- Computer Architecture Techniques for Power-Efficiency; 2008, p51-58, 8p
- Publication Year :
- 2008
Details
- Language :
- English
- ISBNs :
- 9781598292091
- Database :
- Complementary Index
- Journal :
- Computer Architecture Techniques for Power-Efficiency
- Publication Type :
- Book
- Accession number :
- 99265958
- Full Text :
- https://doi.org/10.2200/S00119ED1V01Y200805CAC004