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One of the pandemics that have caused many deaths is the Coronavirus disease 2019 (COVID-19). It first appeared in late 2019, and many deaths are increasing day by day until now. Therefore, the early diagnosis of COVID-19 has become a salient issue. Additionally, the current diagnosis methods have several demerits, and a new investigation is required to enhance the diagnosis performance. In this paper, a set of phases are performed, such as collecting data, filtering and augmenting images, extracting features, and classifying ECG images. The data were obtained from two publicly available ECG image datasets, and one of them contained COVID ECG reports. A set of preprocessing methods are applied to the ECG images, and data augmentation is performed to balance the ECG images based on the classes. A deep learning approach based on a convolutional neural network (CNN) is performed for feature extraction. Four different pre-trained models are applied, such as Vgg16, Vgg19, ResNet-101, and Xception. Moreover, an ensemble of Xception and the temporary convolutional network (TCN), which is named ECGConvnet, is proposed. Finally, the results obtained from the former models are fed to four main classifiers. These classifiers are softmax, random forest (RF), multilayer perception (MLP), and support vector machine (SVM). The former classifiers are used to evaluate the diagnosis ability of the proposed methods. The classification scenario is based on fivefold cross-validation. Seven experiments are presented to evaluate the performance of the ECGConvnet. Three of them are multi-class, and the remaining are binary class diagnosing. Six out of seven experiments diagnose COVID-19 patients. The aforementioned experimental results indicated that ECGConvnet has the highest performance over other pre-trained models, and the SVM classifier showed higher accuracy in comparison with the other classifiers. The resulting accuracies from ECGConvnet based on SVM are (99.74%, 98.6%, 99.1% on the multi-class diagnosis tasks) and (99.8% on one of the binary-class diagnoses, while the remaining achieved 100%). It is possible to develop an automatic diagnosis system for COVID based on deep learning using ECG data. [ABSTRACT FROM AUTHOR]

This paper proposes a digital morphological filtering method based on a novel structuring element (SE) formulated using fractional Fourier transform (FrFT) and cross-convolution of window functions. The highlighting feature of this newly formulated filter is its flexibility in adding an adaptive nature to classical morphological filtering. Until now, every method listed in the literature makes a convenient assumption that noises corrupting ECG signal are Gaussian and model the filter around this assumption. Addressing this shortcoming, the first-of-its-kind filter adopts the α -stable distribution model (of which Gaussian distribution is a special case) of noise to better replicate the real-time noises interfering with ECG signals. The designed filter can suppress the noise and adapt to the changes in ECG signal morphology for better reconstruction. The proposed filter is tested on MIT-BIH Arrhythmia Database. The simulation results show improved performance in several quantitative metrics, demonstrating the superiority of our suggested method over the currently used state-of-the-art techniques. [ABSTRACT FROM AUTHOR]

This work describes the log-MAP (BCJR) algorithm implementation of a close to capacity dirty paper coding CODEC. The CODEC consists of eight deep pipeline processors. It decodes blocks of 975 bits in 26.9 ms using less than 9.7% of low-cost FPGA (and no DSP blocks). Two pipelines, for alpha and beta, calculate the values of gamma (of the BCJR) to reduce the storage requirements. The final log-likelihood ratio (LLR) is calculated together with alpha, reusing intermediate results. The number of bits used by the different signals of the processor is easily configurable. It was set to six bits to the channel measure signals and eight bits to log of probability signals like alpha, beta, and others. The CODEC clock was 100 MHz. The achieved bit rate is 36.2 Kbps per CODEC, but multiple CODECs can be fit into a single chip. The CODEC is 3.49 dB from the channel capacity. [ABSTRACT FROM AUTHOR]

The article announces the recipients of the Best Paper Awards for 2022 in the journal Circuits, Systems & Signal Processing. The awards were established in 2013 and nominations were invited from Associate Editors and readers of the journal. A Selection Committee was formed to choose the best papers in different categories. The recipients of the Armen H. Zemanian Best Paper Award for Circuits and Systems are Sudip Ghosh, Yuvam Bateja, Joshua Roy Palathinkal, and Hafizur Rahaman. The recipients of the Sydney R. Parker Best Paper Award for Signal Processing are N. Ramesh Babu, K. Sanjay, and P. Balasubraminam. The paper by Babu et al. was also chosen for the M.N.S. Swamy Best Paper Award. Each awardee will receive a certificate and cash prize. The Editor-in-Chief congratulates the winners and thanks the nominators and Selection Committee for their contributions. [Extracted from the article]

In this paper, a quasi-time-dependent (QTD) H ∞ filtering approach to discrete-time two-dimensional switched systems is presented, by applying the mode-dependent persistent dwell-time (MPDT) switching method. The Fornasini–Marchesini local state-space model is used to describe the interested system. Compared with the dwell-time and the average dwell-time switchings which are often used in the literature, a MPDT switching, which is a more general class of switching form, is studied in this paper. The objective is to design a full-order filter that ensures the filtering error system exponentially stable with a guaranteed H ∞ noise attenuation performance. By constructing a QTD switched Lyapunov-like function, the sufficient conditions for the existence of the filter are established by using the MPDT switching. The time-independent filter is actually a special case of QTD filter studied in this paper, which implies the developed results in this paper are more general with less conservativeness. Finally, two numerical examples are showed to validate the effectiveness and potential of the developed filter design method. [ABSTRACT FROM AUTHOR]

This article considers the problem of finite-time command-filtered control for switched nonlinear systems with input quantization and output constraints. The unmeasurable state is estimated by designing a switched state observer. During the design process, to overcome the chattering problem effectively, the hysteresis quantization is designed as two bounded nonlinear functions. Furthermore, in order to restrict the output to an expected range, the barrier Lyapunov function approach is introduced. The "explosion of complexity" and the error compensation problems in the backstepping design are solved by using a finite-time command-filtered approach. A first-order Levant differentiator is used instead of the general command filter in this paper, which can not only filter the intermediate signals accurately to get the differential signals, but also ensure the finite-time stability of the filter. Stability of the closed-loop system in the sense of semi-global practical finite-time stability (SGPFS) is proved by exploring a multiple Lyapunov functions approach. Finally, a simulation example is provided to verify the validity of the presented control method. [ABSTRACT FROM AUTHOR]

A call for nominations for these awards was sent out to all the Associate Editors inviting them to nominate those papers published in 2020 or 2021 in CSSP, which should be considered for these awards. This call was also posted on the CSSP Website inviting nominations from CSSP readers. During 2013, Birkhäuser (Springer) instituted three Best Paper Awards for papers published in Circuits, Systems and Signal Processing (see the announcement in the October 2013 issue of CSSP). [Extracted from the article]

The paper proposes a smart method to remove network nodes that are highly prone to impulse noise and replacing them with a linear combination of existing more reliable nodes. This is done to reduce communication cost. To reduce the communication cost in a network, a common way is to remove some nodes randomly and then replace the intermediate estimation of these nodes by the corresponding node estimation. In this direction, the contribution of this paper is twofold. First, we suggest to remove the nodes smartly by omitting the unreliable nodes prone to impulsive noise. This is done by computing the disturbance induced in the adaptation step of the diffusion least mean square. Second, we replace the estimation of removing nodes by a linear combination of existing estimations of reliable nodes instead of just replacing by the estimation of the corresponding node. Also, the coefficients of linear combination are optimized based on the minimum disturbance principle. Furthermore, the minimum achievable disturbance is calculated mathematically and a necessary and sufficient condition for stability of the proposed algorithm is presented. Finally, the simulation results show the efficiency of the proposed method in comparison with some state-of-the-art algorithms. [ABSTRACT FROM AUTHOR]

The recipient for the I Sydney R. Parker Best Paper Award, i given for the best paper published in 2020 in the area of Signal Processing is M. Elhoseny for his paper "Multi-object Detection and Tracking (MODT) Machine Learning Model for Real-Time Video Surveillance Systems" published in the February 2020 issue, pp. 611-630. A call for nominations for these awards was sent out to all the Associate Editors, inviting them to nominate those papers published in 2019 or 2020 in CSSP, which should be considered for these awards. During 2013, Birkhäuser (Springer) instituted three Best Paper Awards for papers published in Circuits, Systems and Signal Processing (see the announcement in the October 2013 issue of CSSP). [Extracted from the article]

This paper proposes a carbon nanotube FET (CNFET)-based ultra-low-power dual- V DD ternary half adder (HA) circuit. The proposed design utilizes both the available ternary power supply voltages ( V DD & V DD / 2 ) and prevents direct path between the power supplies and ground, thus significantly reducing the power dissipation as compared to the conventional designs. The performance of the proposed CNFET dual- V DD HA has been compared with the same circuit implemented with 45 nm MOSFETs and also with other CNFET-based state-of-the-art HA designs proposed in the literature. The proposed HA consumes merely 86 nW of power which is significantly lesser (66–90% lower) than the power required by other ternary HA designs, and also exhibits 69–91% lower delays. The overall PDP of the proposed HA circuit is merely 4–11% of the PDP of corresponding CMOS ternary HA and other benchmarked CNFET HA designs. [ABSTRACT FROM AUTHOR]

In this paper, we propose a general purpose, simple and fast fusion algorithm based on guided image filter. The proposed method can well combine useful source image information into the fused image supported by multi-scale image decomposition, structure transferring property, visual saliency detection, and weight map construction. Multi-scale image decomposition is appropriate to represent and manipulate image features at various scales. Structure transferring property enabled by our algorithm can induce structures of one source image into the other. A new visual saliency detection based on guided image filter introduced in this paper is able to extract significant regions from visually different images of the same scene. The choice of weight maps helped to integrate the complementary information pixel by pixel at each scale. Experimental outcomes of the proposed method are compared and analyzed with traditional and recent guided image filter-based fusion algorithms in terms of visual quality, fusion metrics and run time. In addition, to enhance fusion results further we made an effort to find a suitable image and video enhancement algorithm. The fusion performance analysis clearly indicates that the proposed method is very promising along with less run time. [ABSTRACT FROM AUTHOR]

During 2013, Birkhäuser (Springer) instituted three Best Paper Awards for papers published in Circuits, Systems and Signal Processing (see the announcement in the October 2013 issue of CSSP). A call for nominations for these awards was sent out to all the Associate Editors inviting them to nominate those papers published in 2018 or 2019 in CSSP, which should be considered for these awards. The former paper was also chosen for the I M.N.S. Swamy Best Paper Award, i which is given for the best paper published in 2018 or 2019 irrespective of the subject area. [Extracted from the article]

During 2013, Birkhäuser (Springer) instituted three Best Paper Awards for papers published in Circuits, Systems and Signal Processing (see the announcement in the October 2013 issue of CSSP). A call for nominations for these awards was sent out to all the Associate Editors inviting them to nominate those papers published in 2017 or 2018 in CSSP, which should be considered for these awards. The recipients for the I Sydney R. Parker Best Paper Award i given for the best paper published in 2018 in the area of Signal Processing are Abhishek Choubey and Basant Kumar Mohanty for their paper entitled "Novel Data Access Scheme and Efficient Parallel Architecture for Multilevel 2-D DWT", published in the October 2018 issue, pp. 4482-4503. [Extracted from the article]

In this paper, a double-pole double-throw analog switch with n-channel architecture driven by a charge pump is described. The architecture proposed in this paper not only can reduce the on-resistance of the complementary metal oxide semiconductor (CMOS) switch, but also can realize a stable on-resistance within the full swing range of the input signal. This analog switch has the characteristics of high-speed, low-voltage, and high linearity, which is suitable for high-speed USB (Universal Serial Bus) 2.0 applications and meets low-speed and full-speed USB requirements. The test chip using a 0.25 μm BCD (bipolar–CMOS–DMOS) process confirms the characteristics of the switch. It uses + 2.8 to + 5.5 V single power supply, and the normal operating temperature range is − 40 to + 85 °C. This switch has an over-voltage protection function, which can prevent damage to the switch from the high input voltage. Besides, the switch port can realize dual-direction transmission. The analog switch designed in this paper solves some problems of traditional analog switches, such as large on-resistance, large supply current, and large parasitic capacitance. The on-resistance of the analog switch architecture in this paper is 5 Ω and the on-resistance flatness is 0.1 Ω. The supply current is as low as 0.87 μA while the whole chip area is 0.65 mm2. [ABSTRACT FROM AUTHOR]

This special issue of the circuits, systems and signal processing journal focuses on recent advances and improvements in leading-edge integrated machine learning algorithms and signal processing systems. Although signal processing has been studied over several decades, the computer industry is only beginning to understand how signal processing techniques can be well integrated for the development of human-machine interfaces with the advancement of machine learning algorithms. As advances in signal processing tools and machine learning algorithms are becoming more powerful in terms of functionality and communicative capabilities, their contribution to the journal of circuits, system and signal processing is becoming more significant. [Extracted from the article]

Highlights from the article: Deep learning employs deep neural networks (DNNs), which are neural networks with more than one hidden layer, with recently developed initialization and training strategies using massive amounts of diverse data as examples. The paper provides an overview of recent approaches to deep learning as applied to a range of speech processing tasks, primarily for automatic speech recognition (ASR), but also text-to-speech and speaker, language, and emotion recognition. The authors propose integrating deep neural network (DNN)-HMM technique with the HiLAM method where the state alignment information from the HiLAM is used to discriminatively train a DNN to further improve the system performance.

The article announces the Best Paper Awards for papers published in the periodical in areas of electric circuits, systems and signal processing including the Armen H. Zemanian Best Paper Award to Michał Tadeusiewicz and others; and the Sydney R. Parker Best Paper Award to Fatema Tuz Jhohura and others.

The article announces the recipients of the Best Paper Awards for 2014, including Yaonan Tong, Yigang He, Hongmin Li, Wenxin Yu and Ying Long for the Armen H. Zimanian Best Paper Award.

This short paper presents a novel circuit for sigmoid activation function, which is based on the current-mode analog building block. The proposed circuit is simple, CMOS compatible, operates on current signals and provides an output voltage as desired activation function. The transition point in sigmoid function can be easily varied by changing the reference current. The proposed circuit is simulated using ± 1.75 V supply voltage. The proposal offers a promising advance for future neural applications. [ABSTRACT FROM AUTHOR]

The article announces several best paper awards given to various authors for their papers including the 2013 Armen H. Zemanian award to K. Biswas, M.C. Tripathy and S. Sen, the 2013 Sydney R. Parker award and the 2013 M.N.S. Swamy award to B.K. Meher and P.K. Meher.

Gabor phase retrieval is the problem of recovering a signal from the absolute values of Gabor transform, which has turned into a very active research area. In the paper, we define a generalized Paley–Wiener space, which is obtained by applying the special affine Fourier transform to L p ([ - B , B ]) (2 ≤ p ≤ ∞) and provide the uniqueness of the Gabor phase retrieval in the generalized Paley–Wiener space. When the window function ψ is the inverse special affine Fourier transform of ϕ = 2 1 4 e - π x 2 , we show that every signal in the generalized Paley–Wiener space can be uniquely recovered, up to a global sign, from its the magnitudes of Gabor measurement sampled on a rectangular lattice. Recently, Grohs, Liehr and Wellershoff studied the Gabor phase retrieval problems in the conventional Paley–Wiener space. The paper extends their results to the generalized Paley–Wiener space. Since the generalized Paley–Wiener space includes a broader class of signals, our results expand the applied range of the Gabor phase retrieval. [ABSTRACT FROM AUTHOR]

This research paper presents a circuit-based phase noise model of a cross-coupled LC tank oscillator. The effect of the Oscillator's noise is one of the most critical items in designing modern RF communication systems. The noise factor necessitates a more thorough comprehension of design tradeoffs in RF VCO IC implementations. This research paper introduces a new analytical derivation to produce a well-bounded third-order polynomial equation accurately representing the LC oscillator's phase noise behaviour. The third-order polynomial equation includes circuit parameters such as capacitance, inductance and quality factors to understand the phase noise characteristics. The proposed method determines the amplitude and phase noise and forms a link with the circuit operating point, and phase noise is produced as a direct result of the circuit parameters. The advantage of the proposed resulting equation is that it avoids the need for complex simulations to identify the noise characteristics in such a process. The proposed equation was validated by comparing the tank circuit simulation results. The simulation results verify the applicability of the third-order polynomial equation representing the noise characteristics of the LC oscillator. [ABSTRACT FROM AUTHOR]

This paper proposes an algorithm to obtain the sampling factors to model any frequency partitioning so that it is realized using low complexity rational decimated non-uniform filter banks (RDNUFBs). The proposed algorithm is employed to approximate the Bark scale to find a rational frequency partitioning that can be realized using RDNUFBs with less approximation error. The proposed Bark frequency partitioning is found to reduce the average deviation in centre frequency and bandwidth by 65.04% and 48.50%, respectively, and root-mean-square bandwidth deviation by 54.46% when compared to those of the existing perceptual wavelet approximation of Bark scale. In the first filter bank design approach discussed in the paper, a near-perfect reconstruction partially cosine modulated filter bank is employed to obtain the improved Bark frequency partitioning. In the second design approach, the hardware complexity of the PCM-based RDNUFB is reduced by deriving the channels with different sampling factors from the same prototype filter by the method of channel merging. There is a considerable reduction of 40.83% in the number of multipliers when merging of partially cosine modulated channels is employed. It is also found that both the proposed approaches can reduce the delay by 95.17% when compared to the existing rational tree approximation methods and hence, are suitable for real-time applications. [ABSTRACT FROM AUTHOR]

This paper studies global exponential stability (GES) of discrete-time (D-T) BAM neural networks (BAMNNs) affected by impulses and time-varying delays. An impulse-free D-T BAMNN with time-varying delays is first developed via the properties of M-matrices, and then the relation between the solutions of the original and new BAMNNs is established. From which, sufficient conditions for GES of the original BAMNN are derived by investigating GES conditions of the new BAMNN based on the counter-evidence and the nature of the nonsingular M-matrix. The results of illustrative examples show that the obtained GES criteria are effective. By comparing with previous results, this paper has the following three merits: (a) the obtained GES criteria are to check the positivity of eigenvalues of a constant matrix, which is easy to realize; (b) this method can be used for other D-T system models affected by impulses and time-varying delays; and (c) the numerical results show that our method is less conservative than ones in other literatures. [ABSTRACT FROM AUTHOR]

This paper presents a detailed design of a broadband power amplifier (PA) utilizing 0.18-μm CMOS technology, operating in the frequency range of 2–5 GHz. This ultra-wideband (UWB) power amplifier uses a cascode topology with current reuse to enhance gain over the desired frequency band, utilizing an inductive source degenerate design to achieve the best linearity and output power and gain while maintaining a wide bandwidth. The inductive source degenerate adopts bondwire and microstrip line design. The paper includes extensive analysis, simulation results, and measurements to verify the performance of the amplifier and demonstrate its suitability for broadband power amplifier applications. The measured results for the proposed UWB power amplifier show excellent performance, with an impressive third-order input intercept point (IIP3) ranging from 15 to 18.7 dBm over the frequency range of 2–5 GHz. The output third-order intercept point (OIP3) ranges from 33 to 35 dBm. Additionally, the gain flatness is specified as 12.5 ± 1.5 dB. The reverse isolation is greater than or equal to − 40 dBm. The PA has a P1dB output power (OP1dB) of 10.2 dBm at 3 GHz, 9.2 dBm at 4 GHz, and 9.2 dBm at 5 GHz, respectively. The PA has a P1dB power-added efficiency of 30.5% at 3 GHz, 23% at 4 GHz, and 22% at 5 GHz with a 50 Ω load termination. The power dissipation is 33.3 mW at a supply voltage of 1.8 V. In addition, the PA has an excellent small group delay variation of ± 65 ps. The chip area is 1.01 × 1.08 mm2, including the pads. The proposed UWB PA demonstrates exceptional linearity, efficiency, and group delay in the 2–5 GHz frequency band. [ABSTRACT FROM AUTHOR]

This paper investigates the sliding mode control (SMC) problem of discrete-time singular Markovian jump systems with time-varying delay under an event-triggered strategy (ETS). In the system we study, there are uncertainties in the system matrix, especially in the difference matrix. A state augmentation strategy is proposed due to uncertainties in the difference matrix. A suitable sliding mode surface (SMS) function is built, and the corresponding sliding mode dynamics (SMD) is derived based on ETS. Some sufficient conditions are presented to guarantee that SMD is H ∞ -admissible for all uncertainties. Furthermore, an SMC law under ETS is derived so that the system trajectories can be driven onto the prescribed SMS in finite time. Finally, the effectiveness of the approach in the paper is demonstrated by two simulated examples. [ABSTRACT FROM AUTHOR]

Under the condition of low signal-to-noise ratio, for the problem of insufficient speech feature extraction and speech enhancement effect of the traditional neural network, this paper is based on empirical mode decomposition (EMD), temporal convolutional network (TCN), and gated convolution recurrent neural network (GCRN), while combining with feature fusion module (FFM), the adaptive mean median-empirical mode decomposition-multilayer gated feature fusion module convolutional recurrent neural networks (ME-MGFCRNs) for speech enhancement modeling. The network model uses a split-frequency learning strategy to learn low-frequency features and high-frequency features, i.e., the TCN and MGFCRN networks are used to obtain low-frequency and high-frequency features, and FFM processes the two sets of features to achieve speech enhancement in the form of feature mapping. The model proposed in this paper performs ablation and comparison experiments on the dataset to evaluate the enhancement effect of speech using PESQ, FwSegSNR, and STOI metrics. The research shows that under different noise environments and SNR conditions, the model proposed in this paper improves compared with other baseline models, especially under the low SNR condition of − 5 dB, FwSegSNR and PESQ improve by more than 0.86 dB and 0.02 compared with other baseline models. [ABSTRACT FROM AUTHOR]

This paper studies the consensus problem of Multi-Agent Systems (MASs) with input-delay using the Model Predictive Control (MPC) approach. Due to challenges such as input delay and communication graph, the traditional MPC is not efficient for the considered systems. In this regard, a novel MPC is developed for MASs with input delay. The main advantage of this paper is to design distributed controllers based on minimizing given cost functions which result in the improvement of the transient responses. For this purpose, first, distributed observers are derived to estimate the leader's states, perfectly. Then, distributed controllers are achieved through the MPC approach. Finally, numerical and practical examples are simulated to affirm the efficiency and applicability of the presented scheme. [ABSTRACT FROM AUTHOR]

This paper presents a foreground calibration algorithm combination with a background calibration algorithm for successive approximation register analog-to-digital converters (ADC). The foreground calibration for capacitor mismatch is capacitor recombination algorithm and the background calibration for capacitor mismatch is single-channel least mean square (LMS) algorithm. The capacitor recombination algorithm can initially calibrate the capacitor array mismatch and provide an environment conducive to convergence for LMS algorithm. After running the capacitor recombination algorithm, the convergence speed of LMS algorithm can be improved. The results of 100 times of Monte Carlo simulation show that LMS algorithm can converge within 1500 cycles, the ADC signal-to-noise and distortion ratio is improved from 71.63 to 97.47 dB, the spurious-free dynamic range is improved from 84.98 to 125.28 dB, the effective number of bits is improved from 12.85 to 15.90 bits, the differential nonlinearity is reduced from 2.09 to 0.90 LSBs, and the integer nonlinear is reduced from 7.14 to 0.68 LSBs. [ABSTRACT FROM AUTHOR]

The necessary and sufficient conditions for decomposing a fourth-order (FO) linear time-variant system (LTVS) in the form of cascade connection of a first-order system and a third-order system that are commutative are expressed explicitly in this paper. Some additional conditions are also derived for a valid decomposition when the initial conditions are different from zero. Further, explicit formulas are derived for the determination of the decomposed subsystems. The paper also investigated the effects of changing the connection order on the sensitivity and disturbance properties. Theoretical results about the decomposition are supported and illustrated by considering various examples. [ABSTRACT FROM AUTHOR]

Full adders (FAs) are the core elements and substantially impact the performance of digital signal processing applications such as arithmetic logic unit (ALU). In this paper, XOR gate-based FA design is presented that can operate appropriately in the domain of ultra-low voltage (LV) and low power (LP). In this treatise, FGMOS technique is used to elevate the performance in terms of design complexity and to reduce the power requirements. Important device performance characteristics such as power (pwr), delay (tp), power delay product (PDP) and energy delay product (EDP) are explored for the proposed FGMOS XOR gate design, and existing XOR designs are used to assess the results. This research paper presents a low-power FGMOS XOR gate design with a total power consumption of 5.39 pW at 0.7 V supply. Further, in this work, 1-bit FGMOS-based ALU is proposed to perform the functions of full adder, NAND, NOR and XOR. To ameliorate the performance of the circuit, FGMOS-based NAND and NOR gate designs are also proposed in this treatise. Aforementioned full adder and XOR gate along with pass-transistor logic (PTL)-based multiplexers are used to design efficient design of 1-bit ALU at 22-nm technology node. This research paper explicates the utility of FGMOS technique for the designing of high-performance complex digital circuits. [ABSTRACT FROM AUTHOR]

In this paper, the finite-time and fixed-time consensus tracking of Euler–Lagrange systems (ELSs) under a directed graph is studied. Firstly, note that the settling time of finite-time consensus tracking (Fin-TCT) is related to the initial values, while the settling time of fixed-time consensus tracking (Fix-TCT) is independent of the initial values. The reason for considering both Fin-TCT and Fix-TCT is to compare them in terms of the settling time. Then, this paper designs the distributed estimated-based hierarchical control algorithms to solve the above problems. By Lyapunov stability analysis, if the coupling gains are properly designed, the Fin-TCT and Fix-TCT of the ELSs with external disturbances can be achieved. Finally, simulation results are presented to demonstrate the feasibility of the developed control algorithms. [ABSTRACT FROM AUTHOR]

In this paper, the designs of ternary digital circuits are discussed. The ternary logic is a better choice over conventional logics due its extraordinary offers such as high operating speed, reduced chip area and reduced on-chip interconnects. A new method is presented in this paper to design the ternary circuits using graphene nanoribbon field effect transistors (GNRFETs) and resistive random access memory (RRAM). The dimer line of graphene nanoribbon (GNR) is used to control the threshold voltage of GNRFETs. The RRAM is used because it has multilevel cell capacity that enables the multiple resistance state storage in a single cell. The ternary logic basic circuits such as standard ternary inverter (STI), NAND and NOR circuits are proposed. In addition, ternary half adder circuit is designed that helps to develop the complex circuits. The HSPICE simulator is utilized for simulating the proposed designs to obtain the performances such as delay, power and power delay product (PDP). Furthermore, the obtained circuit performances are compared with carbon nanotube FETs (CNTFETs)-based and RRAM-based circuits. The comparison results show that the proposed GNRFET and RRAM circuits achieved 46.11% of overall performance improvement over the CNTFET and RRAM circuits. Furthermore, line edge roughness (Pr) effect on the proposed STI and half adder circuit performance is investigated. The delay values are increased, and the power and PDP values are decreased for the higher Pr values. The effect of process, voltage and temperature (PVT) variations on proposed STI and half adder circuits is also performed to analyze the performance. It noticed that the proposed STI and half adder circuits show minimum variation on performance for the PVT variations. [ABSTRACT FROM AUTHOR]

To address the issue of performance degradation in the Capon beamformer when the desired signal appears in the training data, the integration operation is introduced for the interference-plus-noise covariance matrix reconstruction, and the steering vector (SV) is estimated by solving a convex optimization problem in some robust adaptive beamforming papers. However, this approach suffers from high computational complexity and is limited by the resolution of the Capon spectrum. In light of this, our paper proposes a novel robust adaptive beamforming method. To overcome the limited resolution of the Capon spectrum, we introduce the multiple signal classification method to acquire the nominal SVs. Subsequently, the SVs are updated based on subspace orthogonality. The proposed method constructs orthogonal components from the nominal SVs to circumvent the convex problem and reduce computational complexity. Additionally, the interference powers are obtained using the Capon spectrum without the noise component via eigenvalue decomposition. This refinement improves the accuracy of the estimated interference powers. Simulation results demonstrate that the proposed method is effective and robust against common mismatch errors. [ABSTRACT FROM AUTHOR]

Multimedia data have increased dramatically today, making the distinction between desirable information and other types of information extremely important. Speech/music discrimination is a field of audio analytics that aims to detect and classify speech and music segments in an audio file. This paper proposes a novel feature extraction method called Long-Term Multi-band Frequency-Domain Mean-Crossing Rate (FDMCR). The proposed feature computes the average frequency-domain mean-crossing rate along the frequency axis for each of the perceptual Mel-scaled frequency bands of the signal power spectrum. In this paper, the class-separation capability of this feature is first measured by well-known divergence criteria such as Maximum Fisher Discriminant Ratio (MFDR), Bhattacharyya divergence, and Jeffreys/Symmetric Kullback–Leibler (SKL) divergence. The proposed feature is then applied to the speech/music discrimination (SMD) process on two well-known speech-music datasets—GTZAN and S &S (Scheirer and Slaney). The results obtained on the two datasets using conventional classifiers, including k-NN, GMM, and SVM, as well as deep learning-based classification methods, including CNN, LSTM, and BiLSTM, show that the proposed feature outperforms other features in speech/music discrimination. [ABSTRACT FROM AUTHOR]

This paper presents rank-awareness algorithms to solve sparse blind deconvolution using modulated input. We consider sparse blind deconvolution as a rank-one column-sparse matrix recovery problem, so the proposed algorithms can use both the rank-one property and the sparsity of the unknowns. Unknown input s is first multiplied by a random sign sequence r and then convolved with an arbitrary filter h to obtain the measurements y . The unknown signal s is assumed to have a sparse representation. Sparse blind deconvolution using modulated input has unique applications, such as the blind calibration of the random demodulation system. When the number of measurements has satisfied certain conditions, blind deconvolution can be solved without considering signal sparsity. This paper mainly studies how to use signal sparsity to reduce the number of measurements required for sparse blind deconvolution. We propose two methods to solve this problem. The first method uses the ℓ 1 -norm regularization to promote the unknown signal to iterate in the direction of sparsity. The second method transforms the sparse blind deconvolution problem into a rank-one constrained block-sparse signal recovery problem, and we propose the rank-awareness sparse blind demodulation algorithm to solve it. Our proposed methods could effectively reduce the number of measurements required for sparse blind deconvolution. Under certain conditions, our proposed sparse blind deconvolution algorithms required 320 and 160 measurements, while 400 measurements were required when signal sparsity was not considered. The simulation results verify the effectiveness of the proposed algorithms. [ABSTRACT FROM AUTHOR]

The paper discusses in detail the inability of a circuit designer to design a single input single element-controlled universal memelement emulator. A Single input Single element-controlled universal memelement emulator would be such a configuration that can provide the realization of any of the three memelements (Memristor/Memcapacitor/Meminductor) by taking a circuit element as inductor (L), Capacitor (C) or Resistor (R) with the same input port. The analysis shows that no such circuit configuration can be built to realize such a highly flexible universal memelement emulator. It is found that by using such structures, only two ideal memelements can be realized at maximum. If these circuit structures are used to realize the remaining third memelement, then, the resulting element comes out to be a non-ideal memelement. Two circuit configurations to demonstrate this theory are also included for both charge-controlled and flux-controlled memelement emulation based on the approaches shown in this paper. [ABSTRACT FROM AUTHOR]

While the practical application of adaptive filters has indeed garnered substantial attention, two pressing issues persist that have a profound impact on their performance—system sparsity and the presence of contaminated Gaussian impulsive noise. In this research paper, we propose a novel approach to tackle both of these issues simultaneously by introducing the concept of a proportionate matrix. Specifically, we present a proportionate maximum total complex correntropy algorithm based on the errors-in-variables model. The paper presents a theoretical analysis of the steady-state weight error power under the influence of impulsive noise. Furthermore, it discusses the performance comparison in system identification and highlights the robustness of the proposed algorithm. To validate its effectiveness, a simulation involving stereophonic acoustic echo cancellation is conducted, and the results confirm the clear advantages of the proposed Proportionate Maximum Total Complex Correntropy algorithm. [ABSTRACT FROM AUTHOR]

This paper studies the problem of finite-time stabilization for singular Markov jump systems (SMJSs) with time-varying delays and generally uncertain transition rates. First, a suitable Lyapunov–Krasovskii functional is constructed. And the criterion of the finite-time stability for singular Markov jump systems is analyzed. We adopt a better design approach for the matrix P ¯ i satisfying the equality constraints, which is much less conservative. Then, a state feedback controller design method based on linear matrix inequalities (LMIs) is presented to ensure that the closed-loop system is finite-time stable. Finally, simulation examples are given to illustrate the results' correctness and validity of this paper. [ABSTRACT FROM AUTHOR]

Several real-life problems that involve a time delay are modeled using fractional time-delay systems. However, most studies related to these systems assume that the delay is already known, which is not the case in practical scenarios where the delay is often uncertain or unknown. To address this issue, this paper proposes an algebraic and robust method to estimate the input delay for a class of fractional time-delay systems in a noisy environment, by applying a cross-convolution approach. Besides, a filtering methodology is incorporated with the proposed approach to enhance its efficacy. In addition, this paper presents novel theories on convolution in the field of fractional calculus. Finally, the performance of the proposed approach is demonstrated by numerical simulations. [ABSTRACT FROM AUTHOR]

Developing an automatic speaker verification (ASV) system for children's speech presents significant challenges. One major obstacle is the scarcity of domain-specific data. This issue is exacerbated when dealing with short speech utterances, a relatively unexplored area in children's ASV. Voice biometric systems struggle during enrollment and verification phase, when faced with inadequate speech data, both in volume as well as in duration. To address data scarcity, this paper explores various in-domain and out-of-domain data augmentation techniques. Out-of-domain data from adult speakers, which have distinct acoustic attributes from children, are modified using techniques like voice-conversion, prosody and formant modification to make them acoustically similar to children's speech. In-domain data augmentation involves perturbing the speed of children's speech. This combined data augmentation approach not only increases training data volume but also captures missing target attributes, resulting in a significant 43.91% reduction in equal error rate (EER) compared to the baseline system. Additionally, the paper addresses the challenge of preserving higher-frequency components in children's speech. It achieves this by concatenating conventional Mel-frequency cepstral coefficients (MFCC) with Inverse-Mel-frequency cepstral coefficient (IMFCC) features at the frame level. The low canonical correlation between MFCC and IMFCC feature vectors motivates this fusion. The feature concatenation approach, when combined with proposed data augmentation, results in an appreciable reduction of 48.51% in the overall EER, demonstrating its effectiveness in improving the performance of children's ASV system. [ABSTRACT FROM AUTHOR]

Analytic signals constitute a class of signals that are widely applied in time–frequency analysis such as extracting instantaneous frequency (IF) or phase derivative in the characterization of ultrashort laser pulse. The purpose of this paper is to investigate the phase retrieval (PR) problem for analytic signals in C N by short-time Fourier transform (STFT) measurements since such measurements enjoy some nice structures. Since generic analytic signals are not sparse in the time domain, the existing PR results for sparse (in time domain) signals do not apply to analytic signals. In this paper, the windows are required to be bandlimited such that they usually have the full support length N and allow us to get much better resolutions on low frequencies. By exploiting the structure of the STFT associated with bandlimited windows for analytic signals, we prove that the STFT-based phase retrieval (STFT-PR for short) of generic analytic signals can be achieved by their (3 ⌊ N 2 ⌋ + 1) measurements, where ⌊ x ⌋ denotes the largest integer that is not larger than x. Since the generic analytic signals are (⌊ N 2 ⌋ + 1) -sparse in the Fourier domain, such a number of measurements is lower than 4 N + O (1) and O (k 3) which are required in the literature for STFT-PR of all signals and of k 2 -sparse (in the Fourier domain) signals in C N 2 , respectively. Moreover, we also prove that if the length N is even and the windows are also analytic, then the number of measurements can be reduced to (3 N 2 - 1) . As an application of this, we get that the instantaneous frequency (IF) of a generic analytic signal can be exactly recovered from the STFT measurements. [ABSTRACT FROM AUTHOR]

Autonomous cars, cloud computing and image recognition technology have spread drastically in recent years. However, operation of these applications requires a large number of multipliers and has a high hardware cost. Logarithmic converters can replace the multipliers at the expense of a large conversion error. This paper proposes a design for area-delay-product (ADP)-efficient logarithmic converters that use compensation methods involving mantissa bits. Replacing the conventional constant adder, bit-level manipulation and shift-and-add scheme, the proposed ADP-efficient logarithmic converters use mantissa bits to compensate for the conversion error of the accurate logarithmic curve. According to different specifications and applications of tolerable logarithmic conversion error, three sets of logarithmic converters, that is, methods 1, 2 and 3, were proposed to approximate the accurate logarithmic curve. The proposed ADP-efficient logarithmic converters can achieve a smaller implementation area, shorter latency and lower error than other methods in the literature. The total conversion errors of the proposed ADP-efficient logarithmic converters are 0.0379, 0.0303 and 0.0241 for methods 1, 2 and 3, respectively. Simultaneously, the proposed ADP-efficient logarithmic converters can attain ADP savings of 35.32, 69.71 and 66.19% compared to previous papers, for the proposed methods 1, 2 and 3. The design's very-large-scale-integration (VLSI) hardware implementation is synthesized by the Taiwan Semiconductor Manufacture Company using 0.18 μm CMOS technology. Additionally, the proposed ADP-efficient implementation structure is ROM-free, fast, simple and has a lower logarithmic conversion error range. The proposed converters can be easily implemented by VLSI digital circuits and may be applied to 5G technology and digital signal processing. [ABSTRACT FROM AUTHOR]

When we study the Karnaugh map in the switching theory course, we learn that the ones in the map are combined in rectangles whose length and width must be a power of two. The result is the logic function described as a sum of products. This paper shows that we can also make groups where the length and width of the rectangles are equal to three. This results in a logic function that is simpler than the sum of products in terms of logic gates, leading to more hardware-efficient circuits. This idea is extended later in the paper to other groups of elements. Finally, a new perspective on the Karnaugh map that integrates the proposed approach with the conventional one is provided. This can be used in switching theory courses to improve the explanation of the Karnaugh map. [ABSTRACT FROM AUTHOR]

This paper aims to propose an effective steerable directional Laplacian regularizer for image denoising. A steerable inhomogeneous directional Laplacian associated with an efficient contextual indicator is presented and taken as the diffusion flux to formulate the desired steerable directional Laplacian regularizer. With the contextual indicator for contextual discontinuities, the steerable directional Laplacian regularizer degenerates to a tangent diffusion equation for sharpening the inter-object boundaries and reduces to a normal diffusion equation for smoothing the homogenous regions. Unlike the traditional Laplacian regularizer, the model in this paper is anticipated to be anisotropic and robust while overcoming the staircase effect caused by most of second-order anisotropic diffusion models. Experimental results support that the proposed model outperforms some benchmark models with regard to both perceptual quality and objective evaluation metrics. [ABSTRACT FROM AUTHOR]

Sparse signals can be reconstructed from far fewer samples than those that were required by the Shannon sampling theorem, if compressed sensing (CS) is employed. Traditionally, a random Gaussian (rGauss) matrix is used as a projection matrix in CS. Alternatively, optimization of the projection matrix is considered in this paper to enhance the quality of the reconstruction in CS. Bringing the multiplication of the projection matrix and the sparsifying basis to be near an equiangular tight frame (ETF) is a good idea proposed by some previous works. Here, a low-rank Gram matrix model is introduced to realize this idea. Also, an algorithm is presented via a computational method of the low-rank matrix nearness problem. Simulations show that the proposed method is better than some other methods in optimizing the projection matrix in terms of image denoising via sparse representation. [ABSTRACT FROM AUTHOR]

This paper presents a high imperceptible and robust audio watermarking algorithm by optimizing the scaling parameter as per the imperceptible requirements with minimum bit error rate. The spread spectrum-based audio watermarking is used in this paper, where the scaling parameter is optimized to achieve trade-off between imperceptibility and robustness of watermarked audio. Primarily, the effect of scaling parameter on the perceptual quality of watermarked audio is investigated and the total error introduced in the host audio due to embedding the watermark is computed. The scaling parameter is optimized for maximizing the robustness by considering objective difference grade (ODG) score (for music signals), perceptual evaluation of speech quality (PESQ) score (for speech signals) as a constraint to meet the imperceptibility requirements. To solve this proposed optimization problem, two search algorithms are developed. The embedding is performed in low-pass framelet transform coefficients through SVD with the optimized scaling parameter. The experimental results show that the proposed algorithm achieves good imperceptibility with an average ODG score of −0.32 and PESQ score of 3.86 for music and speech signals, respectively, under various payload conditions. The proposed algorithm shows better robustness to the common signal processing attacks such as noise addition, filtering, resampling, MP3 compression, amplitude scaling, cropping, and requantization. [ABSTRACT FROM AUTHOR]

This paper presents a novel power and energy-efficient carbon nanotube field-effect transistor (CNTFET)-based design of a quaternary magnitude comparator for single and double digits. It also proposes an improved circuit of the ternary single-digit comparator and a novel design of the double-digit ternary comparator. The designs make use of the pass transistor logic and transmission gates, resulting in a more power and energy-efficient design with a lower number of CNTFETs when compared with existing designs. Besides, this paper also proposes a generalized circuit of magnitude comparator for multiple digits. The proposed circuits are simulated in HSPICE using the 32 nm CNTFET model presented by Stanford University. Average power and propagation delays are observed and the power-delay-product (PDP) is calculated in each case. The impact of process parameter variations has been analyzed through Monte Carlo simulation and has been presented in the form of two-dimensional graphs. [ABSTRACT FROM AUTHOR]