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Degradation of device under substrate hot-electron (SHE) and constant voltage direct-tunnelling (CVDT) stresses are studied using NMOSFET with 1.4-nm gate oxides. The degradation of device parameters and the degradation of the stress induced leakage current (SILC) under these two stresses are reported. The emphasis of this paper is on SILC and breakdown of ultra-thin-gate-oxide under these two stresses. SILC increases with stress time and several soft breakdown events occur during direct-tunnelling (DT) stress. During SHE stress, SILC firstly decreases with stress time and suddenly jumps to a high level, and no soft breakdown event is observed. For DT injection, the positive hole trapped in the oxide and hole direct-tunnelling play important roles in the breakdown. For SHE injection, it is because injected hot electrons accelerate the formation of defects and these defects formed by hot electrons induce breakdown.

Recovery phenomenon is observed under negative gate voltage stress which is smaller than the previous degradation stress. We focus on the drain current to study the degradation and recovery of negative bias temperature instability (NBTI) with a real-time method. By this method, different recovery phenomena among different size devices are observed. Under negative recovery stress, the drain current gradually recovers for the large size devices and gets into recovery saturation when long recovery time is involved. For small-size devices, a step-like recovery of drain current is observed. The recovery of the drain current is mainly caused by the holes detrapping and tunnelling back to the channel surface which are trapped in oxide. The model of hole detrapping explains the recovery under negative voltage stress reasonably.

Negative bias temperature instability (NBTI) and stress-induced leakage current (SILC) both are more serious due to the aggressive scaling lowering of devices. We investigate the SILC during NBTI stress in PMOSFETs with ultra-thin gate dielectrics. The SILC sensed range from -1 V to 1 V is divided into four parts: the on-state SILC, the near-zero SILC, the off-state SILC sensed at lower positive voltages and the one sensed at higher positive voltages. We develop a model of tunnelling assisted by interface states and oxide bulk traps to explain the four different parts of SILC during NBTI stress.

We report a GaN metal-oxide-semiconductor high electron mobility transistor (MOS-HEMT) with atomic layer deposited (ALD) Al2O3 gate dielectric. Based on the previous work [Appl. Phys. Lett. 86 (2005) 063501] of Ye et al. by decreasing the thickness of the gate oxide to 3.5 nm and optimizing the device fabrication process, the device with maximum transconductance of 150 mS/mm is produced and discussed in comparison with the result of 100 mS/mm of Ye et al. The corresponding drain current density in the 0.8-μm-gate-length MOS-HEMT is 800 mA/mm at the gate bias of 3.0 V. The gate leakage is two orders of magnitude lower than that of the conventional AlGaN/GaN HEMT. The excellent characteristics of this novel MOS-HEMT device structure with ALD Al2O3 gate dielectric are presented.

We report Al0.30Ga0.70N/GaN/Al0.07Ga0.93N double heterostructure high electron mobility transistors with a record saturation drain current of 1050 mA/mm. By optimizing the graded buffer layer and the GaN channel thickness, both the crystal quality and the device performance are improved significantly, including electron mobility promoted from 1535 to 1602 cm2/Vs, sheet carrier density improved from 0.87×1013 to 1.15×1013 cm−2, edge dislocation density reduced from 2.4×109 to 1.3×109 cm−2, saturation drain current promoted from 757 to record 1050 mA/mm, mesa leakage reduced by two orders in magnitude, and breakdown voltage promoted from 72 to 108 V.

A GaN-based enhancement-mode (E-Mode) metal-insulator-semiconductor (MIS) high electron mobility transistor (HEMT) with a 2 nm/5 nm/1.5 nm-thin GaN/AlGaN/AlN barrier is presented. We find that the formation of a two-dimensional electron gas (2DES) in the GaN/AlGaN/AlN/GaN heterostructure can be controlled by the presence of the plasma-enhanced chemical-vapor deposition (PECVD) Si3N4 on the barrier layer, and the degree of decrease in sheet resistance Rsh is dependent on the Si3N4 thickness. We choose 13 nm Si3N4 as the gate insulator to decrease gate current and to improve the threshold voltage of devices. With selective etching of the passivation Si3N4 under gate and over fluorine plasma treatment, the MIS-HEMT exhibits a high threshold voltage of 1.8 V. The maximum drain current Id,max and the maximum transconductance are 810 mA/mm and 190 mS/mm, respectively. The devices show a wide operation range of 4.5 V.

Different phenomena are observed under negative gate voltage stress which is smaller than the previous degradation stress in PMOSFETs with different oxide thicknesses. We adopt the real time method to make a point of the drain current to study the degradation and recovery of negative bias temperature instability (NBTI). For the device with thin oxide, recovery phenomenon appears when smaller negative voltage stress was applied, due to the more influencing oxide charges detrapping effects than the interface states. For the device with thick oxide, not recovery but degradation phenomenon comes forth. As many charges are trapped in the deeper position and higher energy level in the oxide, these charges can not be detrapped. Therefore, the effect of the charge detrapping is smaller than that of the interface states in the thick oxide. The degradation presents itself during the ‘recovery’ time.

A new multilayer-structured AlN/AlGaN/GaN heterostructure high-electron-mobility transistor (HEMT) is demonstrated. The AlN/AlGaN/GaN HEMT exhibits the maximum drain current density of 800 mA/mm and the maximum extrinsic transconductance of 170 mS/mm. Due to the increase of the distance between the gate and the two-dimensional electron-gas channel, the threshold voltage shifts slightly to the negative. The reduced drain current collapse and higher breakdown voltage are observed on this AlN/AlGaN/GaN HEMT. The current gain cut-off frequency and the maximum frequency of oscillation are 18.5 GHz and 29.0 GHz, respectively.

A susceptor structure with a ring channel for a vertical metalorganic chemical vapor deposition reactor by induction heating is proposed. Thus the directions of heat conduction are changed by the channel, and the channel makes the heat in the susceptor redistribute. The pattern of heat transfer in this susceptor is also analyzed. In addition, the location and size of the channel in the susceptor are optimized using the finite element method. A comparison between the optimized and the conventional susceptor shows that the optimized susceptor not only enhances the heating efficiency but also the uniformity of temperature distribution in the wafer, which contributes to improving the quality of the film growth.

A simple yet accurate interconnect parasitical capacitance model is presented. Based on this model a novel interconnect bus optimization methodology is proposed. Combining wire spacing with wire ordering, this methodology focuses on bus dynamic power optimization with consideration of bus performance requirements. The optimization methodology is verified under a 65 nm technology node and it shows that with 50% slack in the routing space, a 33.03% power saving can be provided by the proposed optimization methodology for an intermediate video bus compared to the 27.68% power saving provided by uniform spacing technology. The proposed methodology is especially suitable for computer-aided design of nanometer scale on-chip buses.

The anomalous phenomenon of generation current IGD in the lightly doped drain (LDD) nMOSFET measured under the drain bias VD-step mode is reported. We propose an assumption of activated (A) and frozen (F) traps for the VD-step mode: The A traps contributes to IGD while the F process can make them lose the roles as generation centers. The A and F regions can form the F-A region. The comparison of the F and A regions decides the role of the F-A region. The experiments confirm the assumption.

The effects of channel length and width on the degradation of negative bias temperature instability (NBTI) are studied. With the channel length decreasing, the NBTI degradation increases. As the channel edges have more damage and latent damage for the process reasons, the device can be divided into three parts: the gate and source overlap region, the middle channel region, and the gate and drain overlap region. When the NBTI stress is applied, the non-uniform distribution of the generated defects in the three parts will be generated due to the inhomogeneous degradation. With the decreasing channel length, the channel edge regions will take up a larger ratio to the middle channel region and the degradation of NBTI is enhanced. The channel width also plays an important role in the degradation of NBTI. There is an inflection point during the decreasing channel width. There are two particular factors: the lower vertical electric field effect for the thicker gate oxide thickness of the shallow trench isolation (STI) edge and the STI mechanical stress effecting on the NBTI degradation. The former reduces and the latter intensifies the degradation. Under the mutual compromise of the both factors, when the effect of the STI mechanical stress starts to prevail over the lower vertical electric field effect with the channel width decreasing, the inflection point comes into being.

The degradation of AlGaN/GaN high electron mobility transistors (HEMTs) has a close relationship with a model of traps in AlGaN barriers as a result of high electric field. We mainly discuss the impacts of strong electrical field on the AlGaN barrier thickness of AlGaN/GaN HEMTs. It is found that the device with a thin AlGaN barrier layer is more easily degraded. We study the degradation of four parameters, i.e. the gate series resistance RGate, channel resistance Rchannel, gate current IG,off at VGS = −5 and VDS = 0.1 V, and drain current ID,max at VGS = 2 and VDS = 5 V. In addition, the degradation mechanisms of the device electrical parameters are also investigated in detail.

The current slump of different recipes of SiNx passivated AlGaN/GaN high electron mobility transistors (HEMTs) is investigated. The dc and pulsed current-voltage curves of AlGaN/GaN HEMTs using different recipes are analyzed. It is found that passivation leakage has a strong relationship with NH3 flow in the plasma-enhanced chemical vapor phase deposition process, which has impacted on the current collapse of SiNx passivated devices. We analyze the pulsed IDS – VDS characteristics of different recipes of SiNx passivation devices for different combinations of gate and drain quiescent biases (VGS0, VDS0) of (0, 0), (−6, 0), (−6, 15) and (0, 15)V. The possible mechanisms are the traps in SiNx passivation capturing the electrons and the surface states at the SiNx/AlGaN interface, which can affect the channel of two-dimensional electron gas and cause the current collapse.

Electronic properties, surface chemistry and surface morphology of plasma-treated n-Al0.4Ga0.6N material are studied by electrical contact measurements, atomic force microscopy and x-ray photoemission spectroscopy. Although excessive etching can cause the surface roughness to significantly increase, the nitrogen vacancies VN produced by the excessive etching can be compensated for by the negative effects of the rougher surface. Thus, VN produced by excessive etching plays a key role in Ohmic contact of high-Al content AlGaN and it can reduce Ohmic contact resistance. The effect of rapid thermal annealing on the performance of n-Al0.4Ga0.6N can significantly reduce the etching damage caused by excessive etching.

Hot-carrier degradation for 90nm gate length lightly-doped drain (LDD) NMOSFET with ultra-thin (1.4 nm) gate oxide is investigated under the low gate voltage stress (LGVS) and peak substrate current (Isub, max) stress. It is found that the degradation of device parameters exhibits saturating time dependence under the two stresses. We concentrate on the effect of these two stresses on gate-induced-drain leakage (GIDL) current and stress induced leakage current (SILC). The characteristics of the GIDL current are used to analyse the damage generated in the gate-to-LDD region during the two stresses. However, the damage generated during the LGVS shows different characteristics from that during Isub, max stress. SILC is also investigated under the two stresses. It is found experimentally that there is a linear correlation between the degradation of SILC and that of threshold voltage during the two stresses. It is concluded that the mechanism of SILC is due to the combined effect of oxide charge trapping and interface traps for the ultra-short gate length and ultra-thin gate oxide LDD NMOSFETs under the two stresses.

We discuss an issue on the activation of p-GaN material under different annealing conditions and study the mechanism for the p-GaN activation. Under annealing in nitrogen, it is found that hydrogen cannot be completely removed from p-GaN. The experiments also indicate that rudimental hydrogen can exist stably in a certain state where hydrogen does not passivate the Mg acceptor in the sample annealing under bias. However, making additional annealing in nitrogen, we find that the steady state hydrogen can be decomposed and the Mg–H complex could generate again. Hydrogen remaining in the layer seems to play a major role in this reversible phenomenon.