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A novel vertical InN/InGaN heterojunction tunnel FET with hetero T-shaped gate as well as polarization-doped source and drain region (InN-Hetero-TG-TFET) is proposed and investigated by Silvaco-Atlas simulations for the first time. Compared with the conventional physical doping TFET devices, the proposed device can realize the P-type source and N-type drain region by means of the polarization effect near the top InN/InGaN and bottom InGaN/InN heterojunctions respectively, which could provide an effective solution of random dopant fluctuation (RDF) and the related problems about the high thermal budget and expensive annealing techniques due to ion-implantation physical doping. Besides, due to the hetero T-shaped gate, the improvement of the on-state performance can be achieved in the proposed device. The simulations of the device proposed here in this work show ION of 4.45 × 10−5 A/μm, ION/IOFF ratio of 1013, and SSavg of 7.5 mV/dec in InN-Hetero-TG-TFET, which are better than the counterparts of the device with a homo T-shaped gate (InN-Homo-TG-TFET) and our reported lateral polarization-induced InN-based TFET (PI-InN-TFET). These results can provide useful reference for further developing the TFETs without physical doping process in low power electronics applications. [ABSTRACT FROM AUTHOR]

The hot carrier effect (HCE) of an ultra-deep sub-micron p-channel metal--oxide semiconductor field-effect transistor (pMOSFET) is investigated in this paper. Experiments indicate that the generation of positively charged interface states is the predominant mechanism in the case of the ultra-deep sub-micron pMOSFET. The relation of the pMOSFET hot carrier degradation to stress time (t), channel width (W), channel length (L), and stress voltage (Vd) is then discussed. Based on the relation, a lifetime prediction model is proposed, which can predict the lifetime of the ultra-deep sub-micron pMOSFET accurately and reflect the influence of the factors on hot carrier degradation directly. [ABSTRACT FROM AUTHOR]

To enhance the reverse blocking capability with low specific on-resistance, a novel vertical metal–oxide–semiconductor field-effect transistor (MOSFET) with a Schottky–drian (SD) and SD-connected semisuperjunctions (SD-D-semi-SJ), named as SD-D-semi-SJ MOSFET is proposed and demonstrated by two-dimensional (2D) numerical simulations. The SD contacted with the n-pillar exhibits the Schottky-contact property, and that with the p-pillar the Ohmic-contact property. Based on these features, the SD-D-semi-SJ MOSFET could obviously overcome the great obstacle of the ineffectivity of the conventional superjunctions (SJ) or semisuperjunctions (semi-SJ) for the reverse applications and achieve a satisfactory trade-off between the reverse breakdown voltage (BV) and the specific on-resistance (). For a given pillar width and n-drift thickness, there exists a proper range of n-drift concentration (N), in which the SD-D-semi-SJ MOSFET could exhibit a better trade-off of –BV compared to the predication of SJ MOSFET in the forward applications. And what is much valuable, in this proper range of N, the desired BV and good trade-off could be achieved only by determining the pillar thickness, with the top assist layer thickness unchanged. Detailed analyses have been carried out to get physical insights into the intrinsic mechanism of –BV improvement in SD-D-semi-SJ MOSFET. These results demonstrate a great potential of SD-D-semi-SJ MOSFET in reverse applications. [ABSTRACT FROM AUTHOR]

Negative bias temperature instability (NBTI) has become a serious reliability issue, and the interface traps and oxide charges play an important role in the degradation process. In this paper, we study the recovery of NBTI systemically under different conditions in the P-type metal–oxide–semiconductor field effect transistor (PMOSFET), explain the various recovery phenomena, and find the possible processes of the recovery. [ABSTRACT FROM AUTHOR]