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Plasma damage to low k dielectric materials was investigated from a mechanistic point of view. Low k dielectric films were treated by plasma Ar, O2, N2/H2, N2 and H2 in a standard RIE chamber and the damage was characterized by Angle Resolved X-ray Photoelectron Spectroscopy (ARXPS), X-Ray Reflectivity (XRR), Fourier Transform Infrared Spectroscopy (FTIR) and Contact Angle measurements. Both carbon depletion and surface densification were observed on the top surface of damaged low k materials while the bulk remained largely unaffected. Plasma damage was found to be a complicated phenomenon involving both chemical and physical effects, depending on chemical reactivity and the energy and mass of the plasma species. A downstream hybrid plasma source with separate ions and atomic radicals was employed to study their respective roles in the plasma damage process. Ions were found to play a more important role in the plasma damage process. The dielectric constant of low k materials can increase up to 20% due to plasma damage and we attributed this to the removal of the methyl group making the low k surface hydrophilic. Annealing was generally effective in mitigating moisture uptake to restore the k value but the recovery was less complete for higher energy plasmas. Quantum chemistry calculation confirmed that physisorbed water in low k materials induces the largest increase of dipole moments in comparison with changes of surface bonding configurations, and is primarily responsible for the dielectric constant increase. [ABSTRACT FROM AUTHOR]

The packaging process can increase the driving force for interfacial delamination and significantly impacts the reliability of the low k chip. In this study we investigated the packaging effect due to die attach process where a high thermal load occurs during solder reflow before underfilling. With the high thermal load and without the underfill, the chip-package interaction is maximized and can become most detrimental to low k chip reliability. Both SiLK and MSQ dielectrics were investigated to examine the influence of low k properties on packaging reliability. In addition to different low k dielectrics, we investigated the effects due to the substrate material, die size and solder materials, including the lead-free solder. The packaging effect was found to be higher for flip-chip packages with lead-free solder than the eutectic lead solder and the high lead solders. Flip-chip packages with a ceramic substrate were found to have a smaller packaging effect than that with a plastic substrate. Increasing die size increases the crack driving force for low k interfacial delamination, as expected. Packaging effect was generally lower for the Cu/MSQ structure than for the Cu/SiLK structure, and the difference can be attributed to the higher Young’s modulus of the MSQ material. © 2006 American Institute of Physics [ABSTRACT FROM AUTHOR]

The weak mechanical properties of porous low-k dielectric materials raise a major reliability concern for implementation into on-chip interconnects. Mechanical properties of the conventional template-type materials deteriorate with increasing porosity due to the formation of open pores and pore channels during template evaporation. For this reason, NCS (Nano-Clustering Silica) which is a non-template type of porous material was developed as a low-k dielectric for the 65nm technology node and beyond. The NCS material has an elastic modulus higher than 10 GPa because only closed pores are formed and the pore size do not change during the curing process. This paper investigated the fracture behavior of the NCS material using four point bending and DCB (Double Cantilever Beam) tests to measure interfacial fracture energy and sub-critical crack growth rate. Crack formation was found to occur via cohesive fracture with cracks mainly confined within the matrix. The effect of curing on the molecular structure of NCS was investigated using Fourier Transform Infrared (FTIR) spectroscopy. The results indicated that the fracture energy can be correlated to the ratio of the Si-O-Si cage structure to the network structure, which in turn is related to the elastic modulus of the NCS material. © 2006 American Institute of Physics [ABSTRACT FROM AUTHOR]

Electromigration (EM) failure statistics and the origin of the lognormal standard deviation (σ) for Cu interconnects have been investigated by analyzing the statistics of lifetime and void size distributions at various stages during EM testing. Experiments were performed on 0.18μm wide, single damascene Cu interconnects with tests terminated after certain amounts of resistance increase, or after a specified test time. Void size distributions of resistance-based and time-based EM tests were obtained. The σ values of lifetime and void size distributions showed a significant decrease with increasing resistance failure criterion. The statistics of resistance-based void size distributions can be explained by considering geometrical variations of the void shape, while the characteristics of time-based void size distributions require consideration of kinetic aspects of the EM process. The σ values of EM lifetime distributions can be adequately simulated by combining the statistics of both types of void size distributions. Thus, using simulation to fit the experimental data, the parameters influencing the EM lifetime statistics were identified as variations in void sizes, geometrical and experimental factors of the EM test and kinetic aspects of the mass transport process, such as differences in interface diffusivity between the lines. The variation in diffusivities at the cathode ends of the lines are a result of varying Cu grain orientations. Furthermore, the analysis of the EM statistics of samples with a reduced line height and dual damascene processing will be presented. © 2006 American Institute of Physics [ABSTRACT FROM AUTHOR]

Three-dimensional finite element simulations were used to model stress relaxation due to diffusion along interfaces in a damascene copper interconnect structure. By fitting the predicted stress relaxation rates to the available experimental results, we have identified the interfaces that contribute to stress relaxation in the structure, and have estimated values for their diffusion coefficients. © 2004 American Institute of Physics [ABSTRACT FROM AUTHOR]

Electromigration (EM) failure statistics and the origin of the lognormal standard deviation (σ) for Copper (Cu) interconnects have been investigated by analyzing the statistics of EM lifetime and void size distributions at various stages during EM testing. Experiments were performed on 0.18μm wide Cu interconnects with tests terminated after certain amounts of resistance increases, or after a specified test time. Void size distributions of resistance-based, as well as time-based EM tests were obtained using focused ion beam (FIB) microscopy. The lifetime and void size distributions were found to follow lognormal distribution functions. The σ values of EM lifetime and time-based void size distributions decrease with higher percentages of resistance increase, reaching an asymptotic value of σ ∼ 0.14. In contrast, σ values of resistance-based void size distributions are significantly smaller and do not show an obvious dependence on time. The statistics of resistance-based void size distributions can be accounted for by considering geometrical variations of the void shape, while the characteristics of time-based void size distributions require consideration of kinetic aspects of the EM process. The σ values of EM lifetime distributions can be adequately simulated from experimentally obtained void size distributions, including geometrical and experimental factors of the EM experiment as well as kinetic aspects of the mass transport process, such as differences in interface diffusivity between the lines. The variation in diffusivities at the cathode ends of the lines arises from differences in the interface structure as a result of varying Cu grain orientations. © 2004 American Institute of Physics [ABSTRACT FROM AUTHOR]

The continual downward scaling of devices and increases in drive current have required an ever shrinking interconnect pitch and higher current densities. In order to overcome both the higher signal delay, as well as reliability concerns, new metallization technologies like Cu interconnects and low-k interlevel dielectrics have been developed. The implementation of inlaid Cu interconnects introduces a new set of material systems and geometries which results in new mass transport and failure mechanisms under electromigration. This study focuses on the characterization and understanding of electromigration-induced failures in advanced, 0.13 μm technology node Cu interconnects. Statistically based methodologies, using multi-link test structures, were developed and used to further understand the reliability of these advanced interconnects. Single-inlaid structures designed to test both the upper and lower interfaces associated with a Cu via were used to understand the role of void formation and interconnect geometry in EM behavior. These statistical methodologies were also applied to EM tests on dual-inlaid test structures in order to understand the impact of a continuous via-metal connection on void formation including the potential for multiple failure modes. Dual-inlaid integrations of varying maturity levels were examined to highlight the advantages of the statistically based methodology in determining extrinsic failure modes as well as increasing the confidence of EM lifetime prediction. © 2004 American Institute of Physics [ABSTRACT FROM AUTHOR]