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The family of 2D chalcogenide semiconductors has been growing rapidly. Metal monochalcogenides, for instance, can enable new possibilities in functional electronics and optoelectronics. A Gallium Selenide (GaSe) thin flake is used to fabricate a back gated field effect transistor (FET) with n‐type conduction behavior and wide hysteresis at the ambient conditions. The device shows high mobility up to 28 cm2 V−1 s−1 with Ion/Ioff ratio over 103. Under the laser exposure, the device shows a decrease in the threshold voltage and a left‐shift of the transfer characteristic with a slight increase in the current. The transfer characteristic exhibits a hysteretic behavior with hysteresis width linearly dependent on the applied gate voltage. Moreover, the GaSe‐based FET shows a photo response with a photoresponsivity of 475 mAW−1 and detectivity of 4.6 × 1012 Jones. The photocurrent rise and decay times are 0.1 and 1.3 s, respectively. Furthermore, the GaSe FET device can be used as a performant memory device with well separated states and memory window enhanced by the laser exposure, confirming an optoelectronic memory class. [ABSTRACT FROM AUTHOR]

With field effect transistor (FET) sustained to downscale to sub‐10 nm nodes, performance degradation originates from short channel effects (SCEs) degradation and power consumption increment attributed to inhibition of supply voltage (VDD) scaling down proportionally caused by thermionic limit subthreshold swing (SS) (60 mV dec−1) pose substantial challenges for today's semiconductor industry. To further sustain the Moore's law life, incorporation of new device concepts or new materials are imperative. 2D materials are predicted to be able to combat SCEs by virtue of high carrier mobility maintainability regardless of thickness thinning down, dangling bonds free surface and atomic thickness, which contributes to super gate electrostatic controllability. To overcome increasing power dissipation problem, new device structures including negative capacitance FET (NCFET), tunnel FET (TFET), dirac source FET (DSFET) and the like, which show superiority in decreasing VDD by lowering SS below thermionic limit of 60 mV dec−1 have been brought out. The combination of 2D materials and ultralow steep slope device structures holds great promise for low power‐dissipation electronics, which encompass both suppressed SCEs and reduced VDD simultaneously, leading to improved device performance and lowered power dissipation. [ABSTRACT FROM AUTHOR]

Ionic FETs have enormous potential for energy conversion, sensing, and ionic circuits due to their efficient regulation of the nanochannel. Here ionic FETs based on single‐crystal silicon nanopores and the rectification of the fabricated devices are studied. The electrical characterization results demonstrated that since the silicon‐based nanopores have the advantage of modulating the surface charge due to their semiconductor nature and benefitting from the effective 3D gating effect on the nanochannel, the magnitude and polarity of surface charge can be modulated by the gate voltage. The rectification effect can be adjusted by applying a certain voltage and fulfilling a transition between anion selectivity and cation selectivity when the surface charge polarity is reversed. Moreover, current–voltage characteristics of the reported ionic FET can be switched between ohmic and diode‐like regimes. The proposed ionic FETs supply a novel platform to study the ionic properties and have great potential to be applied in large‐scale ionic circuits due to their excellent performance. Finally, simulation results prove the surface charge modulated by the gate voltage determines the magnitude and direction of rectification, which is consistent with the reported experiment result. [ABSTRACT FROM AUTHOR]

High‐quality liquid gate‐all‐around (LGAA) silicon nanowire (NW) field‐effect transistor (FET) biosensors are fabricated and studied their properties in 1 mm phosphate‐buffered saline solution with pH = 7.4 using transport and noise spectroscopy. At small VDS, the conventional current behavior of FET with a linear dependence on voltage is registered in the output current‐voltage (I‐VM) characteristics with M = 1. At drain‐source voltage VDS > 0.6 V, the I‐V characteristics with stronger power M are revealed. It is shown that the current in LGAA NW FETs follows current proportional to voltage in power M = 4 dependence on small liquid gate voltages. Transport and noise spectroscopy analyses demonstrate that the obtained results are associated with the space‐charge‐limited current (SCLC) effect. Moreover, a strong two‐level random telegraph signal (RTS) is found in the region corresponding to SCLC at VDS values exceeding 0.6 V. The RTS related to single trap phenomena results in a well‐resolved Lorentzian component of noise spectra. The results demonstrate that the SCLC and two‐level RTS phenomenon are correlated effects. They should be taken into account during the development of single‐trap‐based devices, including biosensors. [ABSTRACT FROM AUTHOR]

Rhenium disulfide (ReS2) is a type of transition metal dichalcogenides (TMDs) that has potential electronic and photoelectrical applications. However, limited research has been conducted on improving its electrical properties and understanding the effect of doping on ReS2‐based devices. In this study, the enhanced electrical and photoelectrical performance of a 2D/0D heterostructure constructed by decorating the In2O3 quantum dots (QDs) on a multilayer ReS2 field‐effect transistor (FET) is reported. The In2O3 QDs are characterized by using a transmission electron microscope, optical absorption, and photoluminescence spectroscopy. The n‐doping effects with improved mobility are clearly observed, which is attributed to the electron transfer induced by the relatively high conduction band level of In2O3 QDs. Owing to the channel migration of ReS2 and traps at the ReS2/In2O3 QDs interface, additional performance improvements are observed, including reduced contact resistance, improved subthreshold swing, and increased photoresponsivity; however, the photoresponse speed is decreased. In summary, the findings suggest a novel mixed‐dimensional heterostructure for enhancing the performance of ReS2 transistors and provide insights into doping‐induced channel migration for 2D materials. [ABSTRACT FROM AUTHOR]

Proposals for new architectures that shorten the length of the transistor channel without the need for high‐end techniques are the focus of very recent breakthrough research. Although vertical and electrolyte‐gate transistors are previously developed separately, recent advances have introduced electrolytes into vertical transistors, resulting in electrolyte‐gated vertical field‐effect transistors (EGVFETs), which feature lower power consumption and higher capacitance. Here, EGVFETs are employed to study the charge transport mechanism of spray‐pyrolyzed zinc oxide (ZnO) films to develop a new photosensitive switch concept. The EGVFET's diode cell revealed a current‐voltage relationship arising from space‐charge‐limited current (SCLC), whereas its capacitor cell provided the field‐effect role in charge accumulation in the device's source perforations. The findings elucidate how the field effect causes a continuous shift in SCLC regimes, impacting the switching dynamics of the transistor. It is found ultraviolet light may mimic the field effect, i.e., a pioneering demonstration of current switching as a function of irradiance in an EGVFET. The research provides valuable insights into the charge transport characterization of spray‐pyrolyzed ZnO‐based transistors, paving the way for future nano‐ and optoelectronic applications. [ABSTRACT FROM AUTHOR]

The learning accuracy of neuromorphic computing that mimics the biological brain, is affected by the conductance‐modulation characteristics of an artificial synapse. In ferroelectric‐based devices, these characteristics are implemented using a distribution of polarization values. Therefore, the distribution in a ferroelectric thin film with various external voltage signals is investigate. As polarization switching proceeds with voltage pulse, the domains of the switched polarization become larger. In ferroelectric‐gate field effect transistors, the channel layer assumed to lie beneath the ferroelectrics experiences a local conductance change, according to the polarization distribution of the ferroelectric layer. It is found that small clusters with high conductivity become large clusters in the channel layer as the polarization switching proceeds. When the additional pulses are applied, the high conductive regions eventually connect (i.e., percolate) in the channel layer and the conductance of the layer is greatly increased. Adjusting the height of the applied voltage can slow down or speed up this phenomenon. Also, the nanosecond voltage pulses are employed and the width of the conductive pathway is adjusted. It enables to fine‐tune the conductance of the channel layer. It demonstrates that conductance modulation is optimized with an appropriate voltage pulse train pattern. [ABSTRACT FROM AUTHOR]

The piezoelectronic transistor (PET) has been proposed to overcome the voltage and clock speed limitations of conventional field‐effect transistors (FET). In a PET, voltage is transduced to stress, which leads to an insulator‐metal transition in a piezo‐resistive (PR) element. Although the simulated switching speeds are promising, the viable candidates proposed so far for the PR layer are rare earth compounds that require several GPa of pressure (P) to metalize, necessitating breakthroughs in transduction mechanism scaling and processing. Here, a PR candidate that metalizes in the 0–300 MPa range – the transition metal complex platinum benzoquinonedioximato (Pt(bqd)2) is demonstrated. Such electrical sensitivity to the application of P arises when the material is grown as a thin film with the preferred needle orientation perpendicular to the substrate. As evidence, a combination of hydrostatic and uniaxial pressure studies is provided. The former studies are produced on the compressed powder pellet in a specially developed piston‐cylinder cell (P‐C cell) under variable temperatures (T) and P. The latter is via thin film deposition and uniaxial resistivity (ρ) measurements and these revealed the high potential of this material for the PET concept. [ABSTRACT FROM AUTHOR]

This year marks the 20th anniversary of the discovery of LaAlO3/SrTiO3 (LAO/STO) oxide heterointerfaces. Since their discovery, transition metal oxide (TMO) interfaces have emerged as a fascinating and fast‐growing area of research, offering a variety of unique and exotic physical properties which has provided a strong impetus for the rapid advances and actualization of oxide electronics. This review revisits the fundamental mechanisms accounting for the two‐dimensional (2D) conducting interfaces, and how new models proposed to better account for the unique interfacial effects. Recent breakthroughs in the theoretical and experimental domains of oxide interfaces are also discussed including the detection and investigation of 2D quasiparticle. Moving beyond the well‐known LAO/STO interface, this review delves into other systems where unconventional interfacial superconductivity, interfacial magnetism, and spin polarization are dealt with in greater detail. In terms of device applications, this review proceeds with a treatment on the recent developments in domains including field effect transistors and freestanding heterostructure membranes. By emphasizing the opportunities and challenges of integrating oxide interfaces with existing technologies, the review will end off with an outlook projecting the progress and the trajectory of this research domain in the years to come. [ABSTRACT FROM AUTHOR]

Carbon nanotube (CNT) field effect transistors (CNFETs) show promise for the next generation VLSI systems due to their excellent scalability, energy efficiency, and speed. However, high leakage current is a drawback of large diameter CNTs (diameter (DCNT) ≥ 1.4 nm) due to the small electronic band gap (EG) ≤ 0.6 eV and effective mass. This work investigates the on‐current and off‐current tradeoff for two populations of semiconducting‐enriched CNT with DCNT ≈ 1.0 nm displaying a simultaneous 50x improvement in minimun current (IMIN) with 2.5x degradation in contact resistance compared to DCNT ≈ 1.4 nm using a Pd side‐bonded contact. A method to enhance the performance of low‐leakage CNFETs is demonstrated using sub‐monolayer self‐aligned contact doping with 0.8 nm of MoOX, which delivers a 57% reduction in contact resistance to DCNT ≈ 1.0 nm. Robustness is verified after annealing at 200 °C for 30 min and monitoring stability across 6 months post‐fabrication with no change in electrical behaviors. [ABSTRACT FROM AUTHOR]

In this work, bottom‐up Al–Si–Al nanowire (NW) heterostructures are presented, which act as a prototype vehicle toward top‐down fabricated nanosheet (NS) and multi‐wire (MW) reconfigurable field‐effect transistors (RFETs). Evaluating the key parameters of these transistors regarding the on‐ and off‐currents as well as threshold voltages for n‐ and p‐type operation exhibit a high degree of symmetry. Most notably also a low device‐to‐device variability is achieved. In this respect, the investigated Al–Si material system reveals its relevance for reconfigurable logic cells obtained from Si NSs. To show the versatility of the proposed devices, this work reports on a combinational wired‐AND gate obtained from a multi‐gate RFET. Additionally, up‐scaling the current is achieved by realizing a MW RFET without compromising reconfigurability. The Al–Si–Al platform has substantial potential to enable complex adaptive and self‐learning combinational and sequential circuits with energy efficient and small footprint computing paradigms as well as for native components for hardware security circuits. [ABSTRACT FROM AUTHOR]

Large, open‐gate transistors made from metal nanoparticle arrays offer possibilities to build new electronic devices, such as sensors. A nanoparticle necklace network (N3) of Au particles from 300 K to cryogenic temperatures exhibit a nonohmic I–Vd behavior, I ≈ (Vd–VT)ζ, where VT is a conduction gap and ζ is a constant critical exponent. The conduction gap in N3, made from disordered networks of 1D chains of 10 nm diameter Au particles exhibits room temperature (RT) gating. Although the I–Vd behavior at RT is identical to Coulomb blockade, the conduction is modulated by field‐assisted tunneling exhibiting classical critical behavior. In this study, based on three results, invariance of VT on gating, invariance of VT on temperature, and zero–bias conductance, a sharp transition temperature at ≈140 K is discovered where the conduction mechanism switches from Coulomb blockade to classical critical percolation behavior. The N3 architecture allows the reconciliation of the Coulomb blockade versus activation process as a sharp thermal transition to serve as a model system to study the exotic behavior in nanogranular‐metallic materials. The novel global critical behavior to local Coulomb blockade governed transition in these N3 architectures may potentially lead to novel sensors and biosensors. [ABSTRACT FROM AUTHOR]

The rapid development of 2D magnetic materials has opened new possibilities in the field of spintronics. CrTe2, a 2D material with perpendicular magnetic anisotropy (PMA) and ferromagnetic transient temperature near room temperature, holds promise for various applications. However, the underlying mechanism responsible for its global magnetism remains unclear. This work focuses on investigating the magneto‐transport properties of ultra‐thin CrTe2 Field Effect Transistor (FET) under the influence of top gate biases. The application of gate voltage ranging from 25 to −15 V tunes its coercivity (HC) and Curie temperature (TC) (from 152 to 191 K). Notably, a linear correlation is observed between the TC and the hole concentration (np1/3$n_{\mathrm{p}}^{1/3}$) in the CrTe2 film, indicating the involvement of the Ruderman–Kittel–Kasuya–Yosida interaction. This experimental analysis sheds light on the mechanism of the CrTe2's ferromagnetism and paves the way for future advancements and applications in this material. [ABSTRACT FROM AUTHOR]

In this study, the domain switching mechanism of ferroelectric HZO thin films is investigated by analyzing the bulk charge of a graphene field‐effect transistor with an HZO dielectric device by using a pulsed IV measurement method. The domain switching speed, which is generally difficult to observe from a typical DC‐IV analysis of metal‐oxide‐semiconductor field‐effect transistors using a parameter analyzer, is investigated via the fast pulsed IV analysis method. Based on the measurements, most of the ferroelectric HZO domains are fast switched within 100 ns; however, domains that require a longer switching time in the order of 1 ms are also identified. Short pulses can be continuously applied to minimize the influence of other domains that are not switched by the switched domain. The feasibility of partial switching of the domains, which can be utilized for the multi‐functional operation of ferroelectric HZO devices, is observed. The results suggest that further investigation of the physical properties of slow‐switching domains is necessary to develop future synaptic array applications. [ABSTRACT FROM AUTHOR]

The study demonstrates HfZrOx (HZO)‐based Si ferroelectric field‐effect transistors (FeFETs) with a low operating voltage (1.5 V) and immediate read‐after‐write operation (100 ns) via HZO thickness scaling, electron‐beam‐irradiation (EBI) treatment, and interfacial layer (IL) scavenging. With these three strategies, reduced operating voltage, immediate read‐after‐write capability, and improved endurance (>108 cycles) and retention (extrapolated 10‐year) characteristics are achieved in FeFETs. The improved characteristics of FeFETs are attributed to the reduced operating voltage by HZO thickness scaling, the ferroelectric orthorhombic phase‐oriented crystallization by EBI treatment, and the reduced gate voltage drop across the IL and reduced depolarization field by the IL scavenging. It is believed that this work contributes to the development of low‐power and fast‐read FeFETs. [ABSTRACT FROM AUTHOR]

A reconfigurable logic‐in‐memory (R‐LIM) cell performs logic‐in‐memory functions as well as reconfigurable logic gates. The R‐LIM cell is constructed with triple‐gated (TG) feedback field‐effect transistors (FBFETs) that are reconfigured in n‐channel or p‐channel modes via electrostatic doping. Each TG FBFET has one control gate electrode and two program‐gate electrodes that determine the channel mode. Their reconfigurability enables the symmetrical operation of the n‐channel and p‐channel modes through an on‐current ratio of 1:04. Furthermore, the R‐LIM cell performs eight Boolean logic operations, storing the logic outputs for ≈100 s under zero‐bias conditions. The R‐LIM cell is useful for developing in‐memory computing systems with high energy efficiency and functional logic. [ABSTRACT FROM AUTHOR]

Large‐area monolayer graphene is utilized as a metallic electrode for a ferroelectric single‐crystal [Pb(Mg1/3Nb2/3)O3]m–[PbTiO3]n (PMNPT). Unlike conventional metal, whose properties remain unaffected by field‐induced charge carriers, graphene's unique Dirac‐cone band structure causes its carrier density to vary in response to the polarization state of contacting dielectrics. PMNPT capacitors with graphene‐only and graphene/Cr/Au electrodes exhibit similar polarization versus electric‐field curves. However, polarization switching in PMNPT and corresponding charge‐state conversion in the graphene electrode are observed in the device configuration of a graphene‐ferroelectric field‐effect transistor. Systematic analysis of graphene's source‐drain current variation reveals that experimental results align well with a theoretical model considering the intrinsically doped state in graphene and ferroelectric surface charge state in PMNPT. Furthermore, interfacial charge trapping discussed in many previous reports is not observed. These findings suggest that large‐area monolayer graphene effectively serves as an electrode for ferroelectric single‐crystal materials, irrespective of its atomically thin structure and ambipolar metallic nature. [ABSTRACT FROM AUTHOR]

2D transition metal dichalcogenides such as molybdenum disulfide (MoS2) are promising candidates for flexible electronics because of their bandgap tunability, high carrier mobility, and mechanical flexibility. However, flexible MoS2 field effect transistors (FETs) are typically faced with high contact resistance which is identified as a critical limiting factor to their potential applications. The present work successfully addresses this challenge by using Al contacts without any annealing process. It is found that the contact resistance is strongly coupled to the Al thickness, increasing the Al thickness is beneficial to reduce the contact resistance. The observed variation in the device electrical characteristics can be associated with the formation of the natural aluminum oxide (AlxOy) film at the interface. An ultrathin Au insert layer can further advance the device performance. An optimal contact resistance of 2.03 kΩ and an on/off current ratio of 1.57 × 109 can be achieved in the flexible MoS2 FETs using Au/Cr/Al/Au as source/drain electrodes. Furthermore, no apparent degradation in the device properties is observed under systematic cyclic bending testing with bending radii of 18 and 15 mm. The successful integration of Au/Cr/Al/Au source/drain electrodes into MoS2 FETs promises its potential application in flexible electronic devices. [ABSTRACT FROM AUTHOR]

Abstract Large‐area monolayer graphene is utilized as a metallic electrode for a ferroelectric single‐crystal [Pb(Mg1/3Nb2/3)O3]m–[PbTiO3]n (PMNPT). Unlike conventional metal, whose properties remain unaffected by field‐induced charge carriers, graphene's unique Dirac‐cone band structure causes its carrier density to vary in response to the polarization state of contacting dielectrics. PMNPT capacitors with graphene‐only and graphene/Cr/Au electrodes exhibit similar polarization versus electric‐field curves. However, polarization switching in PMNPT and corresponding charge‐state conversion in the graphene electrode are observed in the device configuration of a graphene‐ferroelectric field‐effect transistor. Systematic analysis of graphene's source‐drain current variation reveals that experimental results align well with a theoretical model considering the intrinsically doped state in graphene and ferroelectric surface charge state in PMNPT. Furthermore, interfacial charge trapping discussed in many previous reports is not observed. These findings suggest that large‐area monolayer graphene effectively serves as an electrode for ferroelectric single‐crystal materials, irrespective of its atomically thin structure and ambipolar metallic nature.

Metal‐semiconductor field‐effect transistor (MESFET) devices based on pulsed laser deposition (PLD) grown In2O3 thin films with on–off ratios exceeding 6 orders of magnitude and low sub‐threshold swing values close to the thermodynamic limit are reported. Oxygen plasma treatment and compensation doping with Mg are utilized to suppress the accumulation of electrons at the surface of In2O3, which is a major obstacle for its use as an active material in electronic devices. The influence of both methods is investigated on the electrical properties of thin films as determined by Hall effect measurements on samples of varying film thickness. Using the performance of vertical Schottky barrier diodes as a benchmark, fundamental plasma parameters such as input power and background gas pressure are optimized. [ABSTRACT FROM AUTHOR]

2D MoTe2 is regarded as a favorable candidate for semiconductor nanoelectronics integration. Chemical‐vapor‐deposition‐grown MoTe2 usually presents p‐type characteristics. In order to realize basic electronic units like complementary metal‐oxide‐semiconductor (CMOS) inverter, controllable fabrication of p‐ and n‐type transistors at large scale is of vital importance. Here, large‐scale MoTe2 n‐channel field‐effect transistor (n‐FET) arrays are successfully fabricated with seamless coplanar metallic 1T′‐WTe2 contacts to reduce contact resistance. High‐k HfO2 serves as a gate dielectric and its atomic‐layer‐deposition (ALD) process causes an n‐doping effect on the 2H‐MoTe2 channel. The FETs perform typical n‐type characteristics with average electron density and on/off ratio of ≈1.7 × 1013 cm−2 and 2.1 × 104, respectively. Furthermore, large‐scale homogeneous CMOS inverter arrays are fabricated, showing clear logic swing with low power consumption (≈0.4 nW) and high device yield (≈92%). Notably, their voltage transfer characteristics exhibit small hysteresis, and they work well after being kept in air for 16 months, indicating high device stability. The statistical results show that both the n‐FETs and CMOS inverters have high uniformity and reliability in performance. Significantly, this fabrication method is free from transfer processes and compatible with traditional silicon technology. This work paves the way for the application of few‐layer MoTe2 in semiconductor nanoelectronics integration. [ABSTRACT FROM AUTHOR]

Optoelectronic sampling is the ultimate method to perform ultra‐high frequency analog‐to‐digital conversion. Thanks to the ps photo‐thermo‐bolometric effect in high mobility hexagonal boron nitride (h‐BN) encapsulated graphene, a state‐of‐the‐art optoelectronic sampler over a 40 GHz bandwidth using a 4 ps pulsed laser is demonstrated. The superior transport and optoelectronic linearities of this graphene sampler lead to very high harmonic rejections below –43 dB above 20 GHz. With a physics‐based microscopic model, it is shown that harmonics are generated by optoelectronics saturation effects and only appear when carrier energy reaches that of optical phonons, which is very high in h‐BN encapsulated graphene. This device is the first ultra‐fast optoelectronic sampler based on the bolometric effect. [ABSTRACT FROM AUTHOR]

Abstract Metal‐semiconductor field‐effect transistor (MESFET) devices based on pulsed laser deposition (PLD) grown In2O3 thin films with on–off ratios exceeding 6 orders of magnitude and low sub‐threshold swing values close to the thermodynamic limit are reported. Oxygen plasma treatment and compensation doping with Mg are utilized to suppress the accumulation of electrons at the surface of In2O3, which is a major obstacle for its use as an active material in electronic devices. The influence of both methods is investigated on the electrical properties of thin films as determined by Hall effect measurements on samples of varying film thickness. Using the performance of vertical Schottky barrier diodes as a benchmark, fundamental plasma parameters such as input power and background gas pressure are optimized.

Abstract 2D MoTe2 is regarded as a favorable candidate for semiconductor nanoelectronics integration. Chemical‐vapor‐deposition‐grown MoTe2 usually presents p‐type characteristics. In order to realize basic electronic units like complementary metal‐oxide‐semiconductor (CMOS) inverter, controllable fabrication of p‐ and n‐type transistors at large scale is of vital importance. Here, large‐scale MoTe2 n‐channel field‐effect transistor (n‐FET) arrays are successfully fabricated with seamless coplanar metallic 1T′‐WTe2 contacts to reduce contact resistance. High‐k HfO2 serves as a gate dielectric and its atomic‐layer‐deposition (ALD) process causes an n‐doping effect on the 2H‐MoTe2 channel. The FETs perform typical n‐type characteristics with average electron density and on/off ratio of ≈1.7 × 1013 cm−2 and 2.1 × 104, respectively. Furthermore, large‐scale homogeneous CMOS inverter arrays are fabricated, showing clear logic swing with low power consumption (≈0.4 nW) and high device yield (≈92%). Notably, their voltage transfer characteristics exhibit small hysteresis, and they work well after being kept in air for 16 months, indicating high device stability. The statistical results show that both the n‐FETs and CMOS inverters have high uniformity and reliability in performance. Significantly, this fabrication method is free from transfer processes and compatible with traditional silicon technology. This work paves the way for the application of few‐layer MoTe2 in semiconductor nanoelectronics integration.

The reconfigurable feedback field‐effect transistors (R‐FBFETs) with a double‐gated structure are designed and the logic and memory operations of a logic‐in‐memory (LIM) inverter comprising two R‐FBFETs are investigated. The R‐FBFETs exhibit an extremely low subthreshold swing of ≈1 mV dec−1, a high on/off current ratio of ≈107, and a long retention time of 10 s, owing to a positive feedback loop mechanism. The on‐current ratio of the p‐ to n‐channel modes is 1.03, which indicates a high degree of reconfigurability. The LIM inverter retains the output logic "1" and "0" states for over 50 s under zero‐bias conditions. The symmetric reconfigurable switching and memory operations of the R‐FBFETs enable the LIM inverter to perform logic and memory operations for a long retention time without a power supply. [ABSTRACT FROM AUTHOR]

This study reports the optoelectronic characterization of few‐layer ReSe2field effect transistors at different pressures. The output curves reveal dominant n‐type behavior and a low Schottky barrier at the metal contacts. The transfer curves show a significant hysteresis that can be exploited in memory devices with an order ofmagnitude memory window and good cycling. The devices are dramatically affected by air pressure; their conductance and mobility increase with the lowering pressure that desorbs electronegative air molecules from the surface of the material. The photoresponse under white super‐continuum laser illumination reveals that the device exhibits positive photoconductivity (PPC) at ambient and low (≈1 mbar) pressure and negative photoconductivity (NPC) in a higher vacuum (≈10−4 mbar). The transition from PPC to NPC can be explained by considering that the photoresponse is affected by molecule desorption, which yields PPC at higher pressure, and defect trapping of photogenerated carriers, which can dominate at lower pressures. The transient behavior of the device exposed to laser pulses shows a faster response and a higher photodetection efficiency at ambient pressure, with the highest signal‐to‐noise ratio at the valley of the transfer curve between p‐ and n‐type conduction. [ABSTRACT FROM AUTHOR]

The development of field‐effect transistor‐based (FET‐based) non‐volatile optoelectronic memories is vital toward innovations necessary to improve computer systems. In this work, for the first time, the unique charge‐trapping and charge‐retention properties of solution‐processed colloidal nitrogen‐doped carbon quantum dots (CQDs) are harnessed to achieve functional optoelectronic memories programmable by UV illumination with a multilevel writing possibility. Of particular note, long‐lasting memory function can be achieved thanks to the vast charge trapping sites provided by the N‐doped CQDs and the resultant photo‐gating effect is exercised on the graphene FET. The achieved memory can be erased by a positive gate bias which provides sufficient carriers to remove trapped charges through recombination. This study highlights the possibility to engineer high‐performance all‐carbon non‐volatile FET‐based optoelectronic memories through manipulating and coupling the charge‐trapping properties of colloidal CQDs and graphene. [ABSTRACT FROM AUTHOR]

Spin‐polarized conducting edge currents counterpropagate in quantum spin Hall (QSH) insulators and are protected against disorder‐driven localizations by the time‐reversal symmetry. Using these spin‐currents for device applications requires materials with a large bandgap and fast switchable QSH states. By means of in‐depth first‐principles calculations, this study demonstrates the large bandgap and fast switchable QSH state in a newly introduced 2D material family with 1T′‐MGe2Z4 (M = Mo or W and Z = P or As). These Ge‐based compounds show superior properties with respect to other members of the same family. For the WGe2As4 monolayer it can stabilize the 1T′‐phase, while for the other members of the family, this study needs an appropriate strain. The dynamically stable 1T′‐MGe2Z4 monolayers have a large energy gap up to 237 meV for WGe2As4. These materials undergo a phase transition from a QSH insulator to a trivial insulator with a Rashba‐like spin splitting under the influence of an out‐of‐plane electric field, demonstrating a fast tunability of the bandgap and its band topology for the Ge‐based compounds. Fast topological phase switching in a large gap 1T′‐MGe2Z4 QSH insulators have potential applications in low‐power devices, quantum computation, and quantum communication. [ABSTRACT FROM AUTHOR]

Due to the complicated relationship between wearable electronics performance and various parameters, months even years are needed to obtain a desired sensor by random and time‐consuming trial‐and‐error methods. Herein, a general analytic model based on the micro‐element division and equivalent circuit is presented to guide a rapid optimizing strategy for wearable resistive pressure sensors, which is like the method always used in the traditional design of the metal‐oxide‐semiconductor field‐effect transistor for integrated circuits. The quantitative relationship between the sensitivity and related parameters is declared in the presented model, and the optimized parameters are achieved to design a sensor. The demanded ultra‐highly sensitive pressure sensor is successfully designed and optimized in minutes based on the built model, and the fabricated sensor is applied in a voice real‐time recognition system to obtain 100% recognition accuracy. The on‐demand and agile development strategy paves a promising way to greatly accelerate the transition from random and time‐consuming to the controllable design of wearable electronics. [ABSTRACT FROM AUTHOR]

The large‐scale synthesis of high‐purity semiconducting single‐walled carbon nanotubes (s‐SWCNTs) plays a crucial role in fabricating high‐performance and multiapplication‐scenario electronics. This work develops a straightforward, continuous, and scalable method to synthesize high‐purity and individual s‐SWCNTs with small‐diameters distribution (≈1 nm). It is believed that the water and carbon dioxide resulting from the decomposition of isopropanol act as oxidizing agents and selectively etch metallic SWCNTs, hence enhancing the production of s‐SWCNTs. The performance of individual‐SWCNTs field effect transistors confirms the high abundance of s‐SWCNTs, presenting a mean mobility of 376 cm2 V−1 s−1 and a high mobility of 2725 cm2 V−1 s−1 with an on‐current to off‐current (Ion/Ioff) ratio as high as 2.51 × 107. Moreover, thin‐film transistors based on the as‐synthesized SWCNTs exhibit excellent performance with a mean mobility of 9.3 cm2 V−1 s−1 and Ion/Ioff ratio of 1.3× 105, respectively, verifying the enrichment of s‐SWCNTs. This work presents a simple and feasible route for the sustainable synthesis of high‐quality s‐SWCNTs for electronic devices. [ABSTRACT FROM AUTHOR]

In this study, the authors fabricate Sn‐doped 100‐nm thick polycrystalline β‐Ga2O3 synaptic field‐effect transistors (FETs) emulating optical and electrical spike stimulation. When stimulated by deep ultraviolet (UV) optical spikes or electric voltage spikes at the gate, the devices exhibit several essential synaptic functions of excitatory‐postsynaptic currents (EPSCs), inhibitory‐postsynaptic currents (IPSCs), paired‐pulse facilitation (PPF), spike‐number‐dependent plasticity (SNDP), and spike‐timing‐dependent plasticity (STDP). Following UV optical stimulation, the devices mimic synaptic plasticity with a photogate effect, and the gate voltage stimulation emulates the synaptic weights according to the state of the gate dielectric interface. The β‐Ga2O3 synaptic FET demonstrates synergistic functions in various optoelectronic stimulation modes and successfully mimics the visual memory formation in bees with UV photoreceptors. Moreover, to verify the translation of optoelectrical‐derived synaptic behaviors of β‐Ga2O3 synaptic FETs into artificial neuromorphic computing, handwritten digit image recognition of the Modified National Institute of Standards and Technology dataset is performed using a convolutional neural network, and a learning accuracy of 96.92% is achieved. The realization of these fundamental functions of biological synapses suggests the utility of Ga2O3‐based optoelectronic devices for next‐generation neuromorphic computing. [ABSTRACT FROM AUTHOR]

The deposition of high‐quality dielectric films on graphene surfaces is crucial in fabricating high‐performance graphene‐based electronics. In this study, the first application of UV‐assisted atomic layer deposition (UV‐ALD) to graphene surfaces and the fabrication of graphene field‐effect transistors (GFETs) with UV‐ALD Al2O3 dielectric thin films is demonstrated. Optimal UV irradiation (5 s per cycle) during the ALD process results in denser and smoother Al2O3 dielectric films deposited on the graphene surface with the intimate graphene‐dielectric interface, while excessive UV irradiation in turn prohibits the film nucleation. As a result, the GFETs with a high‐quality dielectric layer deposited by UV‐ALD show improved performance with a Dirac voltage close to 0 V and hole mobility of 1221 cm2 V−1 s−1, i.e., > 200% increase compared to those with thermal ALD. This study demonstrates that UV‐ALD is an effective and simple option to realize a high‐quality interface between 2D materials and ultra‐thin dielectric films. [ABSTRACT FROM AUTHOR]

Semiconducting molybdenum ditelluride (MoTe2) is widely reported owing to its favorable electronic and optoelectronic properties. The effective modulation of its electrical characteristics has garnered growing attention in regard to building high‐performance MoTe2‐based complementary devices. However, the inherent Schottky barrier (SB) in MoTe2‐based devices severely inhibits the charge‐carrier injection efficiency, leading to a high contact resistance between MoTe2 and contact metals. Here, an efficient method is presented for reducing the SB height of field‐effect transistors (FETs) based on MoTe2 by in situ potassium modification. Interestingly, the electrons transported from K continuously change the electrical characteristics of MoTe2 FET from ambipolar to n‐type with an improvement of electron mobility of over one order of magnitude. Meanwhile, the contact resistance of MoTe2 FET is significantly decreased from 11.5 to 0.4 kΩ µm. By regulating the modification region spatially, it is possible to create a complementary inverter with a high gain of ≈32 at VDD = 3 V. This research demonstrates a relatively simple method for optimizing the contact for MoTe2‐based devices and tuning the electrical properties of MoTe2 for future high‐performance complementary electronics. [ABSTRACT FROM AUTHOR]

Reconfigurable field‐effect transistors, capable of being dynamically programmed during run‐time, overcome the static nature of conventional complementary metal‐oxide semiconductors by reducing the transistor count and the circuit path delay. Thereby, SiGe and Ge are predicted to boost drive currents, switching speed and to reduce power consumption. Nevertheless, Ge‐based reconfigurable field‐effect transistor prototypes have so far fallen short in reaching both the promised performance due to interface instability to their contacts and gate oxides, as well as in reaching the current–voltage symmetry necessary for circuit applicability. Here, a top‐down fabricated SiGe‐based reconfigurable transistor technology is reported that is comprised of a vertical Si‐Si0.67Ge0.33 heterostructure enabling the envisioned high and symmetric on‐currents of both n‐ and p‐type operation. Monolithic integration with single‐elementary crystalline Al contacts alleviates process variability compared to conventional Ni‐silicide/Ni‐germanide contacts and introduces an ultra‐thin Si interlayer providing stability and equal injection efficiency of holes and electrons. The implementation of a three top‐gate transistor in combination with a hysteresis‐free Si/SiO2/HfO2 gate stack enhances polarity control and leakage current suppression to limit static power dissipation. Importantly, the obtained Al‐Si‐SiGe multi‐heterojunction and advanced reconfigurable transistor design is the first Ge‐based technology showing the envisioned stability and performance enhancements. [ABSTRACT FROM AUTHOR]

Downscaling the semiconductor into ultrathin film is of vital importance to high‐performance field–effect transistors (FETs), but the high‐mobility FETs based on conjugated polymer monolayers have been rarely realized. Especially, the lack of high‐performance n‐type polymer monolayer FETs hinders the development of complementary integrated circuits. Herein, by fine‐tuning the supramolecular assembly of two thiazole flanked naphthalene diimide‐based conjugated polymers, the ≈2.5 nm‐thick monolayers with well‐defined fibrillar morphology are grown in a controllable way, where the one‐dimensional solution‐state structures are inherited. The resultant monolayer FETs show the electron mobility up to 0.25 cm2 V−1 s−1, among the record for n‐type polymer monolayer FETs. More importantly, the first demonstration of polymer monolayer complementary integrated circuits is present, and a record‐high inverter gain of 113 is achieved, which is also identical to the best polymer thin‐film inverters. [ABSTRACT FROM AUTHOR]

The authors demonstrate improved switching voltage, retention, and endurance properties in HfZrOx (HZO)‐based n/p‐ferroelectric field‐effect transistors (FeFETs) via oxygen scavenging. Oxygen scavenging using titanium (Ti) in the gate stack successfully reduce the thickness of interfacial oxide between HZO and Si and the oxygen vacancy at the bottom interface of the HZO film. The n/p‐FeFETs with scavenging exhibit an immediate read‐after‐write with stable retention property and improved endurance property. In particular, n‐FeFET with scavenging exhibits excellent endurance property that does not show breakdown up to 1010 cycles. The charge trapping model in the n/p‐FeFETs is presented to explain why the effect of oxygen scavenging is more pronounced in n‐FeFET than in p‐FeFET. Finally, further switching voltage scaling potential is estimated by scavenging and HZO thickness scaling. It is believed that this work contributes to the development of low‐power FeFET and the understanding of FeFET operation. [ABSTRACT FROM AUTHOR]

A novel SnO/SnS heterojunction grown by pulsed laser deposition for the fabrication of high‐performance transistors with changeable polarity is described in this study. It is worth noting that the operating mode of a vertical heterojunction transistor can be switched from p‐type to ambipolar to n‐type by growing SnS with a different thickness on SnO with ambipolarity. The p‐type mobility could reach 1.77 cm2 V−1 s−1 and the switching ratio could reach 1517. The ambipolar transistor shows a V‐type transfer curve with electron channel mobility and hole mobility, respectively. The cross‐sectional transmission electron microscopy of the heterojunction interface reveals a high level of quality, which explains the method by which the working mode of the heterojunction changes. In addition, complementary metal‐oxide‐semiconductor (CMOS) inverters are successfully used with p‐type SnO transistors, n‐type SnO/SnS transistors, and ambipolar transistors. This work proposes a novel approach to preparing CMOS electrical components, as well as a new working mode for transistors, that are both simple and efficient. [ABSTRACT FROM AUTHOR]

Conjugated semiconducting polymers are key active materials for printable electronics, sensors and biosensors, organic photovoltaics, organic light emitting devices, and more. The research in the field developed very efficient materials and sound structure property relationships, thus making a case for a transition from laboratory to industrial environment. At this critical juncture, sustainability, and ease of scaling up are at least as important as performances, to the point that efficient materials on a lab scale could become unpractical for the industry. The development of more efficient synthetic protocols and the complete removal of all organic solvents from both the synthesis and the processing of semiconducting polymers can help tremendously to improve sustainability and reduce costs. It is shown that the use of an aqueous dispersion of the food grade surfactant lecithin as the medium, enables the synthesis and processing of the representative semiconducting alternating copolymer poly (9,9‐dioctylfluorene‐alt‐bithiophene) (PF8T2) in high yield and high quality and with transistor performances comparable with those obtained with reference materials synthetized and processed from volatile organic solvents. [ABSTRACT FROM AUTHOR]

The combination of graphene and silicon in hybrid electronic devices has attracted increasing attention over the last decade. Here, a unique technology of graphene‐on‐silicon heterostructures as solution‐gated transistors for bioelectronics applications is presented. The proposed graphene‐on‐silicon field‐effect transistors (GoSFETs) are fabricated by exploiting various conformations of channel doping and dimensions. The fabricated devices demonstrate hybrid behavior with features specific to both graphene and silicon, which are rationalized via a comprehensive physics‐based compact model which is purposely implemented and validated against measured data. The developed theory corroborates that the device hybrid behavior can be explained in terms of two independent silicon and graphene carrier transport channels, which are, however, strongly electrostatically coupled. Although GoSFET transconductance and carrier mobility are found to be lower than in conventional silicon or graphene field‐effect transistors, it is observed that the combination of both materials within the hybrid channel contributes uniquely to the electrical response. Specifically, it is found that the graphene sheet acts as a shield for the silicon channel, giving rise to a nonuniform potential distribution along it, which impacts the transport, especially at the subthreshold region, due to non‐negligible diffusion current. [ABSTRACT FROM AUTHOR]

A method of using non‐volatile and fast ferroelectric field‐effect transistor (FeFET) devices to realize Boolean logic is proposed. First, the internal states are initialized. Then, the gate and body function as input terminals, which are used to write the states of the device, based on the voltage. Finally, the output signals can be easily read through the drain current. Of the 10 Institute of Electrical and Electronics Engineers (IEEE) standard logic gates, eight can be implemented using the proposed operation method alone and by following the definitions listed herein. Thus, to enable FeFET devices to act as functional logic gates, a simple operating method is proposed, providing substantial contributions to the development of computing in memory. The experimental results provide evidence of the efficacy of this method. [ABSTRACT FROM AUTHOR]

In this study, the logic‐in‐memory operations are demonstrated of ternary NAND and NOR logic gates consisting of double‐gated feedback field‐effect transistors. The component transistors reconfigure their operation modes into n‐ or p‐channel modes by adjusting the gate biases. The highly symmetrical operation between these operation modes with an excellent on‐current ratio of 1.03 enables three distinguishable and stable logic levels in the ternary logic gates. Moreover, the ternary logic gates maintain the three logic states for several tens to hundreds of seconds under zero‐bias condition. This study demonstrates that the ternary logic gates are promising candidates for next‐generation low‐power computing systems. [ABSTRACT FROM AUTHOR]

Two‐dimensional transition metal dichalcogenides (TMDCs) demonstrate great potential in nanoelectronics devices owing to their high carrier mobility in the atomically thin channel regime. However, high contact resistance between source/drain electrodes and TMDC channels hinders the TMDCs applications in the very‐large‐scale integration (VLSI) field. Here, this work reports atomically aligned van der Waals (vdW) junction fabrications through thermal‐induced crystallization of layered Sb2Te3 electrodes on monolayer MoS2 using VLSI‐compatible physical vapor deposition and annealing processes. Due to Fermi‐level unpinning with a small band offset between Sb2Te3 and MoS2 and small density of state of Sb2Te3, better device performance is demonstrated on MoS2 MOSFETs with Sb2Te3/W contact than that of Sb/W contact. Moreover, the ideal vdW junctions are found to demonstrate extreme high‐thermal robustness. No intermixing at the Sb2Te3/MoS2 interface or crystallinity degradation of Sb2Te3 is observed after 450 °C annealing, leading to higher thermal stability than its Sb counterpart. Sb2Te3 is a promising candidate as an n‐type contact material for TMDC‐based devices such as MoS2, MoSe2, and WS2 in future VLSI electronics and various other applications. [ABSTRACT FROM AUTHOR]

Black phosphorus (BP) receives extensive attention in many fields such as energy storage, microelectronics, and optoelectronics due to its layer‐controlled direct bandgap, excellent carrier mobility, and unique anisotropy. However, in practical applications, atmospheric degradation and the random channel orientation make the actual performance of BP much lower than the theoretical value. Here, clean and complete BP nanosheets with large size and high crystal quality are obtained by poly(dimethylsiloxane)‐assisted mechanical exfoliation. Then, angle‐resolved polarized Raman spectroscopy is used to distinguish the armchair (AC) orientation of BP and a field‐effect transistor (FET) with controllable channel direction can improve the carrier mobility of the device (up to 826.2 cm2 V−1 s−1) because of higher mobility along the AC orientation. Due to the tunneling of electrons through the electron barrier into the conduction band of BP under a positive gate voltage, the transistor possesses a bipolar transport property. In addition, with the change of channel thickness, both the impurity scattering of the substrate and the interlayer resistance will affect the movement of carriers, so the carrier mobility of the device increases first and then decreases with the increase of the channel thickness. [ABSTRACT FROM AUTHOR]

Diamond exhibits large application potential in the field of power electronics, owing to its excellent and desirable electronic properties. However, the main obstacles to its development originate from the small‐sized single‐crystal wafers and the instability of the electrical conductivity. This work presents a metal‐oxide‐semiconductor field‐effect transistor (MOSFET) on a diamond substrate derived from a five‐inch (110) highly preferred polycrystalline diamond film. The MOSFETs with excellent performance are fabricated by combining an H‐terminated channel and an epitaxially grown boron‐doped layer as the source/drain contacts of the diamond devices. According to the electrical statistical results of ≈110 devices on the polycrystalline diamond substrate, 44% of devices show normally‐off operation with a maximum current density of 400 mA mm−1, while 56% of devices demonstrate normally‐on operation with a maximum current density of 525 mA mm−1. The normally‐off characteristics are more related to the higher amounts of nitrogen concentration than the grain boundaries. The stable boron‐doped source and drain provide a high concentration of holes, which facilitate transport in the surface p‐type channel induced by the H‐termination. The characteristics of the MOSFETs are inspiring for the fabrication of complementary inverter circuits on large diamond wafers. [ABSTRACT FROM AUTHOR]

Developing Ohmic contact systems or achieving low contact resistance is significant for high‐performance semiconductor devices. This work comprehensively investigates the interfacial properties of CrX2N4 (X = C, Si) based field‐effect transistors (FETs) with different metal (Ag, Au, Cu, Ni, Pd, Pt, Ti, and graphene) electrodes by using electronic structure calculations and quantum transport simulations. It is highlighted that the stronger interlayer coupling allows CrC2N4 to form an n‐type Ohmic contact with Ti electrode in the vertical direction. Furthermore, the absence of tunneling barrier at the CrC2N4–Ti interface greatly improves the electron injection efficiency. On the other hand, the studied metals form Schottky contact with CrC2N4 at the lateral interface due to Fermi level pinning (FLP) effects. Surprisingly, the strong FLP effects restrict the Schottky barrier heights of CrSi2N4‐metal contacts to a narrow range. Where Ag, Au, Ni, Pd, Pt, Ti electrodes and Ag, Ti electrodes form ideal ohmic contact with CrSi2N4 in the vertical and lateral directions, respectively, while the other metals form quasi‐ohmic contact. Ti exhibits the highest contact performance as the electrode in both CrC2N4 and CrSi2N4 based FETs. The findings may provide fundamental understanding for designing high‐performance and energy‐efficient FETs based on CrX2N4. [ABSTRACT FROM AUTHOR]

Recently, 2D materials have been intensively investigated for their novel nanoelectronic applications; among these materials, tungsten diselenide (WSe2) is attracting substantial research interest due to its high mobility, sizable bandgap, and ambipolar characteristics. However, Fermi‐level pinning (FLP) at the metal–semiconductor contact is a critical issue preventing further integration of WSe2 to complementary metal–oxide–semiconductor (CMOS) technology. In this study, a facile doping method of oxygen (O2) plasma treatment and an aging effect to overcome the FLP of WSe2 field‐effect transistors (FETs) are utilized. After aging, a reduction is observed in FLP on oxidized WSe2 FETs, along with a decrease in pinning factor (S) for holes from −0.06 to −0.36. Further, the field‐effect mobility of high‐ (Pd) and low‐ (In) work‐function contacted WSe2 devices indicates the presence of more improvement in high‐work‐function metal‐contacted p‐type WSe2 FETs, which further strengthens the Fermi level de‐pinning behavior attributed to the O2 plasma and aging processes. The existence of different tunneling behaviors of Pd and In devices also confirms the effect of O2 plasma doping into WSe2 FETs. Ultimately, this work demonstrates a simple and efficient method for achieving the de‐pinning of Fermi‐levels and modulating FLP of 2D FETs. [ABSTRACT FROM AUTHOR]

Abstract The development of field‐effect transistor‐based (FET‐based) non‐volatile optoelectronic memories is vital toward innovations necessary to improve computer systems. In this work, for the first time, the unique charge‐trapping and charge‐retention properties of solution‐processed colloidal nitrogen‐doped carbon quantum dots (CQDs) are harnessed to achieve functional optoelectronic memories programmable by UV illumination with a multilevel writing possibility. Of particular note, long‐lasting memory function can be achieved thanks to the vast charge trapping sites provided by the N‐doped CQDs and the resultant photo‐gating effect is exercised on the graphene FET. The achieved memory can be erased by a positive gate bias which provides sufficient carriers to remove trapped charges through recombination. This study highlights the possibility to engineer high‐performance all‐carbon non‐volatile FET‐based optoelectronic memories through manipulating and coupling the charge‐trapping properties of colloidal CQDs and graphene.

Abstract The combination of graphene and silicon in hybrid electronic devices has attracted increasing attention over the last decade. Here, a unique technology of graphene‐on‐silicon heterostructures as solution‐gated transistors for bioelectronics applications is presented. The proposed graphene‐on‐silicon field‐effect transistors (GoSFETs) are fabricated by exploiting various conformations of channel doping and dimensions. The fabricated devices demonstrate hybrid behavior with features specific to both graphene and silicon, which are rationalized via a comprehensive physics‐based compact model which is purposely implemented and validated against measured data. The developed theory corroborates that the device hybrid behavior can be explained in terms of two independent silicon and graphene carrier transport channels, which are, however, strongly electrostatically coupled. Although GoSFET transconductance and carrier mobility are found to be lower than in conventional silicon or graphene field‐effect transistors, it is observed that the combination of both materials within the hybrid channel contributes uniquely to the electrical response. Specifically, it is found that the graphene sheet acts as a shield for the silicon channel, giving rise to a nonuniform potential distribution along it, which impacts the transport, especially at the subthreshold region, due to non‐negligible diffusion current.

Abstract Two‐dimensional transition metal dichalcogenides (TMDCs) demonstrate great potential in nanoelectronics devices owing to their high carrier mobility in the atomically thin channel regime. However, high contact resistance between source/drain electrodes and TMDC channels hinders the TMDCs applications in the very‐large‐scale integration (VLSI) field. Here, this work reports atomically aligned van der Waals (vdW) junction fabrications through thermal‐induced crystallization of layered Sb2Te3 electrodes on monolayer MoS2 using VLSI‐compatible physical vapor deposition and annealing processes. Due to Fermi‐level unpinning with a small band offset between Sb2Te3 and MoS2 and small density of state of Sb2Te3, better device performance is demonstrated on MoS2 MOSFETs with Sb2Te3/W contact than that of Sb/W contact. Moreover, the ideal vdW junctions are found to demonstrate extreme high‐thermal robustness. No intermixing at the Sb2Te3/MoS2 interface or crystallinity degradation of Sb2Te3 is observed after 450 °C annealing, leading to higher thermal stability than its Sb counterpart. Sb2Te3 is a promising candidate as an n‐type contact material for TMDC‐based devices such as MoS2, MoSe2, and WS2 in future VLSI electronics and various other applications.

Abstract Developing Ohmic contact systems or achieving low contact resistance is significant for high‐performance semiconductor devices. This work comprehensively investigates the interfacial properties of CrX2N4 (X = C, Si) based field‐effect transistors (FETs) with different metal (Ag, Au, Cu, Ni, Pd, Pt, Ti, and graphene) electrodes by using electronic structure calculations and quantum transport simulations. It is highlighted that the stronger interlayer coupling allows CrC2N4 to form an n‐type Ohmic contact with Ti electrode in the vertical direction. Furthermore, the absence of tunneling barrier at the CrC2N4–Ti interface greatly improves the electron injection efficiency. On the other hand, the studied metals form Schottky contact with CrC2N4 at the lateral interface due to Fermi level pinning (FLP) effects. Surprisingly, the strong FLP effects restrict the Schottky barrier heights of CrSi2N4‐metal contacts to a narrow range. Where Ag, Au, Ni, Pd, Pt, Ti electrodes and Ag, Ti electrodes form ideal ohmic contact with CrSi2N4 in the vertical and lateral directions, respectively, while the other metals form quasi‐ohmic contact. Ti exhibits the highest contact performance as the electrode in both CrC2N4 and CrSi2N4 based FETs. The findings may provide fundamental understanding for designing high‐performance and energy‐efficient FETs based on CrX2N4.