Search

This paper gives an overview on the key features of the several building blocks constituting modern nomadic systems. Different micro-power energy harvesting techniques are described and discussed. In addition, this paper reviews the state of the art and provides recently published examples of low power low voltage analog circuits, such as operational amplifiers, reference generators, and data converters.

In this paper, we extend the traditional 3-moduli set {2n, 2n − 1, 2n+1}, with an equivalent 3n-bit dynamic range, and propose a moduli set extension with a maximum dynamic range of 9n and improve the parallelism according to the requirements. This paper also introduces a novel moduli set to design efficient reverse converters by using modular operations of the form 26n − 1 in order to achieve at most 9n-bit. Experimental results suggest that area reductions up to 65.61% and speed up of 2.38 can be obtained with our proposal in comparison with the best solutions existing in the state-of-the-art with the same DR. The proposed converter allows fewer bits per channel in comparison with the most efficient solutions with smaller dynamic ranges.

This paper shows the design of a wearable device for measuring vital signs, oriented to monitoring applications and home health care. In order to improve the living conditions of the patient, device allows that the patient can perform their daily activities while their health is monitored. The designed device allows measuring electrocardiogram, blood oxygen saturation, non-invasive blood pressure and heart rate. This paper proposes a novel technique to reduce motion artifacts based on signals measurement redundantly, also the importance at clinic level of measuring these variables is shown. The device transmits the information wirelessly to a proprietary application for viewing, the result of used technique for reducing artifacts is shown and a prototype of the device is presented. Finally, the advantages and future improvements of the wearable monitor are discussed.

Controllers based on Synchronous Finite State Machines (SFSM) are widely used in the control unit design of complex digital systems. These systems can present serious problems related to the global clock. In this context, the asynchronous paradigm shows interesting features that fit as an alternative for the design, despite of the difficulties of the application of asynchronous logic. An interesting architecture for the Asynchronous Finite State Machines Asynchronous (AFSM) is based on local clock, because it reduces the requirements of asynchronous logic. This paper proposes a new architecture of local clock to AFSMs, which is described by a popular specification known as Extended Burst-Mode (XBM). This architecture has a better cycle time when compared to other local clock architectures. Also, the paper proposes a "necessary and sufficient" condition for the local clock AFSMs on the proposed architecture to be synthesized completely by the use of conventional tools. Through a case study, we present the architecture, its robustness, the synthesis procedure and compare it with other local clock architectures, highlighting its advantages.

In this paper we have developed an ultrafast pulse generator to turn on a Single Photon Avalanche Diode (SPAD) sensor with picosecond resolution, at specific time windows. The pulse amplitude and duration is user tunable to provide a variable excess bias voltage to the detector. The transition times (rise and fall time) of the pulse is in the range of 250 to 550 ps depending on the amplitude. The generator was designed to be applied in reflectance optical spectroscopy measurements where the diffusive medium is illuminated from a point source and diffused photons are collected at a given distance from the source. To increase the sensitivity to higher penetration depth of investigation, the source and the detector separation should be small which in turn increases the number of unwanted early arriving photons. This system will keep the detector off for the first 500–600ps, thus rejecting the early arriving photons, and will only turn-ON the detector when it is expected to detect the late photons coming from the deeper regions. The proposed fully CMOS integrated system is the first of its kind to be introduced for the ultra-fast gating of the single photon detectors.

This paper enhances SWARM, a novel deterministic analog layout automation approach based on the idea of cellular automata. SWARM implements a decentralized interaction model in which responsive layout modules, covering basic circuit types, autonomously move, rotate and deform themselves to let constraint-compliant, compact layout solutions emerge from a synergetic flow of self-organization. With the ability to consider design constraints both implicitly and explicitly, SWARM joins the layout quality of procedural generators with the flexibility of optimization algorithms, combining these two kinds of automation into a “bottom-up meets top-down” flow. The new enhancements are demonstrated in an OTA example, depicting the power of SWARM and its enormous potential for future developments.

This paper presents a MOS-only high power supply rejection (PSRR) voltage reference with a very low temperature coefficient (TC) that consumes only tens of nano-Watt. It is composed by a threshold voltage monitor circuit with no resistors, cascaded with a thermal voltage generator, adequate for fabrication in standard processes. Since the MOS transistors operate in subthreshold and near-threshold regimes the current consumption is very low. The operation of the circuit is analytically described and a design methodology is proposed. Post-layout simulations for a design in a 130 nm CMOS process are presented, resulting a reference voltage around 670 mV with a best case TC of 1.5 ppm/°C for the −40 to +125 °C range and an average TC of 20 ppm/°C over process variations, untrimmed. A very low sensitivity to VDD is achieved, resulting a PSRR lower than −71 dB at 100 Hz and a line sensitivity (LS) lower than 576 ppm/V for a supply range from 1 to 3 V. The area is very small, 0.0084 mm2 including the start-up stage.

A self-biased current buffer based on the quasi floating gate (QFG) approach to achieve class AB operation is presented in this paper. It was designed in standard 0.18μm CMOS process with 1.8V power supply. The buffer is able to copy an input current range of ±15μA with 8μA bias current. The total harmonic distortion (THD) remains below −84dB for 1 kHz frequency and maximum input current Ipp = 30pA. A comparison with two other class AB architectures in terms of input and output impedances, THD, bandwidth, accuracy and static and dynamic power consumption is also presented.

In this paper a complete implementation and design of a fully-synthesized 32-bit microcontroller in a 130nm CMOS technology is presented. This is the first microcontroller featuring the open source RISC-V instruction set all mounted through AXI4-Lite and APB buses for communication process. The microcontroller contains a 10-bit SAR ADC, a 12-bit DAC, an 8-bit GPIO module, a 4kB-RAM, an SPI AXI slave interface for output verification, and an SPI APB slave interface for checking the correct behavioral of the APB bridge. All peripherals are controlled by a RISC-V and an SPI AXI master interface that is used for programming the device and checking the data flowing through all the slaves. A total power density is reported as 167μW/MHz and the area for this RISC-V microcontroller has a reduced footprint of 798μm×484μm.

This paper presents a strategy for implementing the discrete time version of the Nonlinear Energy Operator (NEO). The proposed implementation approach is based on the utilization of a circuit that produces an output current proportional to the square of its input voltage, which we call transconductor-squarer circuit. In order to avoid adverse effects of mismatch between circuits that should be identical, we propose the reuse of a single transconductor-squarer circuit for the realization of the NEO formula. The NEO system was evaluated simulating its ability to emphasize the presence of neural spikes in a synthetic noisy extracellular neural signal. The circuit is designed aiming at a standard CMOS fabrication process with 90nm minimum channel length and its circuit simulation shows energy consumption of 60pJ per spike. Simulations also show that the circuit is capable of operating at about 30 Ksample/s, compatible with current state-of-the-art neural recording systems.

Field Programmable Gate Arrays (FPGAs) are successful platforms for the implementation of communication systems, due to their potential high throughput and low development costs. In such systems, however, investigating the system's resilience to soft errors is crucial in many scenarios, such as when facing stringent dependability constraints or when operating in radiation-harsh environments. Therefore, in this paper we present a fault injection platform that targets specifically FPGA-based communication systems. The platform operates partially on the device and partially on a host computer, aiming at both flexibility and high performance. A Reed-Solomon decoder is used as a case study to validate the platform, showing its ability to measure metrics that are relevant both for critical systems (e.g., fault sensitivity) as well as for communication systems in general (e.g., bit error rate).

This paper presents the development of a biotelemetry system comprising a microcontrolled sensing unit and a reading unit. Through the magnetic coupling between the coils of an inductive link, the reading unit is able to provide power and establish data communication with the sensing unit. A signal generator and a current driver in the reading unit allow energy transfer to the sensing unit, which has a microcontroller that performs the signal acquisition of a temperature sensor and sends the resulting digital data to the reading unit by means of a LSK modulator. The ASK demodulator of the reading unit retrieves the data that is processed by another microcontroller, which provides the measurement result to a computer over a serial communication interface. The results showed that the sensing unit operates at a coupling distance of up to 21 mm between the sensing and reading unit coils for a 9600 bps data communication rate, whereas the maximum achieved data rate was 38400 kbps for a coupling distance of 8 mm.

This paper presents a novel architecture for capacitive sensor interfaces that is insensitive to electro magnetic interferers in hostile environments. A bridge structure, with a feedback control and a special band-pass filter, overcomes the problems that affect the standard approaches. Behavioural level simulations demonstrate the feasibility of the idea for 12-bit resolution.

When a DC voltage source supplies energy to an electric load, it can operate either for maximum power transfer and low efficiency (50%), or with an acceptable efficiency with less power transferred. In this paper an analytic expression is developed and used to quantify this trade off. Moreover, this expression is validated by an experimental circuit demonstrator.

Traditional synthesis flows dedicated to design ASICs typically adopt standard cells approach to generate VLSI circuits. As a consequence, the layouts of these circuits are not fully optimized due to the restricted number of cells present in the library. To solve this problem, ASTRAN, an open source automatic synthesis tool, was developed. This tool generates layouts with unrestricted cell structures and obtains results with similar density compared to state-of-the-art alternatives. A key step on the ASTRAN flow is the transistor folding, which consists in breaking the transistors that exceed the height limit defined in the project rules. This step is executed in ASTRAN only into single transistors. This paper addresses this issue and introduces a new folding methodology that identifies all stacks of transistors series and applies the folding technique for each of these arrangements. The results obtained through this new folding technique show reductions in cell area.

This paper presents an investigation regarding the model adopted by a commercial layout extraction tool to estimate the aspect ratio (W/L) of enclosed layout transistors (ELT). The method used by the EDA (Electronic Design Automation) tool to obtain an equivalent W/L is compared with well know mathematical models presented on the literature. The influences in the aspect ratio estimation regarding designer-controlled layout variables are also target of investigation. Results indicate that the EDA tool analyzed in this work, overestimates the extraction of aspect ratio from ELT layout, when compared with a more accurate mathematical model used to calculate the effective aspect ratio of square ELT devices. The results also show that designer-controlled layout variables may contribute to increase the divergences among the extraction tool method and the studied models in the estimation of the ELT aspect ratio.

This paper proposes a 2.2 GHz CMOS Power Amplifier (PA) useful to S-Band applications with an effective 3-bit output power control for efficiency improvement. It uses an input transformer to reduce ground bounce effects and operates around 1 W of output power. A tuned driver stage provides impedance matching to the input signal source and proper gain to the next stage. A control stage is used for efficiency improvement, composed by four parallel branches where the state (on or off) of 3 branches is separately activated by a 3-bit input. The classE power stage uses a cascode topology to minimize the voltage stress over the power transistors, allowing higher supply voltages. The PA was designed in a 130 nm RF process and post-layout simulations resulted a peak output power of 28.5 dBm with a maximum power added efficiency (PAE) around 47% under 3.3 V of supply voltage. The 3-bit control allows a total output power dynamic range adjustment of 12.4 dB, divided in 8 steps, with the PAE changing from 13.4% to 47.3%.

This paper proposes an architecture of a conditioning circuit for dual-modality wire-mesh sensors, applied to multiphase flow measuring. The proposed circuit topology uses an AC-based impedance measurement technique, and is able to process signals from a 4×4 wire-mesh structure, performing an I/Q demodulation for the direct extraction of fluid permittivity and conductivity values. System-level considerations are taken into account to derive the requirements for the main circuit blocks, which are aimed to be integrated on standard CMOS technology.

Wireless body area networks have recently gained attention, mainly after the IEEE 802.15.6 standard had been proposed. Reviewing the literature, we easily recognize that several authors use different terminologies for a single concept or a single terminology for different concepts. This generates confusion and blocks fair comparisons between systems. In this paper, we present an overview of Wireless Body Area Networks (WBAN) with focus on the applications. Moreover, we propose a detailed taxonomy that could help to disambiguate the confusion regarding current WBAN terminology.

In this paper we will demonstrate the implementation of a low-dropout hybrid regulator (LDO) that includes a continuous to discrete time feedback loop, in a 28 nm TSMC CMOS technology. The proposed LDO will be given an apriori signal to differentiate between low and high load current states. This mixed mode design is scalable ensuring the best regulation at different load currents for dual or multichannel LDO designs. It has a maximum overshoot of less than 5 mV and undershoot of less than 50 mV with steady state ripple of less than 5 mV. The maximum switching transient time to steady state regulation was found by simulation to be under 830 ps.

In this paper, a high-linearity version of the zero voltage switching (ZVS) current memory cell is presented. The linearity improvement is achieved by using a high-linear differential pair and compensation switch. Higher power efficiency is also obtained by utilizing a Recycling Folded Cascode (RFC). The proposed memory cell is implemented using CMOS 0.35μm and Cadence Spectre simulations are presented to validate the improvements. The proposed structure is used to implement an integrator which achieved a DC gain of 89.44 dB.

This paper presents the simulation results of a linear, fully integrated, two-stage digitally programmable 130 nm CMOS power amplifier (PA) operating at 2.4 GHz. Its power stage is composed of a set of amplifying cells which can be enabled or disabled independently by a digital control circuit. All seven operational modes are univocal in terms of 1 dB output compression point (OCP1dB), saturated output power (PSAT) and power gain at 2.4 GHz. The lowest power mode achieves an 8.1 dBm Psat, a 13.5 dB power gain and consumes 171 mW DC power (Pdc) at an OCPmb of 6 dBm, whereas the highest power mode reaches an 18.9 dBm Psat and a 21.1 dB power gain and consumes 415 mW Pdc at an OCPmb of 18.2 dBm.

This paper presents HF-RISC, a 32-bit RISC processor, along with its associated programming toolchain. The instruction set architecture of the processor is based on MIPS I and its hardware organization comprises three pipeline stages. The processor was synthesized in four different technology nodes for maximum frequency and simulated using CoreMark, an industry-standard performance evaluation benchmark. Using data obtained from synthesis and benchmarking we analyze the processor performance and compare it to similar commercial products. Obtained results indicate that HF-RISC is a good option for embedded design, as it presents performance figures similar to state-of-the-art ARM processors. Furthermore, its partially reconfigurable hardware organization allows the designer to explore performance and area trade offs.

Current mirrors are important basic building blocks of analog electronic circuits. In this paper graphene field effect transistor (GFET) based basic and cascode current mirrors are studied. Drain current equations of the GFET model are coded with Verilog-A language and integrated to SPICE simulator. DC output characteristics of current mirror circuits are analyzed and compared for both configuration with the help of simulation results. AC analysis is also performed and frequency response of the circuits are observed. The simulation results show that GFET based current mirrors can operate properly, however there are some drawbacks to overcome.

This paper presents an approach to automate MOS-Only circuit design under the polynomial regression and surface fitting. The proposed scheme incorporates a unified model, which enables to improve simulation accuracy in standard SPICE and Cadence SPECTRE simulators during the MOS-Only designs. Furthermore, a piecewise polynomial regressive model of transconductance (gm) of the MOS transistors is presented in terms of VDS, channel width (W) and channel length (L) to increase automation efficiency. Exemplary results are given at high frequency operation to validate our model in both Cadence Spectre and LT-Spice as well.

This paper investigates the problem of automatic detection of rotating-machine faults based on vibration signals acquired during machine operation. In particular, two new signal features, namely the kurtosis and entropy, are considered along with main spectral peaks to discriminate between several machine conditions: normal operation, (vertical and horizontal) misalignment, unbalanced load and bearing faults. Moreover, the inclusion of one set of three accelerometers for each roller bearing associated to the system acquiring more vibration signals also affects the generation of feature vector and is part of our proposal. In order to evaluate the rotating machine fault classification, a database of 1951 fault scenarios with several different fault intensities and rotating frequencies was designed and recorded, taking into consideration the specificities of the proposed machine learning task. The artificial neural networks recognition system employed in this work reached 95.8% of overall accuracy, showing the efficiency of the proposed approach.

This work describes a 1 Gb/s digital communication system implemented on an FPGA-based platform to investigate mixed-signal calibration techniques of time-interleaved analog-to-digital converters (TI-ADCs). Design of multi-gigabit TI-ADCs is of great interest for next generation digital communication systems such as optical coherent networks. In these applications, mismatches of the sampling time, gain, offset, and frequency response among the interleaves of a TI-ADC limit the performance of the converter unless they are compensated. Typically, long computer simulation run time is required to evaluate the performance of mixed-signal calibration algorithms. We show that the FPGA-based system described in this paper drastically reduces the emulation time by more than hundreds of magnitude orders. The proposed FPGA framework includes: (i) a diagnostic and control unit built upon an embedded processor NIOSII, (ii) DSP blocks to implement the transmitter and the receiver, and (iii) a Gaussian number generator to emulate the noise channel component. Experimental results with a 2 GS/s 6-bit CMOS TI-ADC demonstrate the excellent capability of the implemented FPGA-based emulator to evaluate the performance of a mixed-signal calibration algorithm.

This paper presents an alternative to crystal based oscillators for reference frequencies in highly integrated SoCs. The frequency reference through the usage of an active bias controlled ring oscillator operating with a supply voltage from 300 to 500 mV for an temperature from −40 to 125 ° C. The oscillator shows a very good temperature and supply voltage frequency stability coming from the active biasing using a stable current reference.

This paper addresses the problem of anomaly detection on rotating machinery in industrial environments using single channel audio signals. The proposed algorithm is based on image processing feature analysis obtained from the image representation of the Short-time Fourier Transform of reference and degraded audio signals. In order to assess the potential of the algorithm, a 8 signals database is recorded. The proposed algorithm is able to separate signals of machinery normal behavior from signals of machinery anomalous behavior with 100% hit rate using the recorded database.

This paper presents a sequential system to jointly denoise and segment an image contaminated with Gaussian noise. A fourth-order partial differential equation (PDE) filter is used for noise cancelling and particle swarm optimization (PSO) is used for segmentation. The system was tested on a chest X-ray image corrupted with different levels of Gaussian noise and, based on the Jaccard and Dice statistics, the proposed system outperformed nine other hybrid models that denoise and then segment the filtered image.

A temperature sensor used to compensate the crystal oscillator frequency instability of a real time clock (RTC) is proposed in this paper. The sensor utilizes the difference of a current proportional to the absolute temperature (PTAT) and another complementary to the absolute temperature (CTAT), generating a high-slope PTAT voltage with minimum value close to zero. The introduced approach provides a voltage signal range that reduces the power and area consumption of a 7-bit successive approximation analog-to-digital converter (SAR-ADC). The principles of the circuit topology alongside the simulation results of corners and Monte Carlo analyzes are presented. A prototype is fabricated in a 0.18 μm CMOS technology and experimental results showed a temperature inaccuracy of −0.812 to 0.266 °C, with an average resolution of 18.01 mV/°C, using a one-point calibration within the range of 0 to 40 °C. The sensor features an area of 0.08 mm2 and consumes less than 73.8 μW from a 1.8 V voltage supply.

A DC-DC switching converter, originally included to reduce the power consumption of a Wireless Sensor Networks (WSN) node, has been proposed as the core of an on-field self-energy meter. In this paper we present a method and circuit that improves the electronics proposed by previous work by conditioning the signal from the switching converter that is connected to the microcontroller's counter. A software module that allows a WSN node to measure its own charge and current consumption was also implemented. The proposed method allows to measure the current consumption in a wide range, from 0 to 30mA, is highly linear and is ultra-low-power (the maximum current consumption is 8μA). Finally, we present a case study in which the proposed method is used to power profile a WSN node. Results show that a time-based estimation (Energest) overestimates the Clear Channel Assessment consumption for more than 10%.