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In this research, a new structure and process integration for backside illuminated CMOS image sensor by using thin wafer handling technology is proposed. First of all, the wafer of a 3 Mega pixel CMOS image sensor is temporary bonded to a silicon carrier wafer with thermal plastic material and ZoneBond technology. Then the CMOS wafer is thinned down to few microns to detect the light from the backside. The backside is then permanently bonded to a glass carrier substrate with a transparent thermal set bonding material. After the glass permanent bonding process, the temporary bonded silicon carrier could be removed. Cu/Sn micro-bump is fabricated at the front-side of the CMOS image sensor, thus no TSVs are needed in the proposed structure. A 3 Mega pixel CMOS wafer with micro-bumps bonded on 500µm-thick glass wafer is demonstrated. Void-free bonding is obtained both in temporary bonding and permanent bonding processes. The thickness of the CMOS image sensor wafer is less than 10 µm after thinning and the total thickness variation is around 1 µm. Thermal plastic material is used for temporary bonding because it flows during bonding process and resulted in excellent planarization. From the cross-section SEM image, Cu/Sn micro-bump is formed at the front-side of the CMOS image sensor and the ENIG UBM is formed on the front side of the Analog-to-Digital Conversion wafer. A 3 Mega pixel image is captured and demonstrated in this research. The proposed backside illuminated CMOS image sensor structure and process integration are processed in wafer level, therefore enabling a low cost technology which can be manufactured using existing infrastructure. By using thin wafer handling technology, direct fusion bond and TSV processes are not needed which provides a low cost wafer level solution.

A novel assembly process was developed for ultra-thin chip stacking technology where wafer-level-packaging (WLP) was adopted and combined with chip-on-wafer (CoW) technology. By such assembly process, thin chip handling would be unnecessary in this process. After assembly process, chip thickness within the chip stack could be thinned down to a thickness of 30µm or less than 30µm. Sheet-type molding compound (SMC) was used to achieve the assembly of ultra-thin chip stacking module. The feasibility of this novel assembly was demonstrated and some process issues were also discussed in this investigation.

Recently, three dimensional integration circuits technology has received much attention since the demands of functionality and performance in microelectronic packaging for electronic products are rapidly increasing. For high-performance 3D chip stacking, high density interconnections are required. In the current types of interconnects, solder micro bumps have been widely adopted. For fine pitch solder micro bump joints, selections of bump height and UBM structure are the important issues that would show the significant effects on the reliability performances of solder micro bump interconnection. In this study, effects of bump height and UBM structure on the reliability properties of lead-free solder micro interconnections with a pitch of 60µm were discussed. The chip-to-chip test vehicle having more than 4290 solder micro bump interconnections with a bump pitch of 60µm was used in this study. To evaluate the effects of bump height and UBM structure on the reliability performance of micro joints, two groups of solder joint were made. The first group of micro joints had a total bump height of 29µm. In this group, Cu/Sn/Cu joint with a thickness of 7µm/15µm/7um, Cu/Sn/Ni/Cu joint having a thickness of 7µm/15µm/2µm/5µm and Cu/Ni/Sn/Ni/Cu joint with a thickness of 5µm/2µm/15µm/2um/5µm were selected. The second group of micro joints had a total bump height of 24µm. In this group, Cu/Sn/Cu joint having a thickness of 7µm/10µm/7um, Cu/Sn/Ni/Cu joint with a thickness of 7µm/10µm/2µm/5µm and Cu/Ni/Sn/Ni/Cu joint having a thickness of 5µm/2µm/10µm/2um/5µm were chosen. We used the fluxless thermocompression bonding process to form these two groups of micro joints. After bonding process, the chip stack was assembled by capillary-type underfill. Reliability tests of temperature cycling test (TCT), high temperature storage (HTS) and electromigration test (EM) were selected to assess the effect of bump height and UBM structure on the reliability properties of those two groups of solder micro bump interconnections.