1. Easing the verification bottleneck using high level synthesis
- Author
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Pradeep Thiruchelvam, Devadas Varma, and Duncan Mackay
- Subjects
Programming language ,business.industry ,Computer science ,Constrained optimization ,System testing ,computer.software_genre ,Bottleneck ,Scheduling (computing) ,Embedded system ,Formal specification ,High-level synthesis ,Circuit complexity ,business ,Hardware_REGISTER-TRANSFER-LEVELIMPLEMENTATION ,computer ,Formal verification - Abstract
As design size grows, the verification complexity grows along with the size of the design description. When design descriptions are written in RTL, the complexity of the testbenches to test this RTL are enormous. As more and more design entry moves to higher level languages such as C/C++ and System C, it's possible to write testbenches in C to verify the functionality of these high level models.
- Published
- 2010
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