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Easing the verification bottleneck using high level synthesis

Authors :
Pradeep Thiruchelvam
Devadas Varma
Duncan Mackay
Source :
VTS
Publication Year :
2010
Publisher :
IEEE, 2010.

Abstract

As design size grows, the verification complexity grows along with the size of the design description. When design descriptions are written in RTL, the complexity of the testbenches to test this RTL are enormous. As more and more design entry moves to higher level languages such as C/C++ and System C, it's possible to write testbenches in C to verify the functionality of these high level models.

Details

Database :
OpenAIRE
Journal :
2010 28th VLSI Test Symposium (VTS)
Accession number :
edsair.doi...........854e91d8736728cfa346b0f3c477e7f3
Full Text :
https://doi.org/10.1109/vts.2010.5469565