1. A 65nm C64x+ Multi-Core DSP Platform for Communications Infrastructure
- Author
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Sanjive Agarwala, Arjun Rajagopal, Anthony Hill, Mayur Joshi, Steven Mullinnix, Timothy Anderson, Raguram Damodaran, Lewis Nardini, Paul Wiley, Peter Groves, John Apostol, Michael Gill, Jose Flores, Abhijeet Chachad, Alan Hales, Kai Chirca, Krishna Panda, Rama Venkatasubramanian, Patrick Eyres, Rajasekhar Velamuri, Anand Rajaram, Manjeri Krishnan, Johnathan Nelson, Jose Frade, Mujibur Rahman, Nuruddin Mahmood, Usha Narasimha, Snehamay Sinha, Sridhar Krishnan, William Webster, Duc Bui, Shriram Moharil, Neil Common, Rejitha Nair, Rajesh Ramanujam, and Monica Ryan
- Subjects
Single chip ,Multi-core processor ,business.industry ,Code division multiple access ,Computer science ,Transistor ,Hardware_PERFORMANCEANDRELIABILITY ,law.invention ,16-bit ,CMOS ,law ,Embedded system ,Hardware_INTEGRATEDCIRCUITS ,business ,Digital signal processing ,Hardware_LOGICDESIGN - Abstract
The combined processing power of three 1+GHz DSP cores and 65nm 7M CMOS integration delivers a WCDMA macro base-station on a single chip. The 300M transistor IC can perform up to 24000MIPS, 8000 16b MMACs per second, coupled with symbol-rate and chip-rate acceleration and dissipates less than 6W.
- Published
- 2007
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