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A 65nm C64x+ Multi-Core DSP Platform for Communications Infrastructure

Authors :
Sanjive Agarwala
Arjun Rajagopal
Anthony Hill
Mayur Joshi
Steven Mullinnix
Timothy Anderson
Raguram Damodaran
Lewis Nardini
Paul Wiley
Peter Groves
John Apostol
Michael Gill
Jose Flores
Abhijeet Chachad
Alan Hales
Kai Chirca
Krishna Panda
Rama Venkatasubramanian
Patrick Eyres
Rajasekhar Velamuri
Anand Rajaram
Manjeri Krishnan
Johnathan Nelson
Jose Frade
Mujibur Rahman
Nuruddin Mahmood
Usha Narasimha
Snehamay Sinha
Sridhar Krishnan
William Webster
Duc Bui
Shriram Moharil
Neil Common
Rejitha Nair
Rajesh Ramanujam
Monica Ryan
Source :
ISSCC
Publication Year :
2007
Publisher :
IEEE, 2007.

Abstract

The combined processing power of three 1+GHz DSP cores and 65nm 7M CMOS integration delivers a WCDMA macro base-station on a single chip. The 300M transistor IC can perform up to 24000MIPS, 8000 16b MMACs per second, coupled with symbol-rate and chip-rate acceleration and dissipates less than 6W.

Details

Database :
OpenAIRE
Journal :
2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers
Accession number :
edsair.doi...........59d2db8cb12f8f4a4be0b520a75bb41e
Full Text :
https://doi.org/10.1109/isscc.2007.373394