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Multinode upset induced by radiation on integrated circuits has caused many circuit reliability issues. This article proposes a single-event quadruple-node upset (QNU) recovery latch (NEST), based on four circular feedback loops that are formed by 25 C-elements to realize high robustness. NEST achieves 29.02% reduction in power consumption compared to the latch design and algorithm-based verification protected against multiple-node upset (LDAVPM) latch and 51.44% reduction in setup time compared to the quadruple-node upset recoverable and high-impedance-state insensitive latch (QRHIL) latch. NEST also achieves a 99.29% QNU recovery rate. Furthermore, a high-speed, high-precision optimization algorithm for multinode upset recovery is also proposed and implemented. This algorithm achieves 99.84 reduction in simulation time for exhaustive fault injections having equivalent accuracy with high performance simulation program with integrated circuit emphasis (HSPICE).

As semiconductor technologies scale down, radiative-particle-induced soft errors and static power consumption are becoming major concerns for digital circuits. Magnetic-tunnel-junctions (MTJs) are widely used to address these concerns. MTJs are nonvolatile (NV) and compatible with traditional CMOS processes. In this article, we first propose a double-node-upset (DNU) tolerant and NV latch, i.e., M-TPDICE-V2, providing high reliability. In addition, we further propose an advanced latch, namely, M-8C, that is able to completely recover from single-node upsets (SNUs) and DNUs. M-8C uses a DNU recovery module and a backup and restore module based on a pair of MTJs. Furthermore, we propose a universal backup and restore module suitable for any latch providing nonvolatility. We simulate the proposed latches using the Synopsys HSPICE tool with a 45-nm CMOS process model. Simulation results confirm the superior capabilities of our proposed M-TPDICE-V2 and M-8C latches. M-TPDICE-V2 exhibits strong SNU and DNU tolerance and nonvolatility, while the M-8C latch provides complete DNU recovery capabilities.

In advanced CMOS technologies, integrated circuits are sensitive to multiple-node-upsets (MNUs) induced in harsh radiation environments. The existing verification of the reliability of latches highly relies on electronic design automation (EDA) tools considering complex error-injection scenarios. In this article, we propose a novel latch, namely, MURLAV, protected against quadruple node-upsets (QNUs) induced in harsh radiation environments, as well as an algorithmic error-recovery verification method. The latch provides complete recovery from all QNUs with a formed redundant structure. The algorithm can simplify the verification process and demonstrate the QNU recovery for the proposed MURLAV latch. Simulation results demonstrate that the proposed latch can recover from any QNU and that it has lower area and delay overhead. Compared with existing latches of the same type, the proposed MURLAV latch achieves an overhead reduction of 34% in silicon area and 15% in delay on average at the cost of moderate power consumption.

The Von-Neumann memory wall bottleneck that keeps expanding is mainly caused by the frequent data transfer between the main memory and the processor. The processing in-memory (PiM) capabilities of emerging nonvolatile devices have the potential to partially alleviate the memory wall problem. In this brief, we use the ferroelectric field-effect transistor (FeFET), one of the emerging nonvolatile devices, to design a multifunctional processing in-memory cell, namely FeMPIM. It can perform multiple logic operations in computing mode as well as content searching in ternary content-addressable memory (TCAM) mode. Simulation results demonstrate the multifunctional capability of the proposed FeMPIM as well as its moderate overhead when compared with the complementary metal-oxide-semiconductor (CMOS) based and the existing FeFET-based devices.

In deep nanoscale and highly integrated complementary metal-oxide-semiconductor (CMOS) technologies, storage circuits are increasingly sensitive to multiple-node upsets (MNUs) caused by charge sharing. In order to mitigate the impact of MNUs, many MNU-hardened latches based on C-elements matrices have been proposed by research scholars. In this article, we analyze and summarize the MNU-hardened latches based on the C-elements matrix, and propose the connection rules and general fault-tolerance principle of the looped C-element matrix. Based on this design idea, we propose a low-overhead and highly reliable quadruple-node upsets (QNUs) self-recovery latch (referred to as QR-R11C2). The proposed latch is based on a looped C-element matrix with 11 rows and 2 columns, forming a heterogeneous interconnect scheme, which can provide complete self-recovery from QNUs in harsh radiation environments. Simulation results show that the proposed latch has the lowest power consumption, area-power-delay product, and setup time among existing QNU self-recovery latches. In addition, this article also analyzes and summarizes the MNU statistics of the looped C-element matrix-based latch designs and proposes an MNU self-recoverability verification method for looped C-element matrix-based latch designs. Taking the example of verifying the self-recoverability of six looped C-element matrix-based latches, the proposed verification method can reduce MNU combinations by 95.24%–99.99% compared to the exhaustive combinations.

The entropy source structure with embedded XOR gates in a ring oscillator (RO) as a true random number generator (TRNG) can improve the speed of accumulating jitter in the oscillator. However, the XOR gate has a certain response time to the input change, and when the input changes too fast, the XOR gate will output short pulses. In this paper, we propose a TRNG design based on a multi-ring convergence oscillator (MRCO) making use of the characteristics of short pulses. We study the output of the XOR gate when facing different inputs. By modeling the time of a fibonacci ring oscillator (FIRO) as an example, we find that the loss of short pulses in an inverter chain is the reason for making the FIRO enter into periodic oscillation. This phenomenon suppresses the accumulation of jitter and occurs periodically in existing structures. Our proposed structure uses independent sub-rings to accumulate jitter, allowing the main-ring to quickly generate short pulses to provide analog randomness. The proposed TRNG design is implemented in Xilinx Virtex-6 FPGA. The experimental results show that it has the highest ratio of throughput rate to hardware resources. The generated random sequence pass both NIST SP800-22 test and NIST SP800-90B test.

Quantum-dot cellular automata (QCA) is a novel nano-electronic technology. QCA has attracted wide attention due to its extremely small feature sizes at the molecular or even atomic scale and ultra-low power consumption, making it a promising candidate to replace the complementary metal oxide semiconductor (CMOS) technology. Binary-Coded Decimal (BCD) adders are widely used in industrial computing. In this brief, we propose two types of excess-3 code (XS-3) based BCD adders (XS-3DAs). We use ripple-carry adders (RCA) and parallel binary adders (PBA) to construct XS-3DAs in QCA Designer tool, respectively. The PBA-based XS-3DA is constructed with a new correction logic. 4-bit, 8-bit, and 16-bit XS-3DAs are constructed based on the two proposed XS-3DAs, respectively. Comparisons show that, with the increase of design scaling, the delay and area-delay product (ADP) of the PBA-based XS-3DAs can be significantly reduced in comparison with that of the RCA-based XS-3DAs. Compared with the 16-digit RCA-based XS-3DA, the cell count, area, delay and ADP of the proposed 16-digit PBA-based XS-3DA are reduced by 37.88%, 25.99%, 37.68% and 53.88%, respectively.

In deep nano-scale and high-integration CMOS technologies, storage circuits have become increasingly sensitive to charge-sharing-induced multiple-node-upsets (MNUs) that include double, triple, and quadruple node-upsets. Currently, verifications for error recovery of existing latches highly rely on EDA tools with complex error-injection combinations. In this article, a latch design protected against MNUs in the harsh radiation as well as an algorithm-based verification process is proposed. Due to the constructed redundant feedback loops, the latch can completely recover from any MNU. Algorithm-based verification and simulations both demonstrate the MNU recovery of the proposed latch. Simulation results demonstrate the low area overhead of the proposed latch compared with the only one existing of the same type.

This article proposes two quadruple node upset (QNU) recoverable latches, namely QNU-recoverable and high-impedance-state (HIS)-insensitive latch (QRHIL) and QRHIL-LC (low-cost version of the QRHIL), for highly robust computing in harsh radiation environments. First, the QRHIL that mainly consists of a 5×5 looped C-element matrix is proposed. Then, to reduce overhead, the QRHIL-LC that mainly uses 24 interlocking C-elements is proposed. Both latches can self-recover from any QNU, while the QRHIL-LC has a low cost compared to the QRHIL. Simulation waveforms show the QNU-recoverability of the proposed QRHIL and QRHIL-LC latches. Moreover, compared with the QRHIL latch, the QRHIL-LC can approximately save power dissipation by 16% and silicon area by 5%.

With the continuous technology scaling of integrated circuits, storage devices are more and more easily affected by soft errors. In order to improve the reliability of storage devices and reduce overhead especially in terms of power dissipation effectively, this article proposes a soft-error-immune quadruple-node-upset tolerant latch (Quad-SIRI). The latch consists of two interlocked soft-error-immune (SIRI) SRAM cells for dual modular redundancy. Considering the characteristic of radiation-induced voltage pulse, the SIRI is designed with stacked transistors to tolerate single-node-upset and reduce sensitive nodes and area overhead. Quad-SIRI latch achieves low area overhead because of fewer transistors. Quad-SIRI latch achieves low power consumption because of clock-gating technique. However, pass transistors and stacked transistors result in small critical charge of the latch. HSPICE simulation in 22 nm CMOS technology shows that, compared with quadruple-node-upset tolerant latches (LCQNUSR, QNUTL, and 4NUHL), Quad-SIRI latch achieves the smallest delay, power and area, at the cost of smaller critical charge. Extensive variation analysis shows that Quad-SIRI latch is less sensitive to temperature and voltage variation in terms of power consumption and less sensitive to temperature variation in terms of delay. So, compared with the existing latches, Quad-SIRI latch makes a good trade-off among delay, power, area and critical charge, and thus it is a good choice for radiation hardening by design in spaceborne applications with low energy particle striking.