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This paper pertains to development of high temperature capable digital integrated circuits in n-channel, enhancement-mode Silicon Carbide (SiC) MOS technology. Among the circuits developed in this work are data latch, flip flops, 4-bit shift register and ripple counter. All circuits are functional from room temperature up to 300C without any notable degradation in performance at elevated temperature. The 4-bit counter demonstrated stable behavior for over 500 hours of continuous operation at 300C.

We describe fabrication of Van der Pauw (VDP) structures for characterization of gate oxides grown on 4H SiC epi surfaces. Implementation of sub-resolvable features (SRF) as a corner compensation mechanism is analyzed with challenges and advantages presented. Results of on-wafer screening tests suggest that implementation of SRFs widens tolerance for misalignment, producing similar yield between uncompensated VDPs with 0.2 micron overlap and compensated VDPs with 0.1 micron overlap for structures with best alignment. Optimization of SRFs for SiC could be an attractive option for extending lithographic capability in advanced devices.

The quality of the SiC/SiO2 interface is critical to the stability and performance of MOS-based SiC power devices. Charge pumping is a flexible interface characterization technique. In this work, a significant portion of the total traps are found to be located in the near-interface oxide using frequency-dependent charge pumping. Oxide trap tunneling mechanisms are discussed, and trap profile as a function of depth is calculated. The trap density is shown to increase exponentially as it gets closer to the interface.

MOSFET-based integrated circuits were fabricated on silicon carbide (SiC) substrates. SiC devices can operate at much higher temperatures than current semiconductor devices. Simple circuit components including operational amplifiers and common source amplifiers were fabricated and tested at room temperature and at 300ºC. The common source amplifier displayed gain of 7.6 at room temperature and 6.8 at 300ºC. The operational amplifier was tested for small signal open loop gain at 1kHz, measuring 60 dB at room temperature and 57 dB at 300ºC. Stability testing was also performed at 300ºC, showing very little drift at over 100 hours for the individual MOSFETs and the common source amplifier.

The gate oxide reliability and channel mobility of carbon face (000-1) 4H Silicon Carbide (SiC) MOSFETs are investigated. Several gate oxidation processes including dry oxygen, pyrogenic steam, and nitrided oxides were investigated utilizing MOS capacitors for time dependent dielectric breakdown (TDDB), dielectric field strength, and MOSFETs for inversion layer mobility measurements. The results show the C-face can achieve reliability similar to the Si-face, however this is highly dependent on the gate oxide process. The reliability is inversely related to the field effect mobility where other research groups report that pyrogenic steam yields the highest electron mobility while this work shows it has weakest oxide in terms of dielectric strength and shortest time to failure.

The performance of 4H-SiC power MOSFETs is limited by the less than ideal electron inversion-layer mobility due to the poor quality of the SiC-SiO2 interface. This poor interface causes several undesirable behaviors of the electrical performance of SiC MOSFETs, including: (1) strong shifts in the threshold voltage with temperature, (2) low channel mobility and (3) strong sensitivity of the mobility to the channel doping concentration. These features are explained by a high density of interface states, the high surface electric field induced in SiC inversion layers, and the combined effectsa combination of Coulomb and surface roughness scattering.

nversion layers of 4H and 6H Silicon carbide based MOS devices are characterized by Gated Hall measurements to determine the trap density close to the conduction band edge and the main scattering mechanisms that limit the mobility. MOS gated Hall structures were fabricated on 4H SiC polytype with p-type doping of 5X1015cm-3 and 2X1017cm-3. MOS Gated Hall structures were also fabricated on 6H SiC polytype with p-type doping of 7.5X1015cm-3. The gate oxide was grown thermally with N2O as a precursor followed by a NO post oxidation anneal. The inversion layer Hall mobility on the 6H SiC MOSFET sample decreased with increasing temperature from room temperature to 423K, while on the 4H SiC MOSFET samples the inversion layer mobility increased slowly. Approximately 50% of the total charge density at the interface of both 6H and 4H SiC MOSFETs was found to be trapped charge. The dominant scattering mechanism in 6H SiC MOSFETs was inferred to be phonon scattering based on the temperature dependence and theoretical estimates of the phonon limited mobility. In the case of 4H SiC, we infer that at surface roughness scattering is the dominant scattering mechanisms at high surface fields.

Low channel mobility is one of the biggest challenges to commercializing SiC MOSFETs. Accurate mobility measurement is essential for understanding the mechanisms that lead to low mobility. The most widely used effective mobility measurements overestimate the inversion charge for devices that have high level of defects. Mobility measured by the Hall effect is more accurate; however the conventional Hall mobility measurement is tedious. In this work, we demonstrate a wafer-level Hall measurement technique, which is simple and convenient to implement. With this method, extensive study of the mobility degradation is possible.

We explain the role of nitrogen in simultaneously increasing the inversion channel mobility and reducing the threshold voltage of SiC MOSFET. A variety of computational techniques have been used to compute the atomic scale configuration of a nitridated SiC/SiO2 interface, and the corresponding change in Fermi level, inversion channel mobility, and threshold voltage. X-ray photoelectron spectroscopy (XPS) has been used to investigate the SiC/SiO2 interface to determine the nitrogen concentrations and chemical bonding. We elucidate the physics behind improved channel mobility due to NO anneal and demonstrate that the trade-off between threshold voltage and inversion channel mobility can be correlated to the extent of nitridation.

Silicon carbide is the only compound semiconductor with silicon dioxide as its native oxide and can form metal–oxide–semiconductor fieldeffect transistors. In this article, we review the inversion layer electron transport properties of 4HSiCSiO2. The inversion layer electron transport theories developed for the SiSiO2system have been reviewed to highlight the behaviour of inversion layer electrons at an ideal interface. The 4HSiCSiO2interface, is currently far from ideal and so we discuss the inversion layer electron transport for several techniques of oxidation of the 0001 4HSiC including nitridation of thermal oxides and sodium enhanced oxidation of 4HSiC. Inversion layer mobility of nitrided oxides is dominated by Coulomb scattering at low surface electric field values and surface roughness scattering at high surface electric field values. In sodium enhanced oxidation samples no trapped charge is found at the interface close to the conduction band edge, but the temperature dependence of mobility shows that the samples are not limited by phonon scattering and therefore not ideal. We also review the results of inversion layer transport on alternate faces of 4HSiC. We conclude highlighting the future work remaining in the field and the behaviour of inversion layer electron mobility we expect to see in an ideal 4HSiCSiO2interface. © 2009 WILEYVCH Verlag GmbH & Co. KGaA, Weinheim

The SiO2/SiC interface is characterized for carbon accumulation using the carbon isotope 13C as a marker layer combined with secondary ion mass spectroscopy (SIMS). SiC was epitaxially grown using an isotopically enriched propane source and subsequently oxidized to a thickness required to consume the entire 13C layer. Mass specific depth profiles through the oxide film yield residual carbon concentrations at or below 3x1011 cm-2. The depth resolution of SIMS and natural abundance of 13C in the bulk SiC film limit sensitivity but allow us to set a limit of 2.5x1014 cm-2 carbon build up at or near the interface.

The mobility of electrons in the inversion layer of 4H-Silicon Carbide (SiC) MOSFETs is lower than the ideal value due to the various scattering mechanisms that takes place at the surface. These scattering mechanisms are strong function of both the interface-trapped charge density and inversion-layer electron density. In this work, we develop a quasi-charge-sheet model to quantify coulomb scattering due to interface trapped-charge in SiC MOSFET inversion layers and calculate the inversion layer electron mobility.

Silicon Carbide (SiC) based metal oxide semiconductor field effect transistors (MOSFETs) were fabricated and characterized using gated hall measurements with different p-type substrate doping concentration (7.2X1016cm-3 and 2X1017 cm-3). An interface trap state density of 5X1013 cm-2eV-1 was observed nearly 0.1 eV above the conduction band edge leading to the conclusion that these states are present in the silicon dioxide rather than the interface. The Hall mobility of the MOSFETs decreased from 26.5 to 20 cm2/Vs as the doping was increased from 7.2X1016 to 2X1017cm-3. The decrease in mobility is primarily due to an increase in the surface electric field that causes an increase in surface roughness scattering. The inversion layer mobility when plotted as a function of average surface electric field is not independent of doping concentration as is the case in silicon MOSFETs because the dominant scattering mechanism is not phonon scattering.

The improvement of the SiC-SiO2 interface has been the main focus of research in SiC MOSFET technology due to the presence of high density of interface traps (Dit) leading to poor threshold voltage temperature stability and poor mobility. In SiC MOSFETs with the gate oxide grown in the presence of sodium, known as sodium enhanced oxidation(SEO), a lower Dit and higher field effect mobility has been observed [1]. Hall effect measurements were performed from 125°K-225°K on such MOSFET samples. The Hall measurements were made as a function of temperature for various sheet charge concentrations. The sheet charge density was measured as a function of gate bias at 225°K and there is very little trapped charge in the sample with oxide grown by SEO while about 50 % of the total charge is trapped in a sample with N2O grown oxide annealed in NO. In samples with oxide grown by SEO, there is a monotonic increase in mobility with sheet charge density and the mobility also increases with temperature. This is an indication that the main scattering mechanism is Coulomb scattering in this regime.

In 4H silicon carbide MOSFETs, threshold voltage varies with temperature. It is believed that this is caused by trapping of inversion electrons at high density of interface-traps (Dit) present at the SiC/SiO2 interface in 4H-SiC MOSFETs. In this work, we present an approach to model the interface trap density as a function of temperature that includes the effect of band gap narrowing. Using the temperature dependent trap charge density, we can estimate the variation of mobile inversion layer charge density, which in turn, explains the threshold voltage behavior with temperature in 4H-SiC MOSFETs.

Depletion-mode 4H-SiC FETs were fabricated for use as harsh environment gas sensors. To enable sensitivity to NOx, O2 and H2 gases, metal oxide catalysts such as InOx were integrated into the gate of the device. The FETs had a total area of approximately 1 mm2. Devices with various gate widths and lengths were fabricated and tested, with sensor performance of 5% or greater in current change from the baseline resulting from designs having a length to width ratio of around 50.