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This study presents a comprehensive investigation of defects in the gate-stack of low-thermal budget replacement metal gate (RMG) MOSFETs treated with novel dielectric passivation techniques using 1/ ${f}$ noise characterization and advanced modeling. This research demonstrates that MOSFETs with gate-stacks treated with atomic hydrogen (H*) and oxygen (O*) (T < 450 °C) yield 1/ ${f}$ noise levels comparable to those of high-thermal budget devices. We also demonstrate that the noise of both pMOSFETs and nMOSFETs mainly originates from defects in the SiO2 interfacial layer (IL). In addition, accurate modeling of 1/ ${f}$ noise provides useful insights into the dielectric defect densities before and after passivation. Notably, the contribution of O-vacancies in HfO2 to 1/ ${f}$ noise appears negligible, whereas it is very important for positive bias temperature instabilities (PBTIs). The results confirm the effectiveness of H* and O* treatments in reducing the electrically active dielectric defects while contributing to a better understanding of the underlying passivation mechanisms.

We report on scaled finFETs built with a novel routing scheme wherein devices are connected via buried power rails (BPRs) from both wafer sides, with tight variability and matching control. On the wafer’s frontside (FS), M1 lines (FSM1) are connected through V0 vias to M0A lines which are then linked to BPR lines by vias called VBPR while also contacting directly the device’s S/D-epi. As for gate wiring, to enable in this work its access from both wafer sides, gate is also connected to BPR via V0 landing on it and on a neighboring M0A line set only on field-oxide. A single-step metallization for M0A and VBPR is preceded by in situ preclean(s) optimized for improved BPR-VBPR contact interface and ${R}_{\text {ext}}$ , as confirmed electrically and by physical analysis. After FS processing, wafer flipping, bonding, and extreme thinning, highly scaled, ~323 nm deep nano-through-Si-vias (nTSVs) land on BPR, with tight overlay control and unchanged BPR resistance [26%–29% lower with improved tungsten (W)-fill], connecting them to the first backside (BS) metal level (BSM1). By moving the power delivery network to the BS (BSPDN), besides alleviating FS routing congestion, considerably smaller dynamic and static IR drop values are predicted from on- chip power heat maps generated for a low power 64-bit CPU at 2-nm design rules: 82% and 96% less worst-case values versus a reference configuration, respectively. P/NMOS show similar or even superior ${I}_{ \mathrm{\scriptscriptstyle ON}}$ – ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ after BS processing and extra anneal(s) added for ${V}_{T}$ recovery, mobility and bias temperature instability (BTI) improvement—up to 8%/15% higher ${I}_{ \mathrm{\scriptscriptstyle ON}}$ linked to anneal selection.

The performance of Si0.75Ge0.25-channel ${p}$ -type nanosheet (NS) devices with a gate length of 14 nm and a sheet width of 12 nm is investigated by Monte Carlo (MC) device simulation. It is found that the stress in the Si–Ge channel can eliminate the performance imbalance with ${n}$ -type NSs arising from the (001) surface in the absence of stress. The performance is the same as the theoretical performance of Si-channel (cSi) ${p}$ -type NSs with Si0.5Ge0.5 source/drain (S/D) pockets under the ideal assumption that no stress relaxation, e.g., due to grain boundaries from merging epitaxial growth occurs for the cSi devices. It is shown that the performance levels can be related to stress-induced quasi-ballistic velocity overshoot and the impact of alloy scattering. This is not captured by standard drift–diffusion (DD) simulation where a smaller saturation velocity predicts a performance degradation for Si–Ge channel devices.

We propose for the first time a dedicated FinFET technology with specific optimization for tox >40 nm and lateral breakdown >35 V to replace the conventional planar high voltage transistors in the 3D NAND Flash periphery. We show significant current increase (>x2) and area saving per footprint, solving one of the key bottlenecks of future 3D NAND nodes. Fabrication of thermally stable prototypes is shown, with no significant impact on the overall fabrication complexity.

BACKGROUND AND AIMS: Induction of apoptosis of cancer cells through ligands of nuclear hormone receptors (NHRs) is a new approach in cancer therapy. Recently, one of the NHRs, peroxisome proliferator activated receptor gamma (PPARgamma), has been shown to influence cell growth in certain cancer cells although its effect on hepatocellular carcinoma (HCC) has not been analysed. METHODS: Experiments were conducted using three human liver cancer cell lines, PLC/PRF/5, Hep G2 and HuH-7, in vitro. These cells were exposed to troglitazone, a synthetic ligand for PPARgamma, and the effects on cell growth were analysed. RESULTS: Expression of PPARgamma mRNA was detected in all three liver cancer cell lines. Activation of PPARgamma by troglitazone caused a marked growth inhibition in a dose dependent manner in three hepatoma cell lines. The DNA fragmentation ELISA assay and Hoechst 33258 staining revealed that the growth inhibitory effect by adding troglitazone was due to apoptosis of PLC/PRF/5, which strongly expressed PPARgamma. Troglitazone also induced activation of the cell death protease, caspase 3, but not caspase 8, in PLC/PRF/5 cells. However, expression levels of antiapoptotic factor bcl-2 and apoptosis inducing factor bax were not affected. CONCLUSION: Our study showed that PPARgamma was expressed in human liver cancer cells and that the ligand for PPARgamma, troglitazone, inhibited the growth of these cells by inducing apoptosis through caspase 3 activation, indicating that troglitazone could be potentially useful as an apoptosis inducer for the treatment of HCC.

The spectral hole burning of InAs self-assembled quantum dots (QDs) embedded in a pin diode has been observed for the first time. The spectral hole depth increases as the electric field is increased. By numerical fitting to experimental results, the possibility of wavelength-domain multiplicity in optical memory by using InAs QDs is shown.

Engineering the effective work function of scaled-down devices is commonly achieved by the implementation of capping layers in the gate stack. Typical cap layers are Al2O3for pMOSFETs and La-oxide or Mg for nMOSFETs. Besides introducing a dipole layer at the SiO2/high-κ interface, the in-diffusion of the metal ions may lead to either passivation or generation of traps in the SiO2/high-κ layer. This paper uses low frequency noise studies to determine the impact of capping layers on the quality of the SiO2/HfO2gate stacks. The influence on the trap profiles of different types of cap layers, different locations of the cap layer (below or on top of the HfO2dielectric) and the impact of different thermal budgets, typically used for the fabrication of Dynamic Random Access Memory (DRAM) logic devices, are investigated. The differences between several metal oxides are outlined and discussed.

A review is given about the impact of the metal gate (MG) in a High-κ/Metal Gate (HKMG) stack on the quality and defectivity of the dielectric, assessed by low-frequency (LF) noise spectroscopy. In a first part, processing aspects are discussed, like, the thickness of the MG and the implementation of a gate-last approach. In the latter case, it is shown that both the cleaning (or dummy gate removal), the growth of the interfacial SiO2layer (chemical versus thermal) and a post-HfO2-deposition heat or SF6plasma treatment need to be optimized for reducing the gate oxide trap density. In a second part, different MGs are compared from a viewpoint of noise magnitude. It is generally found that alternatives to the standard TiN gate yield better static and noise performance. Results will be presented both for scaled planar and FinFET technologies; the latter fabricated on either bulk or Silicon-on-Insulator (SOI) substrates. Also results on Gate-All-Around NanoWire FETs (GAA NWFETs) fabricated on SOI will be included.

In this contribution, we report a fundamental study of the factors that set the contact resistivity between metals and highly doped n-type 2D and 3D semiconductors. We investigate the case of n-type doped Si contacted with amorphous TiSi combining first-principles calculations with Non-Equilibrium Green functions transport simulations. The evolution of the intrinsic contact resistivity with the doping concentration is found to saturate at ∼2 × 10−10Ω.cm2for the case of TiSi and imposes an intrinsic limit to the ultimate contact resistance achievable for n-doped Si|amorphous-TiSi (aTiSi). The limit arises from the intrinsic properties of the semiconductors and of the metals such as their electron effective masses and Fermi energies. We illustrate that, in this regime, contacting heavy electron effective mass metals with semiconductor helps reducing the interface intrinsic contact resistivity. This observation seems to hold true regardless of the 3D character of the semiconductor, as illustrated for the case of three 2D semiconducting materials, namely MoS2, ZrS2and HfS2.

With the continued scaling of CMOS devices below the 10 nm node, process technologies become more and more challenging as the allowable thermal budget for device processing continuously reduces. This is especially the case during epitaxial growth, where a reduction of the thermal budget is required for a number of potential reasons for example to avoid uncontrolled layer relaxation of strained layers, surface reflow of narrow fin structures, as well as doping diffusion and material intermixing. Further aspects become even more challenging when Ge is used as a high-mobility channel material and when the device concept moves from a FinFET design to a nanowire FET design (also called Gate-All-Around FET). In this contribution we address some of the challenges involved with the integration of high mobility Group IV materials in these advanced device structures.

The impact of the implementation of a high-κ/metal-gate (HKMG) stack on the oxide integrity of input-output (I/O) pMOSFETs for DRAM periphery applications is investigated by means of low-frequency (LF) noise spectroscopy. It is shown that the predominant 1/f noise is governed by number fluctuations, irrespective of the details of the gate stack. However, the trap density in the 5 nm SiO2gate oxide, derived from the noise power spectral density is significantly increased by the application of the HKMG and/or Al2O3cap and the subsequent diffusion anneal at 900°C.

Low-frequency noise is studied in planar high-κ/metal-gate (HK/MG) last pMOSFETs in order to assess the impact of a post-HfO2deposition SF6-plasma or heat-treatment on the oxide trap density and profile. It is shown that the gate oxide quality is improved by lowering the active border trap density for both approaches. At the same time, a detailed analysis of the frequency exponent of the flicker noise spectra reveals that in the case of the SF6-plasma, the reduction of the active border trap density occurs more efficiently deeper in the high-κ layer, while the opposite holds for the annealed devices, i.e., a lower trap density is found closer to the interfacial SiO2layer.