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Thermal processing is an integral part of crystalline silicon (c-Si) solar cell manufacturing technology. It is often applied to achieve diffusion, annealing, oxidation, deposition, or reaction process steps in a production environment. This paper reports recent developments in thermal process technology that enable the industry to improve cell efficiency and manufacturing productivity for the standard c-Si cell technology. Especially, continuous inline thermal equipment is adopted in many critical c-Si cell fabrication stages, from emitter formation by dopant diffusion, contact formation by rapid thermal sintering of metallic pastes, to hydrogen annealing to rescue low-efficiency cells.

Gate spacer engineering has become one of the primary concerns in dimensional metrology for semiconductor manufacturing process control. In composite spacers, deposition and etch of each spacer determine where the transistor source/drain implants occur. The sidewall spacer thickness and profile, especially at the feature bottom, is critical to be characterized and controlled by applicable 3D metrology. This paper discusses recent advances in 3D atomic force microscopy (3D-AFM) that solve the specialized characterization needs for critical sidewall spacer geometry controls, including multiple spacer thickness and nitride spacer pulldown. 3D-AFM metrology measures with greater accuracy such typical gate spacer parameters as linewidth, height, pitch, sidewall profile, sidewall angle (SWA), line edge roughness (LER), and line width variation (LWV), and sidewall roughness (SWR).

Thermal processing is an integral part of crystalline silicon (c-Si) solar cell manufacturing technology. It is often applied to achieve diffusion, annealing, oxidation, deposition, or reaction process steps in a production environment. This paper reports recent developments in thermal process technology that enable the industry to improve cell efficiency and manufacturing productivity for the standard c-Si cell technology. Especially, continuous inline thermal equipment is adopted in many critical c-Si cell fabrication stages, from emitter formation by dopant diffusion, contact formation by rapid thermal sintering of metallic pastes, to hydrogen annealing to rescue low-efficiency cells.

Gate spacer engineering has become one of the primary concerns in dimensional metrology for semiconductor manufacturing process control. In composite spacers, deposition and etch of each spacer determine where the transistor source/drain implants occur. The sidewall spacer thickness and profile, especially at the feature bottom, is critical to be characterized and controlled by applicable 3D metrology. This paper discusses recent advances in 3D atomic force microscopy (3D-AFM) that solve the specialized characterization needs for critical sidewall spacer geometry controls, including multiple spacer thickness and nitride spacer pulldown. 3D-AFM metrology measures with greater accuracy such typical gate spacer parameters as linewidth, height, pitch, sidewall profile, sidewall angle (SWA), line edge roughness (LER), and line width variation (LWV), and sidewall roughness (SWR).