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A portable orthogonal phase-locked amplifier for weak signal detection has been developed based on FPGA. First,the signal processing module receives the signal,does variable gain amplification on the signal and puts it through the power frequency noise filtering. The signal is put into the FPGA through A/D conversion module conversion. By the digital phase-locked loop ,the amplifier completes the measured signal phase lock, extracts the feedback signal to calculate the measured signal amplitude, and completes weak signal detection. The lock-in amplifier amplitude measurement range is 100 nV~100 μV, dynamic range can reach up to 60 dB, phase accuracy can attain 0.001°. The system is designed as a portable device, low cost, easy to maintain, can meet the measurement requirements of the special environment such as fieldwork or etc, and has broad application prospects.

In order to solve the problem of the short transmission distance and the high bit-error ratio of multichannel high-speed space camera, an active equalization scheme at the receiver end is proposed and implemented. First of all, the non-dc-balanced characteristics of image data signal is analyzed. Based on the measurement data, the mathematical model of the long transmission cable is created. According to the attenuation characteristics of this model, an equalization circuit is designed, which makes use of the high gain of the high-speed differential amplifier and the frequency selecting feature of the phase-lead feedback network to flatten the frequency response of the lossy transmission channel. The simulation results show that with the equalization circuit the maximum data transfer rate of the channel can be expended from 16 Mbps to 250 Mbps. Besides, the eye diagram measurement results demonstrate that the inter-symbol interference caused by the transmission media is significantly reduced after equalization, resulting in an open eye diagram with reduced jitter and crisp edges. Finally, by observing the Signal Tap logic analyzer, sending grayscale and actual pictures, it has been verified that the error-free transmission distance can reach 80 m at 250 Mbps.

This paper presents an optimization solution on the analog signal generating, sampling and output modules in the signal processing unit of a linear CCD camera. An integrated driver chip is used to increase the drive current of the CCD sensor timing signal, which meets the driving requirements of the horizontal signal. A precise delay circuit is implemented which can adjust the Correlation Double Sampling (CDS) location dynamically and in real time, so that the analog image signal can be always sampled at the best location. To solve the three-color separation problem after sampling and to meet the requirement of the real-time image, the paper designs a resource optimal solution by using only one SDRAM and 25 percent of the FPGA resources to achieve spatial correction. The results show that driven by the timing signal, the output analog image of the CCD sensor is of high quality. The precision of the precise delay circuit is 0.13 ns and the delay is real-time adjustable. In the maximum line rate (9.2 KHz) mode, the output of the imaging system does not have three-color separation. This design is applicable to other imaging systems.