Design of the Key Signal Processing Modules in a Linear CCD Camera

This paper presents an optimization solution on the analog signal generating, sampling and output modules in the signal processing unit of a linear CCD camera. An integrated driver chip is used to increase the drive current of the CCD sensor timing signal, which meets the driving requirements of the horizontal signal. A precise delay circuit is implemented which can adjust the Correlation Double Sampling (CDS) location dynamically and in real time, so that the analog image signal can be always sampled at the best location. To solve the three-color separation problem after sampling and to meet the requirement of the real-time image, the paper designs a resource optimal solution by using only one SDRAM and 25 percent of the FPGA resources to achieve spatial correction. The results show that driven by the timing signal, the output analog image of the CCD sensor is of high quality. The precision of the precise delay circuit is 0.13 ns and the delay is real-time adjustable. In the maximum line rate (9.2 KHz) mode, the output of the imaging system does not have three-color separation. This design is applicable to other imaging systems.