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As an outstanding representative of layered materials, molybdenum disulfide (MoS2) has excellent physical properties, such as high carrier mobility, stability, and abundance on earth. Moreover, its reasonable band gap and microelectronic compatible fabrication characteristics makes it the most promising candidate in future advanced integrated circuits such as logical electronics, flexible electronics, and focal-plane photodetector. However, to realize the all-aspects application of MoS2, the research on obtaining high-quality and large-area films need to be continuously explored to promote its industrialization. Although the MoS2 grain size has already improved from several micrometers to sub-millimeters, the high-quality growth of wafer-scale MoS2 is still of great challenge. Herein, this review mainly focuses on the evolution of MoS2 by including chemical vapor deposition, metal–organic chemical vapor deposition, physical vapor deposition, and thermal conversion technology methods. The state-of-the-art research on the growth and optimization mechanism, including nucleation, orientation, grain, and defect engineering, is systematically summarized. Then, this review summarizes the wafer-scale application of MoS2 in a transistor, inverter, electronics, and photodetectors. Finally, the current challenges and future perspectives are outlined for the wafer-scale growth and application of MoS2.

The goal of this paper is to advance the understanding of the impact of hard switching on the dynamic performance of GaN-based HEMTs. To this aim, we developed a fast (10 V/ns) on-wafer system for testing devices in hard switching. The system has been used to study the reliability of several WG = 2 mm p-type GaN HEMTs with different LGD or buffer properties. First, we show that by optimizing the drain node capacitance, we can speed-up the hard-switching transition to a few ns, even on-wafer level. Second, repeating the experiment by using multiple frequencies, from 1 kHz to 100 kHz, we demonstrate that, in real-world applications, cumulative turn-on stress has a much stronger effect on RON compared to off-state stress. Third, by comparing the results on identical devices having shorter LGD, we pinpoint hot electrons as the main mechanism in the device degradation, ruling out the contribution of self-heating. Finally, by comparing three wafers with different processing conditions (different passivation, different buffer) we suggest that trapping phenomena related to hot electrons happen in ns time scale and that the properties of the buffer can significantly impact the dynamic performance of the devices in hard switching.

As the maximum frequency of electronics is rising, on-wafer measurements play an important role in modeling of integrated devices. Most of the time, due to the lack of measurement accuracy beyond 110 GHz, such models are usually extracted at frequencies much below their working frequencies and are subsequently extrapolated. The validity of such models is then mostly verified after fabrication of the complete chip, with a simple pass and fail test. This is stating the necessity of enhancing measurement results by any means possible, i.e., to reduce the overall uncertainty in such measurements. It is widely accepted that one of the main sources of uncertainty in such measurements is probe contact repeatability, since it is difficult to reach position accuracy below a few micrometers. We are presenting in this article a method to model the S -parameter variation with probe position on the pads, which can then be used to either estimate contact repeatability uncertainty or further enhance measurement results. The approach is validated based on the measurements performed at 500 GHz.

In this paper, the problem of observer design for a class of 1D nonlinear heat equations with pointwise in-domain temperature measurements is addressed. A pointwise measurement injection observer is designed and the robust convergence of its estimation error in presence of bounded distributed perturbations is established by verifying input-to-state stability. The obtained convergence conditions express the underlying interplay between heat conduction and radiation and include specific dependencies on the sensor locations which are the main degrees of freedom in the design approach. The theoretical results are experimentally validated on a semiconductor wafer processing unit.

As the surface acoustic wave (SAW) filters incline to ultrafine, the failures resulting from the wafer molding process have become increasingly prominent. A methodology for coupling the mechanisms of die fly and die shift for the SAW filter miniatured with 737 μm × 517 μm × 200 μm is developed for the trade-off between reliability and yields. In terms of die fly and die shift, the former occurs before the epoxy molding compound (EMC) is cured in the temperature rise period, while the latter occurs in the cooling stage after being cured. The die fly is induced by the fluid flow force in the high-temperature stage of heat compression, which is fatal for the scrap. Followed by the cooling stage, the CTE (coefficient of thermal expansion) misalignment between the die and epoxy molding compound (EMC) seriously affects the die shift and the following lithography process yields. The debonding critical energy in the mixed mode is employed to avert the die fly. Then, the die fly can be shunned by fine-tuning the die thickness, die layout, and EMC layout. A methodology to measure die shift was conducted, by which a total of 47,568 dies were embedded using compression molding. The mechanical error of the mounter and the die shift law are comprehensively leveraged, indicating that the die shift can be controlled within 50 μm for 8-inch wafer-level packaging.

In this paper, the developments achieved in PHOTO-SENS* towards a process for the wafer level manufacturing of hybrid photonic biosensor PICs are outlined. First, the design and fabrication of the PIC wafers is described, followed by the wafer level hybrid integration of active components (light source, detector, and temperature sensor). Then, wafers are material-selectively coated to enable local biofunctionalization of the sensing waveguides. Singulation of the coated hybrid PICs into individual chips is achieved using stealth dicing. * This project has received funding from the European Union’s Horizon 2020 research and innovation programme under grant agreement No 965643. See www.photo-sens.eu for more information., {"references":["M. Chatzipetrou et al., \"A miniature bio-photonics companion diagnostics platform for reliable cancer treatment monitoring in blood fluids,\" Sensors, vol. 21, no. 6, 2021, doi: 10.3390/s21062230","K. Wörhoff, R. G. Heideman, A. Leinse, and M. Hoekman, \"TriPleX: a versatile dielectric photonic platform,\" Adv. Opt. Technol., vol. 4, no. 2, pp. 189–207, 2015, doi: 10.1515/aot-2015-0016","G. Besselink et al., \"Asymmetric Mach–Zehnder Interferometric Biosensing for Quantitative and Sensitive Multiplex Detection of Anti-SARS-CoV-2 Antibodies in Human Plasma,\" Biosensors, vol. 12, no. 8, p. 553, Jul. 2022, doi: 10.3390/bios12080553","W.-S. Lei, A. Kumar, and R. Yalamanchili, \"Die singulation technologies for advanced packaging: A critical review,\" J. Vac. Sci. Technol. B, Nanotechnol. Microelectron. Mater. Process. Meas. Phenom., vol. 30, no. 4, p. 040801, 2012, doi: 10.1116/1.3700230"]}

Candidiasis is one of the most common fungal infections of oral cavity in humans, causing great oral discomfort, pain and aversion to food. To develop more effective antifungal systems for the treatment of oral candidiasis, an oral mucoadhesive wafer containing sertaconazole solid dispersion (STZ-SD) was developed in this study. Dispersion of STZ in Soluplus® as a solubility enhancement excipient was done by melting, solvent evaporation and freeze drying method at various STZ to Soluplus® ratios. The optimized STZ-SD was then incorporated in the sodium carboxymethyl cellulose (SCMC) gel, xanthan gum gel, or their combination to prepare the lyophilized wafers. The swelling capacity, porosity, and mechanical, release and mucoadhesive properties of the wafers, together with their antifungal activity, were then evaluated. The melting method sample with the ratio of 8:1 showed the best results in terms of saturation solubility and dissolution rate. The STZ-SD-composite wafer exhibited higher hardness and mucoadhesion, as compared to those made of the SCMC polymer. The STZ-SD-wafer also exhibited a greater antifungal effect when compared to the STZ-wafer. The present study, thus, suggested that the STZ-SD-wafer could serve as a novel effective delivery system for oral candidiasis treatment.

In the semiconductor industry, achieving a high production yield is a very important issue. Wafer bin maps (WBMs) provide critical information for identifying anomalies in the manufacturing process. A WBM forms a certain defect pattern according to the error occurring during the process, and by accurately classifying the defect pattern existing in the WBM, the root causes of the anomalies that have occurred during the process can be inferred. Therefore, WBM defect pattern recognition and classification tasks are important for improving yield. In this paper, we propose a deep convolutional generative adversarial network (DCGAN)-based data augmentation method to improve the accuracy of a convolutional neural network (CNN)-based defect pattern classifier in the presence of extremely imbalanced data. The proposed method forms various defect patterns compared to the data augmentation method by using a convolutional autoencoder (CAE), and the formed defect patterns are classified into the same pattern as the original pattern through a CNN-based defect pattern classifier. Here, we introduce a new quantitative index called PGI to compare the effectiveness of the augmented models, and propose a masking process to refine the augmented images. The proposed method was tested using the WM-811k dataset. The proposed method helps to improve the classification performance of the pattern classifier by effectively solving the data imbalance issue compared to the CAE-based augmentation method. The experimental results showed that the proposed method improved the accuracy of each defect pattern by about 5.31% on average compared to the CAE-based augmentation method.

25. International Conference on Material Forming, ESAFORM, Braga, Portugal, 27 Apr 2022 - 29 Apr 2022; Key engineering materials 926, 2371-2381 (2022). doi:10.4028/p-hachrx special issue: "Achievements and Trends in Material Forming : Peer reviewed extended papers selected from the 25th International Conference on Material Forming (ESAFORM 2022) / Edited by Gabriela Vincze, Frédéric Barlat", Published by Trans Tech Publications Ltd., Baech

The investigation of two-dimensional (2D) materials has advanced into practical device applications, such as cascaded logic stages. However, incompatible electrical properties and inappropriate logic levels remain enormous challenges. In this work, a doping-free strategy is investigated by top gated (TG) MoS2 field-effect transistors (FETs) using various metal gates (Au, Cu, Ag, and Al). These metals with different work functions provide a convenient tuning knob for controlling threshold voltage (Vth) for MoS2 FETs. For instance, the Al electrode can create an extra electron doping (n-doping) behavior in the MoS2 TG-FETs due to a dipole effect at the gate-dielectric interface. In this work, by achieving matched electrical properties for the load transistor and the driver transistor in an inverter circuit, we successfully demonstrate wafer-scale MoS2 inverter arrays with an optimized inverter switching threshold voltage (VM) of 1.5 V and a DC voltage gain of 27 at a supply voltage (VDD) of 3 V. This work offers a novel scheme for the fabrication of fully integrated multistage logic circuits based on wafer-scale MoS2 film.

Wafer bin maps (WBMs) are essential test data in semiconductor manufacturing. WBM defect classification can provide critical information for the improvement of manufacturing processes and yield. Although deep-learning-based automatic defect classification models have demonstrated promising results in recent years, they require a substantial amount of labeled data for training, and manual labeling is time-consuming. Such limitations impede the practical application of existing algorithms. This study introduces a low-data defect classification algorithm based on contrastive learning. By employing momentum contrastive learning, the network extracts effective representations from large-scale unlabeled WBMs. Subsequently, a prototypical network is utilized for fine-tuning with only a minimal amount of labeled data to achieve low-data classification. Experimental results reveal that the momentum contrastive learning method improves the defect classification performance by learning feature representation from large-scale unlabeled data. The proposed method attains satisfactory classification accuracy using a limited amount of labeled data and surpasses other comparative methods in performance. This approach allows for the exploitation of information derived from large-scale unlabeled data, significantly reducing the reliance on labeled data.

openaire: EC/H2020/826588/EU//APPLAUSE The wafer-level Solid Liquid Interdiffusion (SLID) bonds carried out for this work take advantage of the Cu-In-Sn ternary system to achieve low temperature interconnections. The 100mm Si wafers had μ-bumps from 250μm down to 10μm fabricated by consecutive electrochemical deposition of Cu, Sn and In layers. The optimized wafer-level bonding processes were carried out by EV Group and Aalto University across a range of temperatures from 250°C down to 170°C. Even though some process quality related challenges were observed, it could be verified that high strength bonds with low defect content can be achieved even at a low bonding temperature of 170°C with an acceptable 1-hour wafer-level bonding duration. The microstructural analysis revealed that the bonding temperature significantly impacts the obtained phase structure as well as the number of defects. A higher (250°C) bonding temperature led to the formation of Cu3Sn phase in addition to Cu6(Sn,In)5 and resulted in several voids at Cu3Sn|Cu interface. On the other hand, with lower (200°C and 170°C) bonding temperatures the interconnection microstructure was composed purely of void free Cu6(Sn,In)5. The mechanical testing results revealed the clear impact of bonding quality on the interconnection strength.

This paper describes a terahertz (T-ray) cameraless imaging and profile mapping technique for accomplishing the imaging and/or mapping of a whole wafer with fabricated dies for devising a criterion to sort out good dies. A stratagem for decoupling the wavelength’s dependence on image formation is described, whereby the Abbe diffraction limit is overcome, and a high-resolution image is generated by a larger wavelength T-ray. The mechanics of cameraless image formation is discussed. A 200 mm diameter patterned wafer’s image details have been presented from which die-to-die inconsistencies were investigated. A profile of a row of dies was formed from the scanned intensity and compared with the profiles obtained from the graphical analysis of the image of the same dies. It is demonstrated that a criterion could be established either from the scanned profile or from the profile generated from the graphical analysis of the image. A known good die’s profile could be used as a reference to compare with the other dies’ profiles on the same wafer. Such a criterion could be used to sort the good from bad dies. The technique is extended to a whole wafer populated with die patterns via the profile mapping of the entire wafer. The profile mapping of the whole wafer could be used to compare and sort all wafers from the same batch. The Fab yield is improved by maximizing the count of good dies by applying the efficient sorting criterion.

This paper reports a MEMS disk resonator gyroscope (DRG) with superior overall performance in terms of bias instability, measurement range, and size. Specifically, a fully filled electrodes MEMS DRG is proposed to improve sensing capacitance to 23.66 pF and drive capacitance to 6.14 pF. The DRG is fabricated using a wafer-level vacuum-package process and is controlled and sensed by a configurable ASIC, enabling a small footprint. The DRG achieves an angle random walk (ARW) of 0.05/h and bias instability of 0.42/h within a full scale of 300/s, making it a very promising solution for angular measurement in high-end industrial applications.

To meet the increasing demand for denser integrated circuits, feedforward control plays an important role in the achievement of high servo performance of wafer stages. The preexisting feedforward control methods, however, are subject to either inflexibility to reference variations or poor robustness. In this article, these deficiencies are removed by a novel variable-gain iterative feedforward tuning (VGIFFT) method. The proposed VGIFFT method attains: 1) no involvement of any parametric model through data-driven estimation; 2) high performance regardless of reference variations through feedforward parameterization; and 3) especially high robustness against stochastic disturbance as well as against model uncertainty through a variable learning gain. What is more, the tradeoff in which preexisting methods are subject to between fast convergence and high robustness is broken through by VGIFFT. Experimental results validate the proposed method and confirm its effectiveness and enhanced performance.

A detailed experimental analysis of the impact of device topology on the performance of 1550 nm VCSELs with an active region based on thin InGaAs/InAlGaAs quantum wells and a composite InAlGaAs buried tunnel junction is presented. The high-speed performance of the lasers with L-type device topology (with the largest double-mesa sizes) is mainly limited by electrical parasitics showing noticeable damping of the relaxation oscillations. For the S-type device topology (with the smallest double-mesa sizes), the decrease in the parasitic capacitance of the reverse-biased p+n-junction region outside the buried tunnel junction region allowed to raise the parasitic cutoff frequency up to 13–14 GHz. The key mechanism limiting the high-speed performance of such devices is thus the damping of the relaxation oscillations. VCSELs with S-type device topology demonstrate more than 13 GHz modulation bandwidth and up to 37 Gbps nonreturn-to-zero data transmission under back-to-back conditions at 20 °C.

We examine a scheduling problem for a dual-armed cluster tool that processes multiple similar wafer types concurrently. It has been recently proved that the well-known swap sequence, which is widely used for single wafer type processing, also minimizes the cycle time for concurrent processing. In this article, we wish to minimize wafer delays in a process chamber, which are critical to wafer quality degradation, while maintaining the minimum cycle time. In particular, we show that concurrent processing of wafers with different processing times complicates the analysis of wafer delays significantly, and the wafer delays can be remarkably reduced by finding a proper cycle plan which is the release sequence of different wafer types. We first characterize wafer delays for a given cycle plan by analyzing the circuits of the timed event graph (TEG) model. From this, we prove that concurrent processing of wafers may cause a significant workload imbalance between parallel chambers of a process step, and hence the wafer delays increase substantially. We present that the wafer delays are minimized by a cycle plan that evenly balances workloads between parallel chambers. We also propose how wafer loading task at each process step has to be postponed to meet wafer delay constraints while maintaining the minimum cycle time. Note to Practitioners —Wafer quality control has become an essential fab operational problem in semiconductor manufacturing industry. In cluster tools, which are dominantly being used for diverse wafer fabrication stages, it has been proven that the wafer delays within process chambers have a crucial impact on the wafer quality. Accordingly, modern fabs have introduced stringent quality control to regulate wafer delays in cluster tools. In this research, we propose a scheduling strategy to minimize the wafer delays when a cluster tool concurrently processes multiple wafer types. We first show that the release sequence of different wafer types significantly impacts the wafer delays under concurrent processing, and we then propose how these wafer delays can be minimized by finding the optimal wafer release sequence.

Severe process variations in advanced technology require more devices under test (DUTs) to be characterized in the wafer acceptance test (WAT) to more reliably qualify the fabricated wafers. However, conventional WAT takes a long test time to acquire sufficient characterization data. This article proposes an on-wafer test circuity to fast and accurately characterize DUT arrays during a single probing. It integrates the proposed compact DUT cells, an IR drop compensator, and a wide-input-range (WIR) current digitizer. The proposed IR drop compensator collaborates with the DUT cells to address the IR drop issue and thus improve the test accuracy of the parameter tests. The proposed multi-mode 12-bit WIR current digitizer achieves a 140-dB input range for digitizing the DUTs' output currents in various WAT test items. It eliminates the need of high-end ATE and saves the test cost. A prototype IC including 2048 DUTs has been designed and fabricated in 90-nm CMOS. Its active area is only 60 μm by 1900 μm which can be placed in a scribe line as conventional WAT structure is. Experimental results demonstrate the proposed test circuitry can render spatial variation results and other device parameters of the DUT arrays in addition to typical WAT items.

Most microsensors are composed of devices and covers. Due to the complicated structure of the cover and various other requirements, it difficult to use wafer-level packaging with such microsensors. In particular, for monolithic microsensors combined with read-out ICs, the available process margins are further reduced due to the thermal and mechanical effects applied to IC wafers during the packaging process. This research proposes a low-temperature, wafer-level vacuum packaging technology based on Cu-Sn bonding and nano-multilayer getter materials for use with microbolometers. In Cu-Sn bonding, the Cu/Cu3Sn/Cu microstructure required to ensure reliability can be obtained by optimizing the bonding temperature, pressure, and time. The Zr-Ti-Ru based nanomultilayer getter coating inside the cap wafer with high step height has been improved by self-aligned shadow masking. The device pad, composed of bonded wafer, was opened by wafer grinding, and the thermoelectrical properties were evaluated at the wafer-level. The bonding strength and vacuum level were characterized by a shear test and thermoelectrical test using microbolometer test pixels. The vacuum level of the packaged samples showed very narrow distribution near 50 mTorr. This wafer-level packaging platform could be very useful for sensor development whereby high reliability and excellent mechanical/optical performance are both required. Due to its reliability and the low material cost and bonding temperature, this wafer-based packaging approach is suitable for commercial applications.

Mit der Entwicklung der Mikroelektronik in den letzten 40 Jahren ist die Bedeutung von Wafer-Bonding-Prozessen signifikant gestiegen. Das Waferbonden bietet Vorteile wie die Versiegelung und Verkapselung von Bauteilen auf der Waferoberfläche zum Schutz vor Umwelteinflüssen sowie die Integration von Elementen mithilfe unterschiedlicher Technologien und Materialien.Die zunehmenden Anwendungen des Waferbondens in der Industrie und die daraus resultierenden höheren Anforderungen führten unter anderem zur Entwicklung der ComBond®- Hochvakuum-Waferbond-Technologie. Die Methode dieser Technologie basiert auf dem Konzept der Oxidentfernung an der Oberfläche durch Ionenbestrahlung vor dem Bon- den. Diese Masterarbeit wurde mit dem Ziel durchgeführt, ein erweitertes Verständnis der zugrundeliegenden physikalischen Prozesse zu erlangen, sowie empirische Daten für die Waferverarbeitung mit dem Fokus auf verschiedenen Ionenarten zu sammeln.Untersucht wurde die Auswirkung niederenergetischer Ionenbehandlung mit verschiedenen Ionenarten auf den Amorphisierungsprozess und auf die Bondstärke der gebondeten Wafer. Dafür wurde eine Reihe von Experimenten an der ComBond®-Anlage bei EV Group unter Verwendung von 200 mm Siliziumwafern durchgeführt. Die in der Anlage enthaltene gitterbasierte Hochfrequenz-Ionenquelle wurde mit Argon, Krypton und Xenon betrieben. Der Einfluss der Ionenart, des Einfallswinkels, der Bescheunigungsspannung und der Aktivierungszeit wurde auf die Dicke der amorphen Schicht, die Wafertemperatur, die Oberflächenrauhigkeit, die Bindungsenergie und die elementare Zusammensetzung an der Grenzfläche des gebondeten Wafers untersucht. Einzelne Wafer wurden mit spektroskopischer Ellipsometrie und Rasterkraftmikroskopie untersucht. Gebondete Waferpaare wurden durch Transmissionselektronenmikroskopie einschließlich energiedispersiver Röntgenspektroskopie und mit der Maszara-Methode unter Verwendung einer Infrarotanlage charakterisiert., With the development in microelectronics over the last 40 years, the importance of wafer bonding processes has increased remarkably. Wafer bonding provides benefits like sealing and encapsulating devices on the wafer surface for ensuring protection against environmental influences, as well as the integration of elements with different technologies and materials. The increasing applications of wafer bonding in industry and the consequent higher demands led, among others, to the development of the ComBond® high vacuum wafer bonding technology. The method of this technology is based on the concept of surface oxide removal due to ion irradiation before bonding. This master thesis was conducted with the goal of getting an expanded understanding of the underlying physical processes as well as gathering empirical data with the focus on different ion types for wafer processing.The effect of low energy ion treatment with different ion species on the amorphization process and on the wafer bonding energy was investigated. This investigation includes a series of experiments which were carried out on the ComBond® system at EV Group, using 200 mm silicon wafers. The gridded radio frequency ion source included in the system was operated with argon, krypton and xenon. The influence of ion type, angle of incidence, beam voltage and activation time on the amorphous layer thickness, the wafer temperature, the surface roughness, the bonding energy and the elemental composition at the bonded wafer interface was investigated. Single wafers were inspected by spectro- scopic ellipsometry and atomic force microscopy. Bonded wafer pairs were characterized by transmission electron microscopy including energy-dispersive X-ray spectroscopy and by the Maszara method using an infrared-station.

In this paper, an evaluation of machine learning classifiers to be applied in wafer defect detection is described. The objective is to establish the best machine learning classifier for Wafer Defect Detection application. k-Nearest Neighbours (k-NN), Logistic Regression, Stochastic Gradient Descent, and Support Vector Machine were evaluated with 3 defects categories and one non-defect category. The key metrics for the evaluation are classification accuracy, classification precision and classification recall. 855 images were used to train, test and validate the classifier. Each image went through the embedding process by InceptionV3 algorithms before the evaluated classifier classifies the images.

Nowadays, wafer fabrication in semiconductor manufacturing is highly dependent on cluster tools. A cluster tool is equipped with several process modules (PMs) and a wafer handling robot. When the tool is operating, generally each PM is processing a wafer, and the robot is responsible for delivering the wafers from one PM to another. Thus, when a wafer is completed in a PM, the robot may be busy for performing other tasks such that it cannot immediately unload the completed wafer in the PM, resulting in that the wafer has to stay there for some extra time. The processing time of a wafer together with its delay time for waiting for the robot’s arrival for unloading is defined as wafer residency time in a PM. However, a long wafer delay time may deteriorate its quality. Therefore, it is highly desired and important to reduce the wafer delay time at each step as much as possible. This work aims to tackle this important issue for single-arm cluster tools (SACTs). Specifically, by using a Petri net model, this work analyzes the steady-state operational behavior of an SACT under the backward and earliest starting strategies. It is found that there must exist wafer delay time at the steps in the upstream of the bottleneck step, and such wafer delay time can be reduced by properly adjusting the robot waiting time. Thus, three algorithms are developed to reduce the wafer delay time at each step as much as possible by properly assigning the robot idle time. Finally, the application of the proposed method is illustrated by using examples. Note to Practitioners —In a modern semiconductor fab, there are hundreds of cluster tools for wafer fabrication. To ensure wafer quality, it is important to reduce the wafer delay time in PMs of cluster tools after a wafer is processed since the high temperature, chemical gas, and particles in the PMs may damage the wafer. To do so, this work proposes three algorithms with polynomial complexity to assign the robot idle time as robot waiting time such that the wafer delay time in PMs can be reduced as much as possible. Furthermore, the obtained schedule by these algorithms is optimal in terms of the cycle time. Besides, the developed algorithms can be easily embedded into the controller of cluster tools by facility engineers. Therefore, this work has a practical value.

Diamond offers great potential for use as a thermal spreader in various applications, including power electronics and radio-frequency (RF) applications. However, to be used as an efficient thermal spreader, the atomically smooth surface of the diamond is critical to be bonded with chips. Herein, a polishing technique for a 2-inch diameter wafer-scale bulk polycrystalline diamond substrate is proposed. In this work, 350 μm thick polycrystalline diamond is grown by the microwave plasma-assisted chemical vapor deposition (MPACVD) technique on a Si substrate at a growth rate of 8 µm/h. Thereafter, a three-step polishing process was applied to achieve an atomically smooth surface, consisting of grinding using a diamond slurry with an iron plate, ICP etching using the SF6 gas, and final mechanical polishing using a resin-bonded diamond wheel. Surface roughness of diamond characterized by atomic force microscopy showed the significantly reduced from 900 nm to 0.3 nm. Hence, this study provide the practical methods for obtaining atomically smooth diamond films suitable for thermal management in various areas including power electronics and RF devices.

In this work, the static and dynamic characteristics of a 1.55 μm optical-fiber transmitter based on wafer-fused VCSEL were studied. The device demonstrated single-mode lasing with SMSR >30 dB over a wide range of currents, and the maximum optical output power at the fiber end more than 2.5 mW. The measured –3 dB modulation bandwidth exceeded 11 GHz, and the maximum bit rate achieved was 25 Gbps. Analysis of the lasing spectra under different amplitude modulations was carried out. Positive chirping (spectra broadening) and fiber chromatic dispersion were limiting factors for the data transmission over SMF-28 fiber., В работе были исследованы статические и динамические характеристики оптоволоконного передатчика на основе ВИЛ спектрального диапазона 1.55 мкм, полученного технологией спекания пластин. Прибор демонстрирует одномодовую генерацию с SMSR >30 дБ в широком диапазоне рабочих токов, а максимальная оптическая мощность на выходе волокна превышает 2.5 мВт. Измеренная эффективная частота модуляции превышает 11 ГГц, а максимальная достигнутая скорость передачи данных составила 25 Гбит/с. Был проведен анализ спектров излучения при различной амплитудной модуляции. Положительный чирпинг-эффект (уширение спектра) и хроматическая дисперсия волокна лимитируют дальность передачи данных.

Silicon wafer slicing is a crucial process of solar cell fabrication, this process often stains the silicon wafer surface, Thus, this work systematically investigated the composition, source, cleaning method of typical white spot stains on silicon wafer surface. The EDS and XPS results showed that the white spot stains contained CaCO3 and SiO2 that are basically consistent with the filler components in sticky stick glue. Meanwhile, The effects of stains on copper deposition and copper-assisted chemical etching were systematically studied, the white spot stain was still attached on silicon after the deposition and the etching process, we have fond that the stains can affect the uniform deposition of copper particles on the surface of the silicon wafer, it also impede the catalytic etching process of copper particles. Finally, the KOH solution combined with the ultrasonic field was proposed to remove the surface stains of the silicon wafer. This study has important guidance on knowledge and cleaning of silicon wafer contamination for fabricating high-efficiency solar cells.

The utilisation of alginate polymers for wound healing is well explored; however, little attention is paid towards the optimisation of the manufacturing process, especially in regards to the final morphological and rheological properties that are imparted to the alginate matrix. This is important as it helps to establish a set of guidelines for the consistent fabrication of mechanically strong polymer wafers, which in the context of manufacturing and production contributes to the reduction in research and development time required. In this study, the order of application with respect to cross-linking and freeze-drying parameters have been investigated, which shown to result in distinct differences in terms of their overall morphology and mechanical strength. The application of freeze-drying before cross-linking results in the uniform distribution of cross-links throughout the alginate wafer, thereby producing a mechanically strong polymer wafer that retains the dehydrated matrices original thickness and architecture. Based on the observed data, freeze-drying prior to cross-linking facilitates the increased permeation and distribution of the cross-linker solution into the polymer matrix, thus resulting in the uniform distribution of ionic cross-links, which is necessary to produce a more mechanically superior polymer matrix.

Recently, as an alternative solution for overcoming the scaling-down limitations of logic devices with design length of less than 3 nm and enhancing DRAM operation performance, 3D heterogeneous packaging technology has been intensively researched, essentially requiring Si wafer polishing at a very high Si polishing rate (500 nm/min) by accelerating the degree of the hydrolysis reaction (i.e., Si-O-H) on the polished Si wafer surface during CMP. Unlike conventional hydrolysis reaction accelerators (i.e., sodium hydroxide and potassium hydroxide), a novel hydrolysis reaction accelerator with amine functional groups (i.e., 552.8 nm/min for ethylenediamine) surprisingly presented an Si wafer polishing rate >3 times higher than that of conventional hydrolysis reaction accelerators (177.1 nm/min for sodium hydroxide). This remarkable enhancement of the Si wafer polishing rate for ethylenediamine was principally the result of (i) the increased hydrolysis reaction, (ii) the enhanced degree of adsorption of the CMP slurry on the polished Si wafer surface during CMP, and (iii) the decreased electrostatic repulsive force between colloidal silica abrasives and the Si wafer surface. A higher ethylenediamine concentration in the Si wafer CMP slurry led to a higher extent of hydrolysis reaction and degree of adsorption for the slurry and a lower electrostatic repulsive force; thus, a higher ethylenediamine concentration resulted in a higher Si wafer polishing rate. With the aim of achieving further improvements to the Si wafer polishing rates using Si wafer CMP slurry including ethylenediamine, the Si wafer polishing rate increased remarkably and root-squarely with the increasing ethylenediamine concentration.

In semiconductor foundries, wafer map defect analysis is crucial to prevent yield excursion. However, traditional manual inspection can hardly meet the high throughput demand. Deep learning based automatic defect detection shows promising efforts to achieve high accuracy and efficiency, yet the current approaches’ performance is limited by the imbalanced dataset and lack of interpretability. In this paper, we propose a Variational Autoencoder Enhanced Deep Learning Model (VAEDLM) for wafer defect imbalanced classification. It is light-weighted and effective in wafer defect pattern recognition on imbalanced dataset. It used variational autoencoder and decoder to generate similar wafer defect maps and a refined deep convolutional neural network for feature learning. We demonstrate the method using an authentic wafer map dataset, WM-811K. The performance is not only significantly improved after data augmentation, but it also beats the state-of-the art methods, reaching 99.19% accuracy, 99.10% recall, 99.23% precision, 99.96% AUC and 99.16% for F1-score. It clearly demonstrates the method’s efficacy to deal with the imbalanced defect pattern. Our study using saliency map and t-SNE further leads to enhanced interpretability.

Purpose This paper aims to investigate the root causes of and implement the improvements for the inter layer dielectric (ILD) crack for LQFP C90FG (CMOS90 Floating Gate) wafer technology devices in copper wire bonding process. Design/methodology/approach Failure analysis was conducted including cratering, scanning electron microscopy inspection and focus ion beam cross-section analysis, which showed ILD crack. Root cause investigation of ILD crack rate sudden jumping was carried out with cause-and-effect analysis, which revealed the root cause is shallower lead frame down-set. ILD crack mechanism deep-dive on ILD crack due to shallower lead frame down-set, which revealed the mechanism is lead frame flag floating on heat insert. Further investigation and energy dispersive X-ray analysis found the Cu particles on heat insert is another factor that can result in lead frame flag floating. Findings Lead frame flag floating on heat insert caused by shallower lead frame down-set or foreign matter on heat insert is a critical factor of ILD crack that has never been revealed before. Weak wafer structure strength caused by thinner wafer passivation1 thickness and sharp corner at Metal Trench (compared with the benchmarking fab) are other factors that can impact ILD crack. Originality/value For ILD crack improvement in copper wire bonding, besides the obvious factors such as wafer structure and wire bonding parameters, also should take other factors into consideration including lead frame flag floating on heat insert and heat insert maintenance.

While two-dimensional (2D) hexagonal boron nitride (h-BN) is emerging as an atomically thin and dangling bond-free insulating layer for next-generation electronics and optoelectronics, its practical implementation into miniaturized integrated circuits has been significantly limited due to difficulties in large-scale growth directly on epitaxial semiconductor wafers. Herein, the realization of a wafer-scale h-BN van der Waals heterostructure with a 2 in. AlGaN/GaN high-electron mobility transistor (HEMT) wafer using metal-organic chemical vapor deposition is presented. The combination of state-of-the-art microscopic and spectroscopic analyses and theoretical calculations reveals that the heterointerface between ∼2.5 nm-thick h-BN and AlGaN layers is atomically sharp and exhibits a very weak van der Waals interaction without formation of a ternary or quaternary alloy that can induce undesired degradation of device performance. The fabricated AlGaN/GaN HEMT with h-BN shows very promising performance including a cutoff frequency (fT) and maximum oscillation frequency (fMAX) as high as 28 and 88 GHz, respectively, enabled by an effective passivation of surface defects on the HEMT wafer to deliver accurate information with minimized power loss. These findings pave the way for practical implementation of 2D materials integrated with conventional microelectronic devices and the realization of future all-2D electronics.

Wafer rotational grinding is widely employed for back-thinning and flattening of semiconducting wafers during the manufacturing process of integrated circuits. Grit cutting depth is a comprehensive indicator that characterizes overall grinding conditions, such as the wheel structure, geometry, abrasive grit size, and grinding parameters. Furthermore, grit cutting depth directly affects wafer surface/subsurface quality, grinding force, and wheel performance. The existing grit cutting depth models for wafer rotational grinding cannot provide reasonable results due to the complex grinding process under extremely small grit cutting depth. In this paper, a new grit cutting depth model for wafer rotational grinding is proposed which considers machining parameters, wheel grit shape, wheel surface topography, effective grit number, and elastic deformation of the wheel grit and the workpiece during the grinding process. In addition, based on grit cutting depth and ground surface roughness relationship, a series of grinding experiments under various grit cutting depths are conducted to produce silicon wafers with various surface roughness values and compare the predictive accuracy of the proposed model and the existing models. The results indicate that predictions obtained by the proposed model are in better agreement with the experimental results, while accuracy is improved by 40%–60% compared to the previous models.

Driven by electrostatic attraction, Ce4+ ions or/and positively charged detonation nanodiamond (DND) particles can absorb onto negatively charged polystyrene (PS) spherical colloids. Three types of core-shell structured composite abrasives, PS@CeO2, PS@DND and PS@CeO2/DND, can thus be assembled. When PS@CeO2 and PS@DND were used to polish sapphire wafer at pad rotating speed of 120–150 r/min and load pressure of ~3 kg, the material removing rate (MRR) exceeded 1.0 μm h−1, 10–20 % higher than unitary abrasives. The surface profile roughness (Ra) for wafer polished by these two composite abrasives was respectively 1.25 and 0.63 nm, which is superior to CeO2 (Ra = 1.38 nm) and DND (Ra = 1.29 nm). When using PS@CeO2/DND, the polishing interface area can be increased owing to the combined effect of elastic PS spheres and intensively coated CeO2 and DND. Meanwhile, the synergistic mechanism of sapphire-CeO2 chemical reaction and the strong mechanical abrasion of DND particles benefit the polishing efficiency. MRR for this ternary composite abrasive attained 1.4–1.7 μm h−1 while sapphire can be smoothed to a sub-nanoscale roughness.

A kind of facilities for wafer fabrication, cluster tools (CTs) need to close down to an idle state from time to time because of periodical maintenance and switches from one type of lots to another, which is called a normal close-down process (NCDP). It is crucial to optimize such a transient process since it tends to occur more and more frequently due to customization. Also, process modules (PMs) in CTs are known to be failure-prone. Once a PM failure occurs, a tool needs to close down to an idle state as well, which is different from NCDP and is called a failure close-down process (FCDP). With wafer residency time constraints (WRTCs) being imposed, close-down process optimization for such a tool is challenging, since one needs to not only finish this process as soon as possible but also meet WRTCs during this transient process. In order to tackle this problem, this article first introduces steady state scheduling problems. Then, with a presented backward robot task sequence, a linear programming model is first proposed to optimize NCDP. To deal with the PM failures, efficient PM failure response policies are formulated for the cases in which a PM fails. Then, four linear programs are proposed to optimize an FCDP. Finally, industrial case studies are given to show the usefulness of the proposed approaches.

The semiconductor, β-Ga2O3 is attractive for applications in high power electronic devices with low conduction loss due to its ultra-wide bandgap (∼4.9 eV) and large Baliga's figure of merit. However, the thermal conductivity of β-Ga2O3 is much lower than that of other wide/ultra-wide bandgap semiconductors, such as SiC and GaN, which results in the deterioration of β-Ga2O3-based device performance and reliability due to self-heating. To overcome this problem, a scalable thermal management strategy was proposed by heterogeneously integrating wafer-scale single-crystalline β-Ga2O3 thin films on a highly thermally conductive SiC substrate. Characterization of the transferred β-Ga2O3 thin film indicated a uniform thickness to within ±2.01%, a smooth surface with a roughness of 0.2 nm, and good crystalline quality with an X-ray rocking curves (XRC) full width at half maximum of 80 arcsec. Transient thermoreflectance measurements were employed to investigate the thermal properties. The thermal performance of the fabricated β-Ga2O3/SiC heterostructure was effectively improved in comparison with that of the β-Ga2O3 bulk wafer, and the effective thermal boundary resistance could be further reduced to 7.5 m2K/GW by a post-annealing process. Schottky barrier diodes (SBDs) were fabricated on both a β-Ga2O3/SiC heterostructured material and a β-Ga2O3 bulk wafer. Infrared thermal imaging revealed the temperature increase of the SBDs on β-Ga2O3/SiC to be one quarter that on the β-Ga2O3 bulk wafer with the same applied power, which suggests that the combination of the β-Ga2O3 thin film and SiC substrate with high thermal conductivity promotes heat dissipation in β-Ga2O3-based devices.

Defect patterns on semiconductor wafer maps point to different manufacturing problems. Consequently, they have become key factors in identifying and resolving the root causes of yield improvement. Perhaps not surprisingly, the probability of having multiple defect patterns on a wafer map has increased in tandem with advances in manufacturing technology. Prior research on defect patterns has focused primarily on image classification methods which are neither good at mixed-type defect pattern classification nor able to provide locational information for further analysis. This study develops a framework that integrates a Mask R-CNN-based instance segmentation model with copy-paste and rotational data augmentation. The proposed method is able to precisely classify and locate defect patterns on a wafer map given limited training data, tasks which can help companies identify the manufacturing root causes of defects in a timely manner when ramping up their production for yield enhancement. Our experiments were performed using real-world WM-811K data. Using COCO pre-trained weights and only 1,056 items of original training data, the model reached an accuracy of 97.7% on single-type classification. Mixed-type classification hamming loss, exact match and accuracy were 0.155, 69% and 82%, respectively.

Real-time process monitoring is a vital technique to maintain safety and quality in the wafer fabrication processes. Hence, statistical process monitoring methods such as statistical process control chart, principal component analysis have been widely applied in wafer fabrication. However, these methods often suffer from the performance degradation problem caused by run-to-run (R2R) variations such as uneven duration and R2R drifts. In this paper, we propose a real-time monitoring framework for continuous wafer fabrication processes with uneven duration and R2R drifts. In this framework, processes are divided into several phases and further aligned in a real-time manner to solve the uneven duration problem. Then, R2R drifts are compensated by a down-sampling seasonal autoregressive integrated moving average model and a moving window multi-batch forecast strategy. Finally, multiphase multiway principal component analysis models are built on the compensated data to monitoring the processes. The efficiency of this framework is demonstrated by a case study on a plasma etch process. The results indicate that the proposed framework can diminish the influence of R2R variations and improve the monitoring model performance.

Adding ferromagnetism into semiconductors attracts much attentions due to its potential usage of magnetic spins in novel devices, such as spin field-effect transistors. However, it remains challenging to stabilize their ferromagnetism above room temperature. Here we introduce an atomic chemical-solution strategy to grow wafer-size NiO thin films with controllable thickness down to sub-nanometer scale (0.92 nm) for the first time. Surface lattice defects break the magnetic symmetry of NiO and produce surface ferromagnetic behaviors. Our sub-nanometric NiO thin film exhibits the highest reported room-temperature ferromagnetic behavior with a saturation magnetization of 157 emu/cc and coercivity of 418 Oe. Attributed to wafer size, the easily-transferred NiO thin film is further verified in a magnetoresistance device. Our work provides a sub-nanometric platform to produce wafer-size ferromagnetic NiO thin films as atomic layer magnetic units in future transparent magnetoelectric devices.

In considering the critical role of crystal orientation and working temperature in shaping overall performance of piezoresistive pressure microsensors, this study investigates the effect of wafer orientation (i.e., crystal orientation) and working temperature on thermomechanical and fracture behaviour of a P-type silicon wafer used in pressure sensors. The study was carried out using analytical analysis, based on Kirchhoff–Love plate theory, and numerical analyses side by side with experimental investigations for validation and comparison purposes. The study addresses the following objectives: (1) to investigate the effects of working temperature, wafer positioning and crystal orientation on deflection and fracture behaviour of a silicon membrane; (2) to compare wafer deflections obtained experimentally to those obtained from simulations and numerical approaches; and (3) to determine the effect of maximum wafer deflection on crack initiation and fracture mode through the application of an experimental thermomechanical technique. An agreement between experimental and simulated deflection values of the Si wafer within a temperature range of 25–80 °C was concluded. Moreover, when working temperatures are below 100 °C, the fracture mode is highly brittle when a wafer is oriented at 0° and 45° with respect to [110] directions, whereas the wafer tends to render some ductility at temperatures above 120 °C. It was also found that at room temperature fracture occurs at a deflection of about 389 µm and 463 µm when the crystal is oriented at 45° and 0°, respectively.

Transition metal dichalcogenides (TMDs) are materials that can exhibit intriguing optical properties like a change of the bandgap from indirect to direct when being thinned down to a monolayer. Well-resolved narrow excitonic resonances can be observed for such monolayers although only for materials of sufficient crystalline quality and so far mostly available in the form of micrometer-sized flakes. A further significant improvement of optical and electrical properties can be achieved by transferring the TMD on hexagonal boron nitride (hBN). To exploit the full potential of TMDs in future applications, epitaxial techniques have to be developed that not only allow the growth of large-scale, high-quality TMD monolayers but also allow the growth to be performed directly on large-scale epitaxial hBN. In this work, we address this problem and demonstrate that MoSe2 of high optical quality can be directly grown on epitaxial hBN on an entire 2 in. wafer. We developed a combined growth theme for which hBN is first synthesized at high temperature by metal organic vapor phase epitaxy (MOVPE) and as a second step MoSe2 is deposited on top by molecular beam epitaxy (MBE) at much lower temperatures. We show that this structure exhibits excellent optical properties, manifested by narrow excitonic lines in the photoluminescence spectra. Moreover, the material is homogeneous on the area of the whole 2 in. wafer with only ±0.14 meV deviation of excitonic energy. Our mixed growth technique may guide the way for future large-scale production of high quality TMD/hBN heterostructures.

This paper presents an all-SiC fiber-optic Fabry-Perot (FP) pressure sensor based on the hydrophilic direct bonding technology for the applications in the harsh environment. The operating principle, fabrication, interface characteristics, and pressure response test of the proposed all-SiC pressure sensor are discussed. The FP cavity is formed by hermetically direct bonding of two-layer SiC wafers, including a thinned SiC diaphragm and a SiC wafer with an etched cavity. White light interference is used for the detection and demodulation of the sensor pressure signals. Experimental results demonstrate the sensing capabilities for the pressure range up to 800 kPa. The all-SiC structure without any intermediate layer can avoid the sensor failure caused by the thermal expansion coefficient mismatch and therefore has a great potential for pressure measurement in high temperature environments.

Scheduling semiconductor wafer manufacturing systems has been viewed as one of the most challenging optimization problems owing to the complicated constraints, and dynamic system environment. This paper proposes a fuzzy hierarchical reinforcement learning (FHRL) approach to schedule a SWFS, which controls the cycle time (CT) of each wafer lot to improve on-time delivery by adjusting the priority of each wafer lot. To cope with the layer correlation and wafer correlation of CT due to the re-entrant process constraint, a hierarchical model is presented with a recurrent reinforcement learning (RL) unit in each layer to control the corresponding sub-CT of each integrated circuit layer. In each RL unit, a fuzzy reward calculator is designed to reduce the impact of uncertainty of expected finishing time caused by the rematching of a lot to a delivery batch. The results demonstrate that the mean deviation (MD) between the actual and expected completion time of wafer lots under the scheduling of the FHRL approach is only about 30 % of the compared methods in the whole SWFS.

Conductive atomic force microscopy (C-AFM) was employed to perform conductivity measurements on a facet-specific Cu2O cube, octahedron, and rhombic dodecahedron and intrinsic Si {100}, {111}, and {110} wafers. Similar I–V curves to those recorded previously using a nanomanipulator were obtained with the exception of high conductivity for the Si {110} wafer. Next, I–V curves of different Cu2O–Si heterostructures were evaluated. Among the nine possible arrangements, Cu2O octahedron/Si {100} wafer and Cu2O octahedron/Si {110} wafer combinations show good current rectification behaviors. Under white light illumination, Cu2O cube/Si {110} wafer and Cu2O rhombic dodecahedron/Si {111} wafer combinations exhibit the largest degrees of photocurrent, so such interfacial plane-controlled semiconductor heterojunctions with light sensitivity can be applied to make photodetectors. Adjusted band diagrams are presented highlighting different interfacial band bending situations to facilitate or inhibit current flow for different Cu2O–Si junctions. More importantly, the observation of clear current-rectifying effects produced at the semiconductor heterojunctions with properly selected contacting faces or planes implies that novel field-effect transistors (FETs) can be fabricated using this design strategy, which should integrate well with current chip manufacturing processes., The Cu2O octahedron/Si {100} wafer combination gives a large current-rectifying effect. The Cu2O rhombic dodecahedron/Si {111} wafer combination shows a notable photocurrent response.

Electron beam inspection (EBI) with high resolution is a promising technique to improve the defect inspection on the surface of patterned wafer. However, high resolution usually means long inspection time, which results in the low throughput and limitation of EBI applied in practice. This study aims to optimize the inspection time of EBI by reducing the total number of inspection regions without loss of the accuracy. We first refine this defect inspection optimization problem as a partial congruent square cover problem. Then, we propose two novel mixed-integer linear programming models for this problem. To deal with the large-scale problems, an approximation algorithm is developed to obtain the high-quality solutions. This approximation algorithm efficiently utilizes the linear programming (LP) rounding technique and greedy strategy based on the proposed model. Compared with the existing algorithms in the literature, numerical results show the superiority of the proposed model and algorithm. Note to Practitioners —Defect inspection is a key process in wafer fabrication for identifying and inspecting the patterning defects generated during the complicated fabrication processes. Electron beam inspection (EBI) takes place of optical inspection gradually as the design rules keep shrinking and the circuits are more susceptible to nanoscale killer defects. Low throughput is the main drawback of EBI and the improvements on throughput have far-reaching significance on the high volume manufacturing of semiconductor products. This study aims to reduce the number of inspection regions to improve the total inspection time in the EBI process. Considering that the inspection time for each inspection region is constant, less inspection regions means less total inspection time. However, the positions of inspection regions are arbitrary across the continuous planar space, putting pressure on modeling and solving the problem. A preprocessing algorithm is designed to discover a limited number of candidate positions of inspection regions without loss of optimality, which greatly simplifies the problem. For dealing with large-scale instances, an approximation algorithm combining linear programming (LP)-rounding technique and greedy strategy is designed to get near optimal solutions. Since the number of inspection regions is one key factor determining the total inspection time, the proposed optimization methods have a potential to be applicable to enhance the efficiency of advanced EBI platforms, such as ASML HMI eP series.

The properties of a learning-based system are particularly relevant to the process study of the unknown behavior of a system or environment. In the semiconductor industry, there is regularly a partially observable system in which the entire state of the process is not directly or fully visible due to uncertainties or disturbances. The model for studying such a system that permits uncertainties regarding the stochastic (Markov) process for state information acquisition is called a partially observable Markov decision process (POMDP). This study aims to deal with the optimization issue of compensation control bias of a dynamic multilayer lithography process in wafer fabrication with prior information, the existence of high-dimensionality, and unmeasurable uncertainties. We show how the POMDP on a linear state-space model with uncertainties can encode the information from past runs and layers, and deal with accumulated overlay error at the current run and layer. The Gibbs sampling is applied to optimize the belief function of POMDP optimization approach. Note to Practitioners —The multilayer overlay error of the photolithography process is one of the remarkable and challenging issues in wafer fabrication. In a multilevel manufacturing process, errors occur at each level, which would be accumulated in the upstream operations. The optimization objective will be even more critical in a high-mixed fabrication process. In this study, the learning-based control system emerged with the state-space model compensates the multilayer overlay error. The Gibbs sampling as a Bayesian approach as a core structure of optimization algorithm is utilized, which can be updated with information from engineering’s domain knowledge or estimated information about previous runs. The robustness of the proposed optimization algorithm is shown by comparing the distribution of overlay error with conventional methods and with a fast convergence rate of the learning algorithm.

In this work, a three-step silicon carbide (SiC) wafer manufacturing process using slurryless electrochemical mechanical polishing (ECMP) is proposed. In the first step, ECMP using fixed hard abrasives is applied to an as-sliced SiC wafer to rapidly remove the subsurface damage (SSD) and waviness induced during slicing. Then, the SiC wafer is polished using the second-step ECMP by employing a ceria grinding stone to remove the residual SSD and decrease the surface roughness. Finally, a finishing ECMP step employing a low potential is used to further decrease the surface roughness. Before applying this proposed three-step process to an as-sliced SiC wafer, a suitable grinding stone was selected for the first-step ECMP by evaluating the uniformity of the induced SSD layer and the obtained surface roughness. By applying the first step, i.e., ECMP using fixed-diamond abrasives, the root-mean-square (Sq) surface roughness decreased from 163.33 to 25.45 nm within 20 min with a material removal rate (MRR) of 62 μm/h. During the 30-min second step, the Sq and the maximum height (Sz) surface roughness values further decreased to 0.82 and 6.96 nm, respectively, with an MRR of 11 μm/h. Finally, the 60-min finishing step allowed the Sq and Sz surface roughness values to further decrease to 0.11 and 1.46 nm, respectively; furthermore, a surface with a step-terrace structure was obtained, which is comparable to the surface obtained by conventional chemical mechanical polishing. Overall, the proposed three-step slurryless ECMP method allowed for the rapid transformation of an unprocessed SiC wafer to an atomically smooth surface and is thus expected to reduce the cost and manpower required during SiC wafer manufacturing.

Curcumin is the main active constituent in turmeric, and it is one of the biopolyphenolic compounds. A cumulative body of research supports the use of curcumin in the treatment of wounds, yet poor water solubility and lack of therapeutic dose determination hamper its use for this therapeutic purpose. This work aimed at preparing novel curcumin wafer dressings to provide a favorable environment for wound healing. Hybrid synthetic (PVA, PVP, HPMC, and CMC) and biodegradable (sodium alginate and dextran) polymers were employed to prepare wafer dressings loaded with incremental three doses (2, 10, and 20 mg) of curcumin per a wafer dressing. The solvent casting method was used to prepare the dressings. Dimension, surface pH, mechanical properties, DSC, FTIR, XRD, erosion time, and in vitro release were studied. Skin wound healing assay was studied in Wistar albino rats. Six curcumin-loaded wafers were successfully prepared with good mechanical properties. Curcumin was dispersed in an amorphous/molecular form, as evidenced by thermal (DSC) and spectral (FTIR and XRD) analyses. Prolonged curcumin release (>24 h) was recorded for F6 (10 mg curcumin) and F7 (20 mg curcumin). Wound healing rate constants and time for 50% wound closure (T1/2) were estimated from a semi-log wound diameter versus time curve. A superior healing rate (up to 3-fold faster) was recorded for curcumin-loaded wafer dressings containing 10 mg (F6) with T1/2 of 7 days compared to 20 days for the placebo-treated group. These results warrant using the selected curcumin-loaded wafer dressing for safer and faster wound closure.

Penelitian bertujuan mengetahui taraf pemberian suplementasi wafer pakan daun lamtoro terhadap performa sapi Pasundan. Komposisi ransum terdiri dari pakan konvensional (dedak, jerami padi, dan hijauan rumput gajah), dan wafer suplemen pakan (daun lamtoro, bungkil kelapa, bungkil kedelai, molases, pollard, CaCO3, molases, dan CGM (Corn Gluten Meal) sebagai perlakuan. Penelitian ini menggunakan 4 perlakuan dan 5 kelompok sebagai ulangan. Perlakuan yang digunakan yaitu P0 = pakan konvensional (dedak, jerami padi, dan rumput gajah), P1 = pakan konvensional + 5 % wafer daun lamtoro, P2 = pakan konvensional + 10 % wafer daun lamtoro, P3 = pakan konvensional + 15 % wafer daun lamtoro. Pengelompokan didasarkan pada bobot badan yaitu sangat kecil (70,23 ± 9,15 kg), kecil (99,55 ± 7,87 kg), sedang (102,05 ± 7,29 kg), besar (115,23 ± 8,44 kg) dan sangat besar (136,59 ± 7,10 kg). Variabel yang diamati pada penelitian ini adalah bobot badan akhir, pertambahan bobot hidup harian, dan efisiensi pakan. Disimpulkan bahwa pemberian suplemen wafer pakan pada taraf 10 % (P2) nyata (P < 0,05) meningkatkan bobot badan akhir, pertambahan bobot hidup harian, dan efisiensi pakan sapi Pasundan.

This paper investigates a moiré-based mark for high-precision wafer bonding alignment. During alignment, the mark is combined with digital grating, which has the benefits of high precision and small size. A digital grating is superimposed on the mark to generate moiré fringes. By performing a phase calculation on the moiré fringe images corresponding to the upper and lower wafers, the relative offset of the upper and lower wafers can be accurately calculated. These moiré fringes are exceptionally stable, thereby enhancing the alignment stability. In this study, through practical experiments, we tested the rationality and practicability of the mark.