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In this paper, we present a multiplier based on a sequence of approximated accumulations. According to a given splitting point of the carry chains, the technique herein introduced allows varying the quality of the accumulations and, consequently, the overall product. Our approximate multiplier trades-off accuracy for a reduced latency (with respect to an accurate sequential multiplier) and exploits the inherent area savings of sequential over combinatorial approaches. We implemented multiple versions with different bit-width and accuracy configurations, targeting an FPGA and a 45nm ASIC to estimate resources, power consumption, and latency. We also present two error analyses of the proposed design based on closed-form analysis and simulations., 7 pages

Composable many-core systems enable the independent development and analysis of applications which will be executed on a shared platform where the mix of concurrently executed applications may change dynamically at run time. For each individual application, an off-line Design Space Exploration (DSE) is performed to compute several mapping alternatives on the platform, offering Pareto-optimal trade-offs in terms of real-time guarantees, resource usage, etc. At run time, one mapping is then chosen to launch the application on demand. In this context, to enable an independent analysis of each individual application at design time, so-called inter-application isolation schemes are applied which specify temporal or spatial isolation policies between applications. S.o.t.a. composable many-core systems are developed based on a fixed isolation scheme that is exclusively applied to every resource in every mapping of every application and use a timing analysis tailored to that isolation scheme to derive timing guarantees for each mapping. A fixed isolation scheme, however, heavily restricts the explored space of solutions and can, therefore, lead to suboptimality. Lifting this restriction necessitates a timing analysis that is applicable to mappings with an arbitrary mix of isolation schemes on different resources. To address this issue, we present an isolation-aware timing analysis that unlike existing analyses can handle multiple isolation schemes in combination within one mapping and delivers safe yet tight timing bounds by identifying and excluding interference scenarios that can never happen under the given combination of isolation schemes. Based on the timing analysis, we present a DSE which explores the choices of isolation scheme per resource within each mapping. Experimental results demonstrate the advantage of the proposed approach over approaches based on a fixed isolation scheme., Final version published at the 31st Euromicro Conference on Real-Time Systems (ECRTS 2019)

Modern embedded systems are becoming increasingly multifunctional, and, as a consequence, they more and more have to deal with dynamic application workloads. This dynamism manifests itself in the presence of multiple applications that can simultaneously execute and contend for resources in a single embedded system as well as the dynamic behavior within applications themselves. Such dynamic behavior in application workloads must be taken into account during the early system-level Design Space Exploration (DSE) of Multiprocessor System-on-Chip (MPSoC)-based embedded systems. Scenario-based DSE utilizes the concept of application scenarios to search for optimal mappings of a multi-application workload onto an MPSoC. To this end, scenario-based DSE uses a multi-objective genetic algorithm (GA) to identify the mapping with the best average quality for all the application scenarios in the workload. In order to keep the exploration of the scenario-based DSE efficient, fitness prediction is used to obtain the quality of a mapping. This fitness prediction implies that instead of using the entire set of all possible application scenarios, a small but representative subset of application scenarios is used to determine the fitness of mapping solutions. Since the representativeness of such a subset is dependent on the application mappings being explored, these representative subsets of application scenarios are dynamically obtained by means of coexploration of the scenario subset space. In this chapter, we provide an overview of scenario-based DSE and, in particular, present multiple techniques for fitness prediction using representative subsets of application scenarios: a stochastic, deterministic, and hybrid combination.

In this chapter we define what a mixed-time-criticality system is and what its requirements are. After defining the concepts that such systems should follow, we described CompSOC, which is one example of a mixed-time-criticality platform. We describe, in detail, how multiple resources, such as processors, memories, and interconnect, are combined into a larger hardware platform, and especially how they are shared between applications using different arbitration schemes. Following this, the software architecture that transforms the single hardware platform into multiple virtual execution platforms, one per application, is described.

The complexity of modern embedded systems, which are increasingly based on heterogeneous multiprocessor system-on-chip (MPSoC) architectures, has led to the emergence of system-level design. To cope with this design complexity, system-level design aims at raising the abstraction level of the design process from the register-transfer level (RTL) to the so-called electronic system level (ESL). However, this opens a large gap between deployed ESL models and RTL implementations of the MPSoC under design, known as the implementation gap. Therefore, in this chapter, we present the Daedalus methodology which the main objective is to bridge this implementation gap for the design of streaming embedded MPSoCs. Daedalus does so by providing an integrated and highly automated environment for application parallelization, system-level design space exploration, and system-level hardware/software synthesis and code generation.

This volume contains the papers accepted at the 1st Workshop on Resource Awareness and Adaptivity in Multi-Core Computing (Racing 2014), held in Paderborn, Germany, May 29-30, 2014. Racing 2014 was co-located with the IEEE European Test Symposium (ETS)., Website of the workshop: http://www12.cs.fau.de/racing2014/

Today the hardware for embedded systems is often specified in VHDL. However, VHDL describes the system at a rather low level, which is cumbersome and may lead to design faults in large real life applications. There is a need of higher level abstraction mechanisms. In the embedded systems group of the University of Twente we are working on systematic and transformational methods to design hardware architectures, both multi core and single core. The main line in this approach is to start with a straightforward (often mathematical) specification of the problem. The next step is to find some adequate transformations on this specification, in particular to find specific optimizations, to be able to distribute the application over different cores. The result of these transformations is then translated into the functional programming language Haskell since Haskell is close to mathematics and such a translation often is straightforward. Besides, the Haskell code is executable, so one immediately has a simulation of the intended system. Next, the resulting Haskell specification is given to a compiler, called CëaSH (for CAES LAnguage for Synchronous Hardware) which translates the specification into VHDL. The resulting VHDL is synthesizable, so from there on standard VHDL-tooling can be used for synthesis. In this work we primarily focus on streaming applications: i.e. applications that can be modeled as data-flow graphs. At the moment the CëaSH system is ready in prototype form and in the presentation we will give several examples of how it can be used. In these examples it will be shown that the specification code is clear and concise. Furthermore, it is possible to use powerful abstraction mechanisms, such as polymorphism, higher order functions, pattern matching, lambda abstraction, partial application. These features allow a designer to describe circuits in a more natural and concise way than possible with the language elements found in the traditional hardware description languages. In addition we will give some examples of transformations that are possible in a mathematical specification, and which do not suffer from the problems encountered in, e.g., automatic parallelization of nested for-loops in C-programs.

In this talk, we present watermarking and identification techniques for FPGA IP cores. Unlike most existing watermarking techniques, the focus of our techniques lies on ease of verification, even if the protected cores are embedded into a product. Moreover, we have concentrated on higher abstraction levels for embedding the watermark, particularly at the logic level, where IP cores are distributed as netlist cores. With the presented watermarking methods, it is possible to watermark IP cores at the logic level and identify them with a high likelihood and in a reproducible way in a purchased product from a company that is suspected to have committed IP fraud. The investigated techniques establish the authorship by verification of either an FPGA bitfile or the power consumption of a given FPGA.

Dynamic and partial reconfiguration of hardware architectures such as FPGAs and coarse grain processing arrays bring an additional level of flexibility in the design of electronic systems by exploiting the possibility of configuring functions on-demand during run-time. When compared to emerging software-programmable Multi-Processor System-on-a-Chip (MPSoC) solutions, they benefit a lot from lower cost, more dedication and fit to a certain problem class as well as power and area efficiency. This has led to many new ways of approaching existing research topics in the area of hardware design and optimization techniques. For example, the possibility of performing adaptation during run-time raises questions in the areas of dynamic control, real-time response, on-line power management and design complexity, since the reconfigurability increases the design space towards infinity.

From 11.07.10 to 16.07.10, Dagstuhl Seminar 10281 ``Dynamically Reconfigurable Architectures '' was held in Schloss Dagstuhl~--~Leibniz Center for Informatics. During the seminar, several participants presented their current research, and ongoing work and open problems were discussed. Abstracts of the presentations given during the seminar as well as abstracts of seminar results and ideas are put together in this paper. The first section describes the seminar topics and goals in general. Links to extended abstracts or full papers are provided, if available.

This presentation will focus on algorithms and reconfigurable tiled architectures for streaming DSP applications. The tile concept will not only be applied on chip level but also on board-level and system-level. The tile concept has a number of advantages: (1) depending on the requirements more or less tiles can be switched on/off, (2) the tile structure fits well to future IC process technologies, more tiles will be available in advanced process technologies, but the complexity per tile stays the same, (3) the tile concept is fault tolerant, faulty tiles can be discarded and (4) tiles can be configured in parallel. Because processing and memory is combined in the tiles, tasks can be executed efficiently on tiles (locality of reference). There are a number of application domains that can be considered as streaming DSP applications: for example wireless baseband processing (for HiperLAN/2, WiMax, DAB, DRM, DVB), multimedia processing (e.g. MPEG, MP3 coding/decoding), medical image processing, color image processing, sensor processing (e.g. remote surveillance cameras) and phased array radar systems. In this presentation the key characteristics of streaming DSP applications are highlighted, and the characteristics of the processing architectures to efficiently support these types of applications are addressed.

From 02.04.06 to 07.04.06, the Dagstuhl Seminar 06141 ``Dynamically Reconfigurable Architectures'' was held in the International Conference and Research Center (IBFI), Schloss Dagstuhl. During the seminar, several participants presented their current research, and ongoing work and open problems were discussed. Abstracts of the presentations given during the seminar as well as abstracts of seminar results and ideas are put together in this paper. The first section describes the seminar topics and goals in general. Links to extended abstracts or full papers are provided, if available.

Dynamic and partial reconfiguration of hardware architectures such as FPGAs and XPPs brings an additional level of flexibility in the design of electronic systems by exploiting the possibility of configuring functions on-demand during run-time. This has led to many new ways of approaching existing research topics in the area of hardware design and optimization techniques. For example, the possibility of performing adaptation during run-time raises questions in the areas of dynamic control, real-time response, on-line power management and design complexity, since the reconfigurability increases the design space towards infinity. This Dagstuhl Seminar on Reconfigurable Architectures has aimed at raising a few of these topics e.g. on-line placement, pre-routing/on-line routing trade-off, power minimization etc., and also at presenting novel ideas on how to overcome the difficulties introduced in dynamic reconfigurable systems.

We present an FPGA-based reconfigurable platform called Erlangen Slot Machine (ESM). The main advantages of this platform are: First, the possibility for each module to access peripherals independent from its location through a programmable crossbar, and local SRAM banks for individual modules. This physical design eases the implementation of run-time reconfigurable partial modules and enables an unrestricted relocation of modules on the device. We present our two-board ESM implementation and demonstrate a partially reconfigurable video filter application as well as a relocatable computer game including a dedicated inter-module communication scheme.

Many inpatients remain on expensive intravenous medications, even after they become able to take bioequivalent oral alternatives. We developed a computer intervention to identify such patients and to deliver alerts suggesting a switch to the oral medication. In the first phase of the project, alerts were delivered to pharmacists. The Brigham Integrated Computer System (BICS) was used to produce a daily report of patients receiving any of six targeted intravenous medications, who also had orders for an oral diet or other scheduled oral medications. Staff pharmacists screened the report and suggested IV to PO conversion in appropriate cases to the patient's nurses and/or physicians. Feedback was documented in the BICS system. Analysis of the pilot study showed that in 31.7% of cases, physicians agreed to change (or had just changed) the patient's medication from IV to PO. Further analysis of pilot (Phase I) data was performed against a variety of parameters in order to increase the fraction of alerts deemed appropriate for conversion. These more specific alerts can be sent directly to physicians.

The Internet is quickly changing the way business-to-consumer and business-to-business commerce is conducted in the world. The Electronic Revolution has also spawned a trend of price wars and, in some instances, chaos because of the zero-sum nature of the electronic channel. The technology has created an opportunity to get beyond the lose-lose nature of single issue price wars by determining sellers' and buyers' preferences across multiple issues and encouraging negotiations, thereby creating possible joint gains for all parties. We develop simple multiple issue algorithms and heuristics that could be used in electronic auctions and electronic markets, to match business to business and consumers based on dovetailing underlying interests and preferences. We provide arguments that such dovetailed matches should help stabilize markets and make them more efficient.

With the advent of the mass use of the Internet involving the classic use of e-mail, file transfer and now the more recent use of www applications, such as home pages, chat, Internet phone, audio and video and web broadcast systems, business transactions over the net are increasing dramatically. An important, yet relatively undeveloped component for electronic commerce is the negotiation of contracts and the resolution of disputes. We discuss Web-based technology and practice in supporting business negotiations and communication. The focus of the paper is on the present and the future promises of such technology.

Physician order entry is a key factor in improving the quality of healthcare, while simultaneously reducing its cost. This paper describes an editor, a database, and a run-time system for creating and executing highly customized, user modifiable, order entry templates. The system allows non-programmers to create new order entry templates rapidly. Over the past 18 months, the templates have been used on over 2500 patients to enter over 40,000 separate orders.

We added two advanced features to our automated alerting system. The first feature identifies and displays, at the time an alert is reviewed, relevant data filed between the login time of a specimen leading to an alerting result and the time the alert is reviewed. Relevant data is defined as data of the same kind as generated the alert. The other feature retracts alerts when the alerting value is edited and no longer satisfies the alerting criteria. We evaluated the two features for a 14-week period (new relevant data) and a 6-week period (retraction). Of a total of 1104 alerts in the 14-week evaluation, 286 (25.9%) had new relevant data displayed at alert review time. Of the 286, 75.2% were due to additions of comments to the original piece of alerting data; 24.1% were due to new or pending laboratory results of the same type that generated the alert. Two alerts (out of 490) were retracted in a 6 week period. We conclude that in our system, new clinically relevant data is often added between the time of specimen login and the time that an alerting result from that specimen is reviewed. Retractions occur rarely but are important to detect and communicate.

We developed and evaluated a system to automatically identify serious clinical conditions in inpatients. The system notifies the patient's covering physician via his pager that an alert is present and offers potential therapies for the patient's condition (action items) at the time he views the alert information. Over a 6 month period, physicians responded to 1214 (70.2%) of 1730 alerts for which they were paged; they responded to 1002 (82.5% of the 1214) in less than 15 minutes. They said they would take action in 71.5% of the alerts, and they placed an order directly from the alert display screen in 39.4%. Further study is needed to determine if this alerting system improves processes or outcomes of care.

We developed a computer application to support the ordering of chemotherapy. Key goals were to guard against errors in chemotherapy ordering and dosing, to, coordinate the outpatient and inpatient chemotherapy services, and to support the overall process flow of a chemotherapy cycle. In a six-month period, 512 daily-dose and 386 weekly-dose warnings were generated; 167 (19%) resulted in a cancellation or re-evaluation of the dose. The system has been well accepted, and has helped to coordinate the efforts of the many members of the oncology care team.

Our group has developed a computer system that supports all phases of the inpatient discharge process. The system fills in most of the physician's discharge order form and the nurse's discharge abstract, using information available from sign-out, order entry, scheduling, and other databases. It supplies information for referrals to outside institutions, and provides a variety of instruction materials for patients. Discharge forms can be completed in advance, so that the patient is not waiting for final paperwork. Physicians and nurses can work on their components independently, rather than in series. Response to the system has been very favorable.

We have developed a provider-patient database system, known as Coverage List, which maintains the associations between house staff and inpatients in a teaching hospital. Coverage List automatically links each patient to the proper resident when the patient is admitted, and updates the linkage whenever the resident coverage changes due to night or weekend coverage, physician illness, changes in clinical rotations, and other factors. Using this association, decision-support applications that detect significant clinical events can transmit them directly to the responsible resident. Sign-out and patient-review systems, which collect information on all of a physician's patients, always know the patients for whom that physician is responsible. Nurses who need to contact a physician about a patient issue always know which physician is covering that patient. Coverage List also manages schedule entry and display for physicians, or for any other staff members. A physician can enter individual schedule changes, sign out her service and her pager for the day, and page consultants automatically without going through an operator. These functions support clinical practice directly and enhance the value of other clinical programs.

We examined the effect of computerized physician order entry on housestaff time use patterns, using time motion techniques. For both medical and surgical house officers, writing orders on the computer took about twice as long (p < 0.001), or 44 minutes for medical and 73 minutes for surgical house officers. Medical house officers recovered about half this time because some administrative tasks--e.g. looking for charts--were made easier. Within types of orders, sets of stereotyped orders took much less time with order entry, but one-time orders took longer. We have since developed strategies to make it easier to enter one-time orders.

The Brigham Integrated Computing System (BICS) provides a broad range of clinical and administrative data-management functions for Brigham and Women's Hospital (BWH), a 720-bed major urban teaching hospital. We describe here the development of an inpatient order-entry system (BICS-OE) which is fully integrated into the BICS clinical environment. BICS-OE uses direct entry of orders by physicians to improve order response time and minimize transcription problems. BICS-OE includes a number of novel features to enhance its acceptance by physician users and its benefit to clinical practice in the hospital. Dual-mode input gives users a choice of full-screen assistance with ordering, or an intelligent text mode which provides rapid entry of orders by direct typing. An automated primary/on-call coverage by direct typing. An automated primary/on-call coverage list directs patient alerts and cosigning requests to the proper physician. Variable order sets allow a large group of orders to be stored and entered rapidly, even when some of the orders may change for different conditions. Multitasking allows the user to check prior orders and labs while concurrently entering new orders. The system permits a wide range of order checking and alerts.

Nine WWW-based interfaces to clinical information systems were reviewed. Five have progressed past the proof of concept phase and into alpha testing in the clinical environment. All key features desirable in an advanced clinical information were present in at least one interface, however many implementations were rudimentary. Much human computer interface research and WWW tool development needs to occur before implementation of a WWW-based interface to a clinical information system should be considered for a mission-critical, production environment.

This thesis presents a highly automated design framework, called DaedalusRT, and several novel techniques. As the foundation of the DaedalusRT design framework, two types of dataflow Models-of-Computation (MoC) are used, one as timing analysis model and another one as the implementation model. The timing analysis model is used to formally reason about timing behavior of an application. In the context of DaedalusRT, the Mode-Aware Data Flow (MADF) MoC has been developed as the timing analysis model for adaptive streaming applications using different static modes. A novel mode transition protocol is devised to allow efficient reasoning of timing behavior during mode transitions. Based on the transition protocol, a hard real-time scheduling approach is proposed. On the other hand, the implementation model is used for efficient code generation of parallel computation, communication, and synchronization. In this thesis, the Parameterized Polyhedral Process Network (P3N) MoC has been developed to model adaptive streaming applications with parameter reconfiguration. An approach to verify the functional property of the P3N MoC has been devised. Finally, implementation of the P3N MoC on a MPSoC platform has shown that run-time performance penalty due to parameter reconfiguration is negligible.

MORA is a novel platform for high-level FPGA programming of streaming vector and matrix operations, aimed at multimedia applications. It consists of soft array of pipelined low-complexity SIMD processors-in-memory (PIM). We present a Domain-Specific Language (DSL) for high-level programming of the MORA soft processor array. The DSL is embedded in C++, providing designers with a familiar language framework and the ability to compile designs using a standard compiler for functional testing before generating the FPGA bitstream using the MORA toolchain. The paper discusses the MORA-C++ DSL and the compilation route into the assembly for the MORA machine and provides examples to illustrate the programming model and performance.

This paper presents a solution for secure remote reconfiguration of FPGAs. Communicating the bitstream has to be done in a secure manner to prevent an attacker from reading or altering the bitstream. We propose a setup in which the FPGA is the single device in the system's zone-of-trust. The result is an FPGA architecture that is divided into a static and a dynamic region. The static region holds the communication, security and reconfiguration facilities, while the dynamic region contains the targeted application.