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The use of photovoltaic (PV) systems as the energy source of electrical distributed generators (DG) is gaining popularity, due to the progress of power electronics devices and technologies. Large-scale solar PV power plants are becoming the preferable solution to meet the fast growth of electrical energy demand, as they can be installed in less than one year, as compared to around four years in the case of conventional power plants. Modular multilevel inverters (MMIs) are the best solution to connect these large-scale PV plants to the medium-voltage (MV) grid, due to their numerous merits, such as providing better power quality, having higher efficiency, providing better reliability, and their scalability. However, MMIs are still progressing and need some improvement before they can be implemented safely in the industrial, medium, and high voltage networks. The main purpose of this paper is to review the present MMIs topologies when used in PV applications. The review aims to present a comprehensive study of the various recent submodule circuits associated with MMI topologies. Maximum power point tracking (MPPT) control schemes for PV inverters will be explored extensively. Then, the different control strategies of PV MMIs will be presented and compared to give a holistic overview of the submodules balancing techniques, ranges, and capabilities under balanced and unbalanced grid conditions. In addition, the paper will discuss the future of PV MMIs systems in electricity networks.

Publisher Copyright: CCBY Copyright: Copyright 2021 Elsevier B.V., All rights reserved. | openaire: EC/H2020/824070/EU//CONNECT Minimally invasive implantation of subdural electrodes can dramatically benefit the patients with various neurological diseases. In modern clinical practice, the implantation procedure of the electrode arrays remains traumatic for patients and increases postoperative infection risk. Here we report a design and insertion technique of thermally activated shape-memory polymer-based electrode array that can recover up to ten times length deformation. The compressed four-centimeter wide array can be easily packed into a three-millimeter diameter tube and subsequently deployed thought five-millimeter opening in a restricted space between a brain phantom and a simulated skull. The mechanical properties of the developed array are comparable to the materials traditionally employed for the purpose, and the electrical and signal recording properties are preserved after shape deformation and recovery. Additionally, the array is biocompatible and exhibits conformability to a curvy brain surface. The results demonstrate that insertion of the electrode array through a small hole into a restricted space similar to subdural cavity is possible, which may inspire future solution of minimal invasive implantation for patients suffering from epilepsy, amyotrophic lateral sclerosis or tetraplegia.

This paper introduces a novel modeling approach that allows to obtain fast simulations of pulsewidth-modulated DC-DC switched-mode power supplies (SMPS). The proposed methodology combines the use of precise switched models during transient evolutions and averaged models during steady-state or slowly varying conditions. In that way, the resulting mixed modeling approach enables to obtain the detailed switching behavior of SMPS in the context of long-term simulations. The commutation between models is automatically performed in runtime by an algorithm that detects the transient or slowly varying condition according to the evolution of some model variables. When the precise switched model is used, the mentioned algorithm also adjusts the averaged model parameters so that its results are accurate irrespective of the operating point. This paper also describes the implementation of the methodology in the Modelica language and reports simulation experiments showing that the results are as accurate as those obtained using precise switched models, but several times faster. Fil: Migoni, Gustavo Andres. Consejo Nacional de Investigaciones Científicas y Técnicas. Centro Científico Tecnológico Conicet - Rosario. Centro Internacional Franco Argentino de Ciencias de la Información y de Sistemas. Universidad Nacional de Rosario. Centro Internacional Franco Argentino de Ciencias de la Información y de Sistemas; Argentina Fil: Romero, Monica. Consejo Nacional de Investigaciones Científicas y Técnicas. Centro Científico Tecnológico Conicet - Rosario. Centro Internacional Franco Argentino de Ciencias de la Información y de Sistemas. Universidad Nacional de Rosario. Centro Internacional Franco Argentino de Ciencias de la Información y de Sistemas; Argentina Fil: Bergero, Federico. Consejo Nacional de Investigaciones Científicas y Técnicas. Centro Científico Tecnológico Conicet - Rosario. Centro Internacional Franco Argentino de Ciencias de la Información y de Sistemas. Universidad Nacional de Rosario. Centro Internacional Franco Argentino de Ciencias de la Información y de Sistemas; Argentina Fil: Kofman, Ernesto. Consejo Nacional de Investigaciones Científicas y Técnicas. Centro Científico Tecnológico Conicet - Rosario. Centro Internacional Franco Argentino de Ciencias de la Información y de Sistemas. Universidad Nacional de Rosario. Centro Internacional Franco Argentino de Ciencias de la Información y de Sistemas; Argentina

Here, the setup of a three-phase 100 A linear amplifier is proposed. This work focusses on the use of this linear amplifier as power element for machine-emulation. In contrast to common power electronics, a linear amplifier avoids ripple content in the output current caused by switched-mode operation.

This article presents a modulator for optical wireless communication (OWC) via LEDs, controlled by a dual closed loop. While the potential communication speed and performance of OWC have received a lot of research attention, the design of appropriate modulator circuits has not been studied so widely. This article addresses the control aspects to minimize power losses and to ensure automatic adaptation to component spreads or aging, for “high-power” LED emitters. We initially address a “low-bandwidth– system, particularly suited for indoor camera-based detection, and then a “higher bandwidth” one for Li-Fi data communication. In contrast to maximizing data throughput as it applies to high-speed modulators, low-speed modulators aim at high power and high efficiency in general lighting applications. Specifically, for the high-power modulator, we propose a control strategy that allows a wide range of combinations of LED types and LED power supplies. The power consumption of the modulator is minimized by voltage margin setting that is automatically adapt to the modulation and the LED type using the nonlinear detector. The common industry practice is to use constant-current LED drivers for powering LEDs. After creating a theoretical framework of some generality to evaluate designs and control loops with rationals and verified models, we realize modulator designs that are supplied by constant current LED drivers and verify their performance by simulation and measurements.

In the last few decades, the use of power converters has become essential in the smart grid environment. Consequently, this leads to the presence of a high-level of conducted electromagnetic interference between the smart grid elements. This paper studies the effect of two power converter modulation techniques: conventional fixed-frequency modulation and spread-spectrum modulation, on the performance of the Power Line Communication (PLC) signal. The paper presents a practical implementation of the system and discusses the results for different operating scenarios.

A switch-mode power amplifier topology that can achieve both a high conversion efficiency and low-output signal distortion is introduced. Such systems are desirable for ultra-high precision amplifiers that, for example, drive actuators in nanometre-accuracy mechatronic positioning applications in integrated semiconductor manufacturing. An efficient Class-D power stage, which is limited in output signal quality due to its inherent half-bridge interlock time, is combined through a magnetically coupled inductor with a dual buck conversion stage that does not require interlock time and, due to its circulating bias current that defines the half-bridge switching waveforms, achieves very low-harmonic output signal distortion. The control system can seamlessly adjust the current sharing of the two converter stages such that overall conversion efficiencies over 95% and output total harmonic distortion values below −100 dB are achievable at power levels up to several kilowatts. Detailed computer simulations demonstrate the feasibility of the concept.

Boost DC–DC converters are widely used in non-conventional power conversions namely in solar and wind power generation systems. It is also used in switched mode power supplies. Since there is no filter inductor on output side, output current of boost converter is pulsed and it is not desirable. The quality of power required is very high when DC–DC converters are employed for transferring the requisite amount of power. In this study, the conventional cuk converter (CCC) having a continuous current at both input and output sides is taken as the candidate for performance analysis. Accordingly an interleaved cuk converter (ICC) is proposed and designed to reduce the input current ripple and also to improve transient performances. Both the CCC and the proposed ICC are simulated and validated experimentally. The proposed converter is having better efficiency attributable to cancellation of source current ripple, reduction of ripple content in both output voltage and current, and improvement of transient performance.

The evolution of solid-state lighting technology has transformed traditional solutions in lighting. High-brightness light-emitting diodes (HB-LEDs) have become very attractive light sources due to their excellent characteristics, namely high efficiency, a long lifetime, and low maintenance. It is evident that HB-LED drivers must be durable and efficient in order to enjoy these advantages. Moreover, to replace incandescent bulbs, the ac-to-dc HB-LED driver must be simple and have low size and comply with international regulations (i.e., injecting low-frequency harmonics into the mains supply). With the last modifications regarding low-power lighting equipment (i.e., SpanishMinistry of Education and Science under Project MINECO-13-DPI2013-47176- C2-2-R, by Government of the Principality of Asturias under the Project FC-15-GRUPIN14-143 and byEuropean Regional Development Fund (ERDF) grants

Under the concept of the Internet of Things, was designed a PCB to monitor faults in refrigerators or freezers, which use conventional compressors or non-inverters. It should be emphasized that these equipment belong to a cold chain, where it is considered approximately 2000 refrigerators. This solution includes among its main requirements Sigfox wireless communication, to send data or alarms from refrigerators or end nodes to the server in the cloud. One of the attractions to choose SigFox technology is its low cost as a communication service. Other aspects of design are: control the compressor, alert operational failures, measure the temperature inside the freezer, measure power consumption, voltage and current. Another fundamental requirement of the design is to achieve a low cost in its production to be in the margin of the sale of conventional temperature controllers, perhaps not equal, but not be well above the commercial value. With these premises, the hardware architecture is basically composed by a Switched-Mode Power Supply (SMPS), a control unit with a PIC32, 5VDC relays to switch an output of 220V AC, NTC temperature sensor, Power meter IC, battery charger, Sigfox communication module and E-Paper Display. © 2019 IEEE. Fondo Nacional de Ciencia Tecnología e Innovación: FP44842-502-2015 Department of Science, Information Technology and Innovation, Queensland Government Universidad Tecnológica de Pereira: FI1607T2004 Departamento Administrativo de Ciencia, Tecnología e Innovación, COLCIENCIAS: Colciencias Ministry of Information and Communications Technology, Iran The authors would like to acknowledge the cooperation of all partners within the Centro de Excelencia y Apropiación en Internet de las Cosas (CEA-IoT) project. The authors would also like to thank all the institutions that supported this work: the Colombian Ministry for the Information and Communications Technology (Ministerio de Tecnologías de la Información y las Comunicaciones - MinTIC) and the Colombian Administrative Department of Science, Technology and Innovation (Departamento Administrativo de Ciencia, Tecnología e Innovación - Colciencias) through the Fondo Nacional de Financiamiento para la Ciencia, la Tecnología y la Innovación Francisco José de Caldas (Project ID: FP44842-502-2015). The authors would also like to thank Universidad Tecnológica de Bolívar for partial financial support with the project Design and Implementation of an Application Prototype for Predictive Control of Temperature in Logistic Cold Chains (Project ID: FI1607T2004).

This paper presents a method to predict the real operation current wave-shape of Ferrite Core (FC) inductors in switching power supply applications involving a moderate inductor saturation. The method is based on a behavioral analytical model of inductance versus current saturation curve, obtained starting from the data provided by inductors manufacturers. The algorithm developed to solve the nonlinear model of the inductor can be applied to predict the range of the operating conditions involving a sustainable partial saturation for FC inductors, and the resulting method is best suited for the selection of minimum size inductors for high-power-density power supply design solutions.

© 2019 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes,creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. OmpSs@FPGA is the flavor of OmpSs that allows offloading application functionality to FPGAs. Similarly to OpenMP, it is based on compiler directives. While the OpenMP specification also includes support for heterogeneous execution, we use OmpSs and OmpSs@FPGA as prototype implementation to develop new ideas for OpenMP. OmpSs@FPGA implements the tasking model with runtime support to automatically exploit all SMP and FPGA resources available in the execution platform. In this paper, we present the OmpSs@FPGA ecosystem, based on the Mercurium compiler and the Nanos++ runtime system. We show how the applications are transformed to run on the SMP cores and the FPGA. The application kernels defined as tasks to be accelerated, using the OmpSs directives are: 1) transformed by the compiler into kernels connected with the proper synchronization and communication ports, 2) extracted to intermediate files, 3) compiled through the FPGA vendor HLS tool, and 4) used to configure the FPGA. Our Nanos++ runtime system schedules the application tasks on the platform, being able to use the SMP cores and the FPGA accelerators at the same time. We present the evaluation of the OmpSs@FPGA environment with the Matrix Multiplication, Cholesky and N-Body benchmarks, showing the internal details of the execution, and the performance obtained on a Zynq Ultrascale+ MPSoC (up to 128x). The source code uses OmpSs@FPGA annotations and different Vivado HLS optimization directives are applied for acceleration. This work is partially supported by the European Union H2020 program through the EuroEXA project (grant 754337), and HiPEAC (GA 687698), by the Spanish Government through Programa Severo Ochoa (SEV-2015- 0493), by the Spanish Ministry of Science and Technology (TIN2015-65316-P) and the Departament d’Innovació Universitats i Empresa de la Generalitat de Catalunya, under project MPEXPAR: Models de Programació i Entorns d’Execució Paral·lels (2014-SGR-1051).

This paper proposes a new modeling approach for ferrite-core (FC) power inductors used in switch-mode power supplies (SMPSs). In particular, a novel power-loss-dependent inductance behavioral model is proposed, whose parameters can be identified through a limited set of proper experimental measurements of inductor current and voltage. Unlike conventional thermal modeling approaches, which require information on core temperature, the proposed behavioral model relies only on easily measurable quantities. The model is also suitable for being implemented in circuit simulators. By comparing PSIM simulations and experimental measurements on a buck converter for commercial FC inductors, we show that the model allows a reliable prediction of the steady-state inductor current, under different SMPS working conditions.

This article proposes a systematic approach to determine the most suitable analogue redesign method to be used for forward-type converters under digital voltage mode control. The focus of the method is to achieve the highest phase margin at the particular switching and crossover frequencies chosen by the designer. It is shown that at high crossover frequencies with respect to switching frequency, controllers designed using backward integration have the largest phase margin; whereas at low crossover frequencies with respect to switching frequency, controllers designed using bilinear integration with pre-warping have the largest phase margins. An algorithm has been developed to determine the frequency of the crossing point where the recommended discretisation method changes. An accurate model of the power stage is used for simulation and experimental results from a Buck converter are collected. The performance of the digital controllers is compared to that of the equivalent analogue controller both in simulation and experiment. Excellent closeness between the simulation and experimental results is presented. This work provides a concrete example to allow academics and engineers to systematically choose a discretisation method.

An accurate measurement method to extract the common mode (CM) and the differential mode (DM) noise source impedances of a switched-mode power supply (SMPS) under its operating condition is developed and validated. With a proper premeasurement calibration process, the proposed method allows extraction of both the CM and the DM noise source impedances with very good accuracy. These noise source impedances come in handy to design an electromagnetic interference filter for an SMPS systematically with minimum hassle. Published version

Nowadays, the solid-sate lighting technology evolution has changed traditional solutions in lighting. High-Brightness Light–Emitting Diodes (HB-LEDs) have become very attractive light sources due to their excellent characteristics: high efficiency, high life-time and low maintenance. It is evident that HB-LED drivers must be durable and efficient to achieve these advantages. Moreover, for replacing incandescent bulbs, the ac-dc HB-LED driver must be low cost and comply with international regulations (i.e. injection of low frequency harmonics into the mains). Traditionally, authors have focused its efforts on increasing efficiency. All these solutions obviate the elimination of traditional electrolytic capacitor of ac to dc converters, highlighting that this is the price to pay for a very low-cost solution. This paper presents a new proposal to design a simple and low-cost ac to dc HB-LED driver for retrofit lamps without electrolytic capacitor. The proposed solution comes from a very well-known technique used in the past: Active Input Current Shapers (AICS), but in this case without electrolytic capacitor. If the electrolytic capacitor of an AICS is removed, then low frequency ripple arises in its intermediate dc bus, increasing the distortion of the line input which already has appreciable distortion. However, the increase of distortion is very slight. Also, the low frequency ripple is not transferred to the output due to the high output dynamic response of AICS, avoiding flickering. This paper presents a theoretical analysis that guarantees a trade of between compliance with international regulations and the use of other capacitor technologies different from the electrolytic one. Finally, a 24W experimental prototype has been built and tested in order to validate the theoretical results presented in this digest, Spanish Ministry of Education and Science under Project MINECO-13-DPI2013-47176- C2-2-R, by Government of the Principality of Asturias under the Project FC-15-GRUPIN14-143 and by European Regional Development Fund (ERDF) grants

This paper presents the design of a resonant converter with a switching frequency in the very high frequencyrange (30-300 MHz), a large step down ratio (10 times) and low output power (1 W). Several different invertersand rectifiers are analyzed and compared. The class E inverter and rectifier are selected based on complexity andefficiency estimates. Three different power stages are implemented; one with a large input inductor, one with a switch with small capacitances and one with a switch with low on resistance. The power stages are designed with the same specifications and efficiencies from 60:7􀀀82:9% are achieved

Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. A. Sánchez, Á. de Castro, V. M. López, F. J. Azcondo, J. Garrido, "Single ADC Digital PFC Controller Using Precalculated Duty Cycles", IEEE Transactions on Power Electronics, vol. 29, no. 2, pp. 996 - 1005, Feb 2014, Traditional digital power factor correction (PFC) uses three sensors to measure the input and output voltages and the input current. Each sensor, especially the input current one, increases the cost of the system and generates power losses in case of resistive sensors. This paper presents a controller for boost PFC converters. It uses precalculated duty cycles generated offline, and applies them to the switch. In order to control the converter with nonnominal conditions, just one analog-to-digital converter (ADC) is used, which measures the output voltage. Measuring the average and the ripple of the output voltage with this ADC, the controller takes compensation action for changes in the input voltage but also in the load of the converter. The average value is used to control the input voltage changes, while the ripple value is used to control load changes. These two loops present low frequency bandwidth, so the ADC and the whole system can be low cost. Finally, a comparator is used to detect the zero-crossing of the input voltage, so the precalculated values are synchronized with the ac mains. In this way, the converter only uses one ADC and one comparator, both with low bandwidth. Results show that high power factor and normative compliance are reached, even under nonnominal conditions.

This paper describes the results of an amplitude modulation experiment performed on a pulse-preionized transverse-flow transverse-discharge CO/sub 2/ laser. The amplitude modulation of the laser power was achieved by pulsewidth modulation of the discharge current using a switched-mode power supply. The causes of growth of discharge instability observed during the experiment with long excitation pulses are explained. The power control of the laser using this technique has been studied and this method is compared with the conventional method where the discharge current level is varied to achieve the laser-power control.

An S-band radar transmitter MMIC is reported containing a class-F power amplifier and a switched mode power supply. The integration of the power supply offers the possibility to optimize the power amplifier bias voltage for each individual device in a AESA antenna. This has several advantages such as amplitude tapering with preservation of efficiency, the reduction of spurious signals due to decoherence and the removal of single point of failure. © 2012 IEEE.

A highly integrated high-power transmitter has been designed in a high breakdown GaAs MMIC technology. The transmitter includes, on top of an S-Band 10 W class-F HPA, a DC/DC converter and its associated gate driver, the full voltage regulation control loop, which provides a significant step for phased array transmit chain miniaturization and transmit pulse flexibility. The complete transmitter chip is assembled in a standard QFN package. The DC/DC converter operates at a switching frequency around 100MHz with an efficiency of 82%, including the on-chip control circuits. The overall DC to RF efficiency of the integrated transmitter is 32%. © 2012 IEEE.

International audience; Dielectric barrier discharge (DBD) lamps, being capacitive loads, must be associated with bidirectional current sources for an appropriate control of the transferred power. Pulsed current source supplies, which are known to offer very interesting performances, require specific power switches that are able to manage bidirectional voltage and unidirectional current at much higher frequencies (several hundreds of kilohertz) than commercial thyristors. This paper proposes the detailed design of such a high-speed synthesized thyristor, using discrete components: a MOSFET in series with a high-voltage (HV) diode and a logic circuit that controls its gate. This switch is associated with an optimized self-powered driver, which is a very efficient solution to handle the perturbations associated with the HV and high-frequency operation. Experimental application of this device for DBD excimer lamp supply is proposed.

peer-reviewed Modern isolated switched mode power supplies (SMPSs) commonly utilise digital control methods over their classical analogue counterparts. These methods are now preferred for ease of programmability and implementation, scalability and they also accommodate advanced control techniques such as adaptive control. However in most digital implementations, inexpensive opto-couplers are still used to transmit analogue signals across the isolation barrier. It is well known that these types of opto-couplers suffer many drawbacks including variable gain due to ageing effects. The main research contribution in this thesis focuses on developing and implementing a full bi-directional digital data-link between both sides of the isolation barrier, i.e. all signals (feedback and auxiliary) are digitalised and transmitted as a single encoded data stream across the isolation barrier. A key advantage of this scheme is that only a single set of digital couplers is required to achieve bi-directional communication, when compared with its analogue counterpart which would require multiple opto-couplers. This proposed scheme is therefore a more cost-effective and efficient solution and does not suffer from performance degradation due to ageing effects. To reduce the size and improve power efficiency and loop response, switching frequencies are continually increasing. Higher switching frequencies reduce the transmission window and therefore the number of bits to be transmitted across the isolation barrier per switching cycle needs to be minimised. To achieve this objective for the bi-directional data-link proposed, a new state-dependent encoding scheme for the required analogue-to-digital converter (ADC) has been specifically designed. This state-dependent encoding scheme ensures a high resolution during the steady-state operation of the SMPS while still providing adequate accuracy during transients. Along with the state-dependent ADC, two digital pulse width modulators (DPWMs) for single- and multi-phase SMPSs have been designed for use with the proposed communication system. These DPWMs were implemented using field programmable gate arrays (FPGAs), but are also suitable for application specific integrated circuits (ASICs). The DPWM designs only require a small number of logic elements while achieving high speed and high resolution, temperature independence and good scalability. This has been achieved using a hybrid approach which uses a novel fine-resolution block along with a coarse resolution block. This approach takes advantage of digital clock manager (DCM) blocks available on most commercial FPGAs available today. Manual placing and routing techniques result in high linearity and monotonic behaviour. For test purposes, the bi-directional communication scheme has been implemented on FPGAs and verified using a custom-built SMPS board.

A highly integrated high-power transmitter has been designed in a high breakdown GaAs MMIC technology. The transmitter includes, on top of an S-Band 10 W class-F HPA, a DC/DC converter and its associated gate driver, the full voltage regulation control loop, which provides a significant step for phased array transmit chain miniaturization and transmit pulse flexibility. The complete transmitter chip is assembled in a standard QFN package. The DC/DC converter operates at a switching frequency around 100MHz with an efficiency of 82%, including the on-chip control circuits. The overall DC to RF efficiency of the integrated transmitter is 32%. © 2012 IEEE.

An S-band radar transmitter MMIC is reported containing a class-F power amplifier and a switched mode power supply. The integration of the power supply offers the possibility to optimize the power amplifier bias voltage for each individual device in a AESA antenna. This has several advantages such as amplitude tapering with preservation of efficiency, the reduction of spurious signals due to decoherence and the removal of single point of failure. © 2012 IEEE.

Switched-Capacitor Converters (SCC) suffer from a fundamental power loss deficiency which make their use in some applications prohibitive. The power loss is due to the inherent energy dissipation when SCC operate between or outside their output target voltages. This drawback was alleviated in this work by developing two new classes of SCC providing binary and arbitrary resolution of closely spaced target voltages. Special attention is paid to SCC topologies of binary resolution. Namely, SCC systems that can be configured to have a no-load output to input voltage ratio that is equal to any binary fraction for a given number of bits. To this end, we define a new number system and develop rules to translate these numbers into SCC hardware that follows the algebraic behavior. According to this approach, the flying capacitors are automatically kept charged to binary weighted voltages and consequently the resolution of the target voltages follows a binary number representation and can be made higher by increasing the number of capacitors (bits). The ability to increase the number of target voltages reduces the spacing between them and, consequently, increases the efficiency when the input varies over a large voltage range. The thesis presents the underlining theory of the binary SCC and its extension to the general radix case. Although the major application is in step-down SCC, a simple method to utilize these SCC for step-up conversion is also described, as well as a method to reduce the output voltage ripple. In addition, the generic and unified model is strictly applied to derive the SCC equivalent resistor, which is a measure of the power loss. The theoretical predictions are verified by simulation and experimental results.

International audience; A sliding mode control (SMC) algorithm dedicated to switching mode power supply (SMPS) is validated experimentally in a FPGA. A constant high switching frequency is obtained using an hybrid digital pulse width modulator (DPWM). The proposed SMC strategy cooperates with an off-chip ADC and the hybrid DPWM takes advantage of a digital clock manager (DCM) and a counter-comparator based DPWM with a Multi-stAage-noise-SHaping (MASH) ¿-¿ modulator. Experimental results verify closed-loop operation at switching frequency up to 4 MHz only limited by the discrete SMPS and its dynamic response less than 30 ¿s. Simulation results show that the complete digital controller chip in 0.35 ¿m CMOS process takes 0.72 mm2 of silicon area and the current consumption is roughly 100 ¿A/MHz for a dynamic response of 16 ¿s.

Operation of a S/C power system based on the SMP technique for Maximum Power Point Tracking management is the subject of the present work. Improvements both in transient behaviour and EMC are reported and experimental results are analysed with reference to specific design solutions. Particular design techniques are then presented, specifically developed to avoid that the increased circuit complexity could negatively affect the system reliability, especially in the cases where Commercial Off The Shelf components are used. Basically, the circuits for fundamental operation, designed on the basis of classical and very reliable schemes, are separated from those dedicated to the SMP control, based on digital integrated circuits, with an higher failure rate. Then, the interfaces between the two blocks are designed so that the SMP control circuit can only affect (positively) the system operation when it is correctly operating, while its interactions with the basic circuit are blocked if errors are detected.

Switched-mode power supplies in variable-frequency drives often combine good electrical efficiency with generous production of conducted emission. The common-mode (CM) current through the output-to-motor cablemay perturb nearby systems via cable-to-cable crosstalk. Parameters relevant for the coupling are the rise–fall times and amplitude of the output current and voltage, and types and lengths of the cables. Of the many techniques to reduce the crosstalk, we investigated a particular one: reduction of the CM current by the armor of the motor cable. The armor is intended for mechanical protection, but may also substantially reduce the crosstalk. In an actual installation, we measured the transient current through the three phase leads of a motor cable. The cable length was 85 m, and it was buried in wet soil for most of its length. We also measured the transfer impedance of the armor up to 10 MHz, and used this to calculate the overall CM current in a coupled cable model using assumed reasonable values for the cable and soil parameters.Measurements and model results agreed well on the amplitude of the dominant resonance at about 300 kHz. The ratio of the inside transients to CMcurrent was a factor of 20.

Differential-mode buck-boost inverters have merits such as reduced switch number, ability to provide voltages higher or lower than the input voltage magnitude, improved efficiency, reduced cost and size, and increased power density, especially in low-power applications. There are five buck-boost inverters that can provide flexible output voltage without the need of a large electrolytic input side capacitor, which degrades the reliability of inverters. The continuous input current of these inverters is appropriate for maximum power point tracking operation in photovoltaic and fuel cells applications. Three of the five inverters can be isolated with high-frequency-link transformers where the common-mode leakage current can be mitigated. However, the performance and control of such converters have not been discussed in detail. In this paper, the five possible single-stage three-phase differential-mode buck-boost inverters with continuous input current are investigated and compared in terms of total losses, maximum ripple current, total harmonic distortion, and device and passive element ratings. In addition, the possible methods are presented for eliminating the input third-order harmonic current, resulting from the stored energy in the passive elements, as well as the output second-order harmonic currents. The ability for isolating the input and output sides of the inverters with a small-high frequency transformers is discussed. A changeable-terminal 2.5-kW bidirectional inverter is used to validate the design flexibility of the inverter topologies, when digital signal processor-controlled. NPRP Grant NPRP 4-250-2-080 from the Qatar National Research Fund (a member of Qatar Foundation). Scopus

This paper describes the behaviour of fusing systems in the presence of both nonlinear single phase and three phase loads. Such loads, producing harmonic currents, yield high peak currents. Specifically, IT-equipment where the nonlinearity is caused by the bridge rectifier of the switching power supply and variable speed drives are considered. The paper presents the study of the influence of the waveform of the neutral conductor current on the behaviour of the fusing system. Using a programmable power source, an arbitrary voltage waveform is generated. Each phase is loaded by a variable number of resistors. For different set ups of the power source and load conditions, the phase currents are analysed using on-line monitoring. The ratio of the phase RMS to peak current on the behaviour of fusing systems is analysed.

This paper deals with the analysis of the effects of radio frequency conducted interfering signals (RFI) on integrated circuits (ICs). After reviewing the basic results of the susceptibility analysis of operational amplifiers and smart power integrated circuits, the behavior of several pin-to-pin compatible control ICs for PWM current-mode switching power supplies (SMPS) has been tested in the presence of both continuous wave interfering signals (CW) as well as of pulsed noise signals (underground condition). The tested ICs were selected between some common models available on the market. The variations of the primary functional parameters (inner voltage reference, switching frequency, etc.) are evaluated in different test conditions. The paper gives a comparative view of the results, focusing on the key macroscopic effects.

The improvements in modern circuit technology reduce system size, improve the efficiency and reduce the cost. Utilization of soft-switching resonant power converters give high density high effeciency power converters for narrow output voltage ranges. To overcome this a cascaded switched-capacitor dc-dc converter is used to implement a Universal Serial Bus Power Delivery compliant charger. The converter uses a custom designed application specific integrated circuit designed for switched-capacitor dc-dc converters and wide bandgap technology allowing high frequency, high power design. The converter achieves peak efficiencies up to 98 % at 60 W output power with a corresponding junction temperature of 50 ◦C. Worst case junction temperatures reach 64 ◦C and is viable for use in longterm battery charger systems. The cascaded power stages take up 14 mm × 22 mm.