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This work investigates the non-uniform doping effect on a junctionless (JL) FinFET 6T SRAM cell. Employing a Gaussian doping distribution across the fin region of JL FinFET structure improves the OFF-current and ON-current performance. This opens up an opportunity for better device/circuit co-design. The implementation of 6T SRAM cell with Gaussian doped JL FinFET (GD-JL FinFET) has been demonstrated in the present work. It shows 12.23 %, 4.62 %, and 4.4 % improvements in noise immunity during read, write and hold mode, respectively than uniformly doped JL SRAM cell. Additionally, the improvement in write/read access time has been observed. The impact of supply voltage reduction on SRAM performance metrics has also been investigated. Furthermore, the statistical variability analysis of GD-JL FinFET based SRAM cell has been demonstrated in this work.

In advanced technology nodes, SRAM cells, used in the aerospace industry, have become highly susceptible to soft-error. In this brief, a Soft-Error-Aware Read-Decoupled 14T (SAR14T) SRAM cell is proposed for aerospace applications. To assess the performance of the proposed cell, it is compared with other soft-error-aware SRAM cells, like WE-QUATRO, QUCCE12T, RHD12T, RSP14T and RHBD14T. Simulation results show that all the sensitive nodes of SAR14T can reattain their initial states after being impacted by soft-error. Furthermore, the cell is capable of recovering from multi-node upset induced at its internal node-pair. Due to the employment of the read-decoupling technique, SAR14T shows the highest read stability compared to its peers. The proposed cell also proves to be the superior SRAM in terms of write ability and write delay. All these improvements are accomplished at the expense of a slightly longer read delay.

In Static Random Access Memory (SRAM) that is most ubiquitous of portable devices, the power consumption is a major concern. The emerging nonvolatile device-based SRAM designs have shown reduced power consumption by enabling power down mode without the loss of data. This paper presents a novel nonvolatile SRAM cell that employs eight transistors and a single TiO2 memristor as a nonvolatile device. The proposed 8T1M has low write power consumption, low store/restore energy and does not require reset phase. The performance of the proposed cell is compared with existing 8 T nvSRAM cells to demonstrate its versatility over others. The proposed cell shows 99.7% and 47% reductions in write ‘0’ power consumption and store/restore energy, respectively, with respect to existing 8 T nvSRAM counterparts, while the corresponding improvement in write margins and average store/restore delay is 69% and 70%. The results at different power supply and technology nodes are also captured to validate the impeccable performance of the proposed cell.

The SRAM cells are used in many biomedical applications such as Pace makers,ECG devices,body area networks etc.,where power consumption will be the main constraint. The conventional 6T SRAM cell has reduced stability and more power consumption when technology is scaled resulting in supply voltage scaling, so other alternative SRAM cells from 7T to 12T have been proposed which can address these problems. Here a low power 7T SRAM cell is suggested which has low power consumption and condensed leakage currents and power dissipation. The projected design has a leakage power of 5.31nW and leakage current of 7.58nA which is 84.9 % less than the 7T SRAM cell without using the proposed leakage reduction technique and it is 22.4 % better than 6T SRAM and 22.1 % better than 8T SRAM cell when both use the same leakage reduction technique. The cell area of the 7T SRAM cell is 1.25µm2, 6T SRAM is 1.079µm2 and that of 8T SRAM is 1.28µm2all the results are simulated in cadence virtuoso using 18nm technology.

Purpose This work is proposed for low power energy-efficient applications like laptops, mobile phones, and palmtops. In this study, P-channel metal–oxide–semiconductor (PMOS)’s are used as access transistor in 7 transistors (7 T) Static Random Access Memory (SRAM) cell, and the theoretical Static Noise Margin (SNM) analysis for the proposed cell is also performed. A cell is designed using 7 T which consists of 4 PMOS and 3 NMOS. In this paper write and hold SNM is addressed and read SNM is also calculated for the proposed 7 T SRAM cell. Design/methodology/approach The authors have replaced N-channel metal–oxide–semiconductor (NMOS) access transistors with the PMOS access transistors, which results in proper data line recovery and provides the desired coupling. An error is likely to occur, if the read operation is performed too often probably by using the NMOS pass gate. It results in an improper recovery of the data line. Instead, by using PMOS as a pass gate, the time required for read operation can be brought down. As we know the mobility (µ) of the PMOS transistor is low, so the authors have used this property into the proposed design. When a low signal is applied to its control gate, the PMOS transistor come up with the desired coupling, when working as a pass gate. Findings Feedback switched transistor is used in the proposed circuit, which plays an important role in the write operation. This transistor is in OFF state and PMOS’s work as access transistor, when the proposed cell operating in read mode. This helps in the reduction of power. This work is simulated using UMC 40 nm technology node in the cadence virtuoso environment. The simulated result shows that, write power saving of 51.54% and 61.17%, hold power saving of 25.68% and 48.93% when compared with reported 7 T and 6 T, respectively. Originality/value The proposed 7 T SRAM cell provides proper data line recovery at a lower voltage when PMOS works as the access transistor. Power consumption is very less in this technique and it is best suitable for low power applications.

In this paper, we have investigated the stability and power consumption of an 8 transistor (8 T) carbon nanotube field-effect transistor (CNTFET) based static random-access memory (SRAM) cell. The power and noise performances of the proposed 8 T CNTFET SRAM cell are observed for write, hold and read operations. The power consumption and noise margin of the proposed 8 T CNTFET SRAM cell are compared with that of conventional 6 T and 8 T CNTFET SRAM cells. From the simulation results, it is noted that during the write, hold, and read operations, the proposed structure consumes less power than the conventional CNTFET SRAM cells. The proposed 8 T CNTFET SRAM cell provides greater write and hold modes stability than conventional CNTFET SRAM cells, which is measured by calculating static noise margin (SNM). The performance of CNTFET depends on several parameters like dielectric constant (Kox), oxide thickness (Hox), supply voltage, pitch value, and temperature. The effect of these parameters on the power and stability of the conventional and proposed CNTFET SRAM cells are observed. It is noted that the proposed 8 T CNTFET SRAM cell provides good stability during PVT variation and consumes less power than conventional 6 T and 8 T CNTFET SRAM cells. The performance metrics of the proposed 8 T CNTFET SRAM are observed for both pre-layout and post-layout simulations. All the simulations are performed using the Stanford University 32 nm CNTFET model with the HSPICE simulation tool.

Advent and rapid development of on-chip computation in applications based on internet of things has opened space for integration of human life processes with technology. Wireless sensor node is a crucial component of this integration and SRAM employed in these nodes is under renovation phase. In this work, a novel single ended, bit-line powered 10T static random-access memory cell is proposed which improves access time, dissipates low power and supports bit-interleaving. The performance metrics of proposed design are compared with conventional 6T (conv.6T), tunable 8T(TUA8T), transmission gate based 9T(TRD9T), PPN10T(P10T), Schmitt-trigger based 10T (STR10T), loop cutting 10T (LC10T), and data dependent 11T(DD11T) cell to affirm the novelty of observed results. The reduction of soft error in proposed 10T cell is indicated by 1.22 $$\times$$ /1.13 $$\times$$ /1.13 $$\times$$ /0.91 $$\times$$ /1.49 $$\times$$ /1.12 $$\times$$ improvement in critical charge in comparison to conv.6T/TUA8T/TRD9T/STR10T/P10T/LC10T cell respectively. The read and write delay of proposed cell is improved by 1.56 $$\times$$ /1.04 $$\times$$ //1.04 $$\times$$ /1.57 $$\times$$ /1.14 $$\times$$ /1.12 $$\times$$ /1.05 $$\times$$ and 3.29 $$\times$$ /2.29 $$\times$$ /2.49 $$\times$$ /7.94 $$\times$$ /7.15 $$\times$$ /3.38 $$\times$$ /2.32 $$\times$$ respectively compared to conv.6T/TUA8T/TRD9T/STR10T/P10T/DD11T/LC10T cell. Additionally, read and write static noise margin of proposed 10T cell is improved by 2.22 $$\times$$ /2.04 $$\times$$ /1 $$\times$$ /1.67 $$\times$$ /1.06 $$\times$$ /1.75 $$\times$$ /1 $$\times$$ and 1.18 $$\times$$ /1.22 $$\times$$ /0.89 $$\times$$ /0.93 $$\times$$ /1.23 $$\times$$ /1.33 $$\times$$ /0.98 $$\times$$ respectively in comparison to conv. 6T/TUA8T/TRD9T/STR10T/P10T/DD11T/ LC10T cell. This article further demonstrates 1.88 $$\times$$ and 1.26 $$\times$$ tighter disperse in read power variability and read current variability respectively as compared with that of conv. 6T SRAM cell. The reduced cell density due to more number of transistors is compensated by improved $$I_{on}$$ / $$I_{off}$$ ratio.

In space, due to high energy particles, which cause single event upsets (SEUs), the traditional 6T SRAM cell becomes more susceptible to soft-error. In order to address this, a radiation hardened memory-by-design 10T (RHMD10T) SRAM cell is proposed in this brief. The relative strength of RHMD10T is estimated by comparing it with other contemporary cells such as QUATRO10T, QUCCE10T, QUATRO12T, QUCCE12T, NS10T and PS10T over various major design metrics. RHMD10T exhibits $1.09\times / ~1.16\times / ~1.26\times $ shorter read delay than QUCCE10T/ QUATRO10T/ NS10T. RHMD10T has the highest read stability and can tolerate the highest amount of critical charge than all other comparison cells. RHMD10T consumes the lowest hold power than all other comparison cells, except NS10T. In addition, RHMD10T is the least susceptible to SEU, except QUCCE12T. All these aforementioned improvements of RHMD10T are obtained at a cost of slightly longer write delay and lower write ability.

To achieve improved speed of operation, a higher integration density and lower power dissipation, transistors are being scaled aggressively. This trend has reduced the critical charge of sensitive nodes. As a result, SRAM cells used in the high radiation environment of aerospace have become highly vulnerable to soft errors. In this paper, we propose a soft-error-aware 14T (SEA14T) SRAM cell for aerospace applications. The performance of the proposed cell is assessed by comparing it with other radiation-hardened SRAM cells like QUCCE12T, WE-QUATRO, RHM12T, RHD12T, RSP14T and RHBD14T. The proposed cell can fully recover from a single-event upset, of any strength and polarity, induced at all the sensitive nodes. Simulation results also show that SEA14T can fully recover from a multi-node upset induced at the internal node-pair. The proposed cell exhibits $1.06\times / 1.08\times / 1.36\times $ shorter read delay than QUCCE12T/ WE-QUATRO/ RHBD14T and $1.03\times / 1.09\times / 1.12\times / 1.15\times / 1.17\times $ shorter write delay than RHM12T/ WE-QUATRO/ QUCCE12T/ RSP14T/ RHD12T. It also shows $1.33\times / 1.6\times / 2.4\times $ higher read stability than QUCCE12T/ WE-QUATRO/ RHBD14T and $1.13\times / 1.32\times / 1.37\times / 1.42\times / 1.5\times $ higher write ability than RHM12T/ WE-QUATRO/ QUCCE12T/ RSP14T/ RHD12T. Furthermore, the proposed cell consumes $2.31\times / 2.42\times / 2.55\times / 3.04\times $ lower hold power than RHD12T/ RSP14T/ WE-QUATRO/ QUCCE12T @ ${V} _{\text {DD}}$ = 1 V. All these improvements are achieved at the cost of a slightly larger area overhead.

For high speed application the static random access memory is mostly demandable. Such kind of device should possess additive parameters that can withstand during transistor scaling process. Their exist static noise margin (SNM) which degrades the device performance of memory architectures, majorly observed at write and read operation create write noise margin (WNM) and read noise margin (RNM). In this paper we discuss about the basic design of 6 transistor SRAM (6T SRAM) using 180nm and 45nm CMOS technology in Cadence Virtuoso with write noise margin analysis. The propagation delay, power dissipation, WNM are measured for both the technologies and observed that WNM is relatively low in 45nm.

Advanced CMOS technology is highly susceptible to ageing effects such as negative bias temperature instability (NBTI) and process variability. This article focuses on investigating the ‘combined im...

This paper presents a single-ended 9T SRAM cell with data-aware write-word-line structure to improve write ability, and a positive feedback sense amplifier (SA) to solve sensing challenge at an ult...

In this paper, eight different SRAM cells are studied and evaluated with a 65nm CMOS technology. The cells were designed with radiation-hardening-by-design approaches including schematic and layout techniques. The eight types of cells were placed into eight pages of an SRAM test chip. The alpha and proton irradiation demonstrated that the Dual Interlocked Cell (DICE) has the best radiation-tolerant performance, but requires the largest area. The 6T and 11T cells designed with charge cancellation techniques can reduce soft errors up to 2-3 times with less area overhead. Several DICE variants were developed with reduced area overhead and showed SEU resilience performance equivalent to DICE. Simulation results are also presented in this paper to validate the findings.

This paper examines the factors that affect the static noise margin (SNM) of static random access memories which focus on optimizing read and write operation of 8T SRAM cell which is better than 6T SRAM cell using swing restoration for dual node voltage. New 8T SRAM technique on the circuit or architecture level is required. In this paper, comparative analysis of 6T and 8T SRAM cells with improved read and write margin is done for 130nm technology with cadence virtuoso schematics tool.

Static Random Access Memory (SRAM) is primarily used as a memory storage element, which is susceptible to radiation-induced Single Event Upsets (SEUs). Hence, a robust SRAM bit-cell design is primarily a difficult task to address the space radiation environment. Furthermore, as the transistor’s size moves into nanometer regimes, a new challenge like Single Event Multiple Effects (SEME’s) evolved in SRAMs. SEME’s make the design of SRAM a serious challenge. In this article, a novel Radiation Hardened By Design (RHBD) SRAM bit-cell is proposed based on the polarity upset mechanism of SEUs. This work shows that the proposed RHBD14T SRAM bit-cell is SEU immune and delivers higher SEME critical charge than state-of-the-art RHBD SRAM bit-cells. The Monte Carlo (MC) simulations further show that the proposed RHBD14T SRAM delivers the lower Probability of Failure when compared to reported RHBD SRAM cells. Consequently, the proposed bit cell’s sensitive area is 128% lower with respect to the recently reported state-of-the-art RHBD RSP14T SRAM bit-cells.

In the present era of diminishing technology nodes, stability and performance of SRAM cells deteriorate. To cope up with the above growing concerns, a new 11 T SRAM cell has been proposed which imp...

The need of genuine processors operation improvement cultivates the necessity for reliable, low power and fast memories. Several challenges follow this improvement at lower technology nodes. The impact of variability of process, temperature and voltage, on different performance parameters turns out to be most relevant issues in the nanometre SRAM design. The authors propose a 10T SRAM circuit that shows reduction in read power dissipation while maintaining fair performance and stability. Impression of process parameter variations on various design metrics such as read power, read current and data retention voltage of the proposed cell are presented and compared with already proposed SRAM cell. The projected topology offers differential read and single‐ended write operation. The read margin and write margin are enhanced by 8.69% and 16.85% respectively in comparison to standard 6T SRAM cell even when single‐ended write operation is performed. Furthermore, the read and write delay of projected topology improve by 1.78× and 2.326× in comparison with conventional 6T bit SRAM cell. In FF process corner, the proposed topology shows lowest data retention voltage (DRV) and minimum variation in DRV with temperature. Out of all considered topologies, the proposed circuit is optimized to minimum power delay product during read operation. Further, standby power and read power of proposed 10T cell is reduced by 34.65% and 2.03× in contrast to conventional 6T SRAM at 0.9 V supply voltage. Analysis of process variations tolerance read power and read current is also presented with 45 nm generic process design kit technology file using cadence virtuoso tool.

In this brief, we have explored the impact of negative and positive bias temperature instability (NBTI and PBTI) for both DL (dopingless) and conventional junctionless (JL) FET based SRAM cells under worst-case scenario (extreme asymmetry). Using device-circuit co-simulation approach, read stability and delay of high performance and high density SRAM cells have been investigated for temporal variability due to NBTI+PBTI and NBTI (alone) of time span 2000s. The read static noise margin of high density SRAM cell based on DL-JLFET has 11% reduction as compared to 33% for conventional JLFET under NBTI+PBTI. It is observed that the DL-JLFET experiences less and symmetric shift in VTH compared to conventional JLFET under NBTI and PBTI, hence, circuits based on DL-JLFET may be less sensitive to temporal variations.

Charge plasma based doping-less tunnel FETs (DLTFETs) are attracting attention for providing reduced leakage currents and high ION/IOFF ratio. In this work, a new GaAs based gate stack charge plasma doping-less tunnel FET (GaAs based GSDLTFET) has been proposed. The simulation results show that the proposed device gives higher ION/IOFF ratio in comparison to DLTFETs due to high mobility of the GaAs substrate. Various SRAM circuits have been designed and analyzed using DLTFET and GaAs based GSDLTFET viz. 6 T standard SRAM, 6 T TFET SRAM and 7 T TFET SRAM. The circuit analysis shows that SRAM cell designed using GaAs based GSDLTFET provides better noise margins in comparison to DLTFET based SRAMs due to high ION/IOFF ratio. Standby leakage power is also reduced in DLTFETs as compared to CMOS. Due to the enhanced noise margins and reduced leakage power our proposed GaAs based GSDLTFET can be used to design energy- efficient memory devices.

As the technology is scaled the power consumption increases significantly, because of which the battery life of portable devices is reduced. Due to high power density, the increased power consumption becomes an obstacle for scaling of devices. Power optimization is the most significantly visible in future portable IC’s. As per increasing need for a low power circuit, the reduction in leakage current becomes very important aspect while designing any IC. The leakage can be reduced by altering the threshold voltage. Further as the technology is scaled FinFET is the alternate for CMOS with increased control of gate over the channel. In this paper a FinFET based 7T SRAM cell is proposed which is faster in its operation and consumes less power. In order to further reduce the leakage power, FinFET based 7T SRAM cell is designed using self-controllable voltage level (SVL) techniques. In this paper, an 18 nm FinFET based SRAM cell is designed using SVL circuit to reduce the leakage current and power. The proposed design has the least leakage current of 16.56 nA and leakage power of 11.59 nW by using the combined technique of LSVL and USVL. All the circuit design and simulation have been done in Cadence Virtuoso using 18 nM FinFET technology.

Static Random-Access Memory cells with ultralow leakage and superior stability are the primary choice of embedded memories in contemporary smart devices. This paper presents a novel 8T SRAM cell with reduced leakage and improved stability. The proposed SRAM cell uses a stacking effect to reduce leakage and transmission gate as an access transistor to enhance stability. The performance of the proposed 8T SRAM cell with a stacked transistor has been analyzed based on the power consumption and static noise margin (RSNM, HSNM, and WSNM). The power consumption in the case of FinFET based 8T cell is found to be 572 pW at 22 nm technology node, which is reduced by a factor nearly as compared to that of CMOS based 8T cell. Further, in the case of FinFET based novel 8T SRAM cell at 22 nm technology node, the power consumption is found to be reduced by a factor of as compared to that of FinFET based conventional 6T SRAM cell. WSNM, HSNM, and RSNM of the 8T SRAM cell designed with FinFET logic are observed as 240 mV, 370 mV, and 120 mV respectively at 0.9 V supply voltage. When comparing with conventional 6T FinFET Cell, the proposed Cell shows 20%, 5.11%, and 7% improvement in WSNM, HSNM, and RSNM, respectively. The sensitivity of SNM with temperature variation is also analyzed and reported. Further, the results obtained confirm the robustness of the proposed SRAM cells as compared to several recent works.

In this letter, we propose a new design of an ultra-low-power and high performance six – transistor (6 T) static random access memory (SRAM) cell using graphene nanoribbon field-effect transistors ...

The main attention in the area of technology is given to the low power SRAM (Static random Access Memory).GaAs SRAM have been developed with great efforts which include its many advantages such as reduced power consumption and temperature tolerance. There are many limitations of conventional cell which are overcome by the design of new cell which is used to simulate SRAM. The structure of MESFET and the limitations are discussed in the paper. Further, a code in silvaco is run and simulated and the result analysis is done using tony plots.

This paper presents a low leakage power 10T single-ended SRAM cell in the sub-threshold region that improves read, write, and hold stability. While at low voltages, the write-ability is increased by temporarily floating the data node, the read stability of the cell is maintained approximately as equal as the hold state by separating the data-storage node from the read bit line by using only a single transistor. According to Simulations using HSPICE software in 10 nm FinFET technology, the read stability of the proposed cell is approximately 4.8× higher than the conventional 6T at 200 mV. Furthermore, the proposed cell is found to have the lowest static power dissipation, as it tends to be 4% lower than the standard six-transistor cell at this voltage. This study shows that the yield of the proposed cell is higher than 6σ in all operations, and supply voltages down to 200 mV.

SRAM cells are used in many applications such as micro and multi core processor. SRAM cell improves both read stability and write ability at low supply voltage. The objective is to reduce the power dissipation of a novel low power 12T SRAM cell. This method removes half-select issue in 6T and 9T SRAM cell. This work proposes new functional low-power designs of SRAM cells with 6T, 9T and 12 transistors which operate at only 0.4V power supply in sub-threshold operation at 45 nm technology. The leakage power consumption of the proposed SRAM cell is thereby reduced compared to that of the conventional six-transistor (6T) SRAM cell. 12T cell obtains low static power dissipation.

This study presents a negative bias temperature instability (NBTI) mitigation design technique for CMOS 6T-static random access memory (6T-SRAM) cells. The proposed approach is based on transistor sizing technique. It consists of sizing the nMOS access transistors of the cell to alleviate NBTI ageing occurring in its pMOS pull-up transistors threatening the cell stability. Once the access transistors are sized for a better hold static noise margin under NBTI, the other transistors of the 6T-SRAM cell could be properly sized for improved read stability and write-ability.

Biomedical applications such as body area networks (BANs) require the design of power-efficient SRAM cells for the extended battery lives of BAN sensor nodes. In this work, we have proposed a bit-interleaving supporting, robust, low-power single-ended 9T (SE9T) bitcell. Design metrics of our bitcell are compared with several bitcells such as the 7T, FD8T and SEDF9T cells for their comparative analysis. The proposed cell shows 2.87×/3.36× higher RSNM than that of 7T/FD8T and 1.05×/1.5×/7.0× higher WSNM than that of 7T/FD8T/SEDF9T, 1.15×/1.06× and 1.54×/1.38× lower distribution in TRA and IREAD, respectively, compared to 7T/FD8T. In addition, the proposed cell shows 1.15×/1.22× shorter TWA when compared to SEDF9T/7T. Furthermore, SE9T cell consumes 10.80×/17.81× lower write power than that of SEDF9T/FD8T and 1.52×/18.37× lower read power than that of 7T/FD8T. It also exhibits 1.04×/2.92× lower leakage power dissipation than that of FD8T/7T. All these developments are obtained at a cost of 2.5× longer TWA, 1.73×/1.73× longer TRA when compared to FD8T and 7T/FD8T, and 1.64×/1.06× higher write power/read power than 7T/SEDF9T @ VDD = 700 mV.

This paper examines the factors that affect the Static Noise Margin (SNM) of a Static Random Access memories which focus on optimizing Read and Write operation of 8T SRAM cell which is better than 6T SRAM cell Using Swing Restoration for Dual Node Voltage. The read and Write time and improve Stability. New 8T SRAM technique on the circuit or architecture level is required. In this paper Comparative Analysis of 6T and 8T SRAM Cells with Improved Read and Write Margin is done for 130 nm Technology with Cadence Virtuoso schematics Tool.

This paper proposes a new 8T nonvolatile SRAM (nvSRAM) cell employing ULP FinFETs and ferroelectric FinFETs to enable energy-efficient and low-latency store/recall operations. Different from other types of nvSRAM requiring additional circuitry or nonvolatile memories connected to a standard 6T SRAM cell to achieve nonvolatility, the proposed hybrid nvSRAM cell reduces the area penalty by embedding the nonvolatile ferroelectric FinFETs in a 6T SRAM cell without sacrificing the cell stability, read/write performance and power consumption.

In recent, the low-power and high- speed memory is required because of this extensive use in the electronic portable equipments. The power consumption and speed are the major factor for memory design techniques. This paper presents design of the proposed circuit, and the implementation for proposed 6T SRAM with a Transmission gate and supply-gated technology. In this paper the comparative analysis on different parameters of conventional 6T SRAM, existing 6T SRAM and the proposed 6T SRAM are performed. This new approach can reduce the total power and total delay compared to conventional and existing 6T SRAM. All the experimental works are done by Microwind and DSCH 2.7 version software tool.

Smaller, lighter, and cost-effective satellite design is a major field of research today. Since such satellites are equipped with limited resources, there is a huge demand for low-power cache memory capable of performing reliably even when subjected to harsh cosmic radiations. To address the same, we have proposed a reliable, power-efficient, half-select-free dynamic loop-cutting write assist 12T (DWA12T) cell. The DWA12T has been compared with other state-of-the-art designs, such as the fully differential 8T (FD8T), single-ended disturb free 9T (SEDF9T), bit-interleaving architecture-implementing 11T (BI11T), differential 12T (D12T), and self-refreshing logic-based 12T (WWL12T) cells to estimate their relative performance in terms of major design metrics under severe process, voltage, and temperature (PVT) variations. The proposed cell exhibits $1.65\times /3.03\times /1.08\times /1.38\times $ shorter write delay ( ${T} _{\text{WA}}$ ) and $3.81\times /1.20\times /1.90\times /2.13\times $ higher write ability [write margin (WM)] than that of SEDF9T/BI11T/D12T/WWL12T and $1.36\times /1.54\times /1.22\times $ shorter read delay ( ${T} _{\text{RA}}$ ) and $6.63\times $ higher read stability [read static noise margin (RSNM)] than that of SEDF9T/BI11T/D12T and FD8T, respectively. Moreover, it consumes $1.05\times /1.21\times /1.10\times /1.81\times $ lower static power ( ${H} _{\text{PWR}}$ ) than that of FD8T/SEDF9T/D12T/WWL12T while showing $3.44\times $ higher hold stability [hold static noise margin (HSNM)] when compared to BI11T. In addition, the DWA12T cell consumes $1.01\times /1.02\times /1.04\times $ smaller area than that of BI11T/D12T/WWL12T. Furthermore, DWA12T shows lower susceptibility to soft error when compared to FD8T. These improvements are achieved at the cost of $1.37\times /1.13\times $ penalty in ${T} _{\text{WA}}/{T} _{\text{RA}}$ and $6.23\times $ penalty in ${H} _{\text{PWR}}$ when compared to FD8T and BI11T, respectively, at ${V} _{\text{DD}} = \text{0.7}$ V.

for the future technologies in which the devices and circuits are integrating more, low power consuming devices are needed. Mostly the reduction of power dissipation work is concentrated on switching and leakage current. However sub threshold current is also a big factor which leads to power consumption especially for memories. In this paper, leakage power of SRAM memory cell is reduced by power gated sleepy stack structure which leads to lesser power dissipation. The power dissipation is reduced to 226 µW with proposed technique compared with power dissipation of conventional 6T SRAM cell which had 740 µW. With lesser power dissipation the circuit can have more battery backup and lesser heat emission

A Fully Differential Write Assist 10T (FDWA10T) SRAM cell has been proposed in this work. The various design metrics and their behavior under severe process variation have been analyzed in this paper and have been compared with other state-of-the-art designs - FD8T, SEDF9T, BI11T, WWL12T and D12T cells. The FDWA10T cell shows $$1.47\times/1.73\times/2.09\times$$ shorter $$\textit{T}_{\mathrm{RA}}$$ than that of D12T/BI11T/SEDF9T and $$1.20\times/1.59\times/1.86\times/4.33\times$$ shorter $$\textit{T}_{\mathrm{WA}}$$ than that of D12T/WWL12T/SEDF9T/BI11T. In addition, it shows $$1.05\times$$ narrower spread in $$\textit{T}_{\mathrm{RA}}$$ than that of BI11T and $$3.94\times$$ higher RSNM than that of FD8T. A $$4.10\times$$ improvement in WSNM is also observed when compared to SEDF9T/D12T/WWL12T. The FDWA10T cell also exhibits $$1.03\times /1.03\times /1.06\times /2.09\times$$ lower hold power ($$\textit{H}_{\mathrm{PWR}}$$) consumption than that of D12T/FD8T/SEDF9T/WWL12T and consumes $$1.14\times /1.26\times /1.23\times$$ lesser area when compared to BI11T/WWL12T/D12T. These improvements are obtained at the cost of $$1.50\times /2.42\times$$ longer $$\textit{T}_{\mathrm{RA}}$$/$$\textit{T}_{\mathrm{WA}}$$ than that of FD8T, $$6.4\times$$ higher $$\textit{H}_{\mathrm{PWR}}$$ dissipation than that of BI11T and $$1.10\times /1.15\times$$ higher area consumption than that of FD8T/SEDF9T.

There is an immense necessity of several kilo bytes of embedded memory for Biomedical systems which typically operate in the sub-threshold domain with perfect efficiency. SRAMs (Static Random Access Memory) dominates the total power consumption and the overall silicon area, as 70% of the die has been occupied by them. This brief proposes the design of a Transmission gate-based SRAM cell for Bio medical application eliminating the use of peripheral circuitry during the read operation. It commences the read operation directly with the help of Transmission gates with which the data stored in the storage nodes can be read, instead of using the precharge and sense amplifier circuits which suits better for the implantable devices. This topology offers smaller area, reduced delay, low power consumption as well as improved data stabilization in the read operation. The cell is implemented in 45nm CMOS technology operated at 0.45V.

An increasing demand of on-chip assessment of data in IoT-based devices requires the design of low power on board memory circuits. In this context, a novel 10 T SRAM cell with lower power consumption and improved stability has been design and simulated on 45-nm technology node with cadence virtuoso tool. The loop cutting technique is utilized to improve the stability and minimize the power dissipation of 10 T SRAM cell. It has been noticed that read power consumption is reduced by 11.4% in 10 T SRAM cell as of standard 6 T SRAM cell. The read/write stability is enhanced by 2.4 times/ 2.36 times in comparison with standard 6 T SRAM cell. It occurs because of read decoupled structure. However, the read delay in 10 T SRAM cell is increased by 1.31 times in comparison with six-transistor SRAM cell.

As technology advances, the need for SRAM cells that may be utilised in high-speed applications grows. SRAM cells' static noise margin (SNM) is one of the most important variables to consider when designing a memory cell, and it is the main predictor of SRAM cell speed. The static noise margin will have an impact on the read and write margins. When it comes to the SRAM Cell's stability, the SNM is very important. For high-speed SRAMs, read/write margin analysis is critical since it affects how much data can be read and written. The simulation was run using Mentor Graphics' IC Station, which utilised 350nm technology rather than 180nm technology.

Memories are one of the most important component in semiconductor integrated circuits. In recent years, faster memories with more data stability and lower power consumption emerge in different technologies. Among the types of memories, SRAM is one of the fastest which is generally used as high speed registers and caches. The stability, power consumption and speed of SRAM are current trending research fields. This work consists of 6T SRAM Cell modelled in 180nm and 90nm CMOS Technology and compared the average power and delay in different temperatures across these technologies. The entire work is simulated in Cadence.

In this paper, a 9T SRAM cell with low power (LP9T) and improved performance has been proposed. This cell is free from half-select issue and works with single-ended read and differential write operation in the sub-threshold region. To evaluate the relative performance, the obtained characteristics of LP9T SRAM cell are compared with other state-of-the-art designs at 45-nm technology node. The read and write power dissipation of LP9T SRAM cell is reduced by [Formula: see text] and [Formula: see text] as compared to Conv.6T SRAM cell. In proposed cell, leakage power is reduced by [Formula: see text], [Formula: see text], [Formula: see text], [Formula: see text], [Formula: see text] and [Formula: see text] as compared to conventional 6T (Conv.6T), low power (LP8T), transmission gate 8T(TG8T), transmission gate 9T (TG9T), Schmitt trigger 9T (ST9T), and positive feedback control 10T (PFC10T) SRAM cells. This reduction in leakage power is attributed to stacking effect. LP9T SRAM cell also exhibits significant improvement in read/write access time as compared to all considered cells. Also, the read and write energy of proposed cell is lowest among all considered cells. The LP9T SRAM cell has [Formula: see text] and [Formula: see text] higher read and write stability as compared to Conv.6T SRAM cell. Proposed SRAM cell has the highest value of ON to OFF current ratio ([Formula: see text]) which signifies the highest bit-cell density among all considered cells. The LP9T SRAM cell occupies [Formula: see text] large area as compared to Conv.6T SRAM cell. The overall quality of SRAM cell is calculated through the electrical quality metric (EQM). It is observed that LP9T SRAM cell has the highest value of EQM in comparison to considered cells at 0.3[Formula: see text]V supply voltage.

The SRAM cells are used in many applications where power consumption will be the main constraint. The Conventional 6T SRAM cell has reduced stability and more power consumption when technology is scaled resulting in supply voltage scaling, so other alternative SRAM cells from 7T to 12T have been proposed which can address these problems. Here a low power 7T SRAM cell is suggested which has low power consumption and condensed leakage currents and power dissipation. The projected design has a leakage power of 5.31nW and leakage current of 7.58nA which is 84.9% less than the 7T SRAM cell without using the proposed leakage reduction technique and it is 22.4% better than 6T SRAM and 22.1% better than 8T SRAM cell when both use the same leakage reduction technique. The cell area of the 7T SRAM cell is 1.25µM2, 6T SRAM is 1.079µM2 and that of 8T SRAM is 1.28µM2all the results are simulated in cadence virtuoso using 18nm technology.

The present day electronic gadgets have semiconductor memory devices to store data. The static random access memory (SRAM) is a volatile memory, often preferred over dynamic random access memory (DRAM) due to higher speed and lower power dissipation. However, at scaling down of technology node, the leakage current in SRAM often increases and degrades its performance. To address this, the voltage scaling is preferred which subsequently affects the stability and delay of SRAM. This paper therefore presents a negative bit-line (NBL) write assist circuit which is used for enhancing the write ability while a separate (isolated) read buffer circuit is used for improving the read stability. In addition to this, the proposed design uses a tail (stack) transistor to decrease the overall static power dissipation and also to maintain the hold stability. The comparison of the proposed design has been done with state-of-the-art work in terms of write static noise margin (WSNM), write delay, read static noise margin (RSNM) and other parameters. It has been observed that there is an improvement of 48%, 11%, 19% and 32.4% in WSNM while reduction of 33%, 39%, 48% and 22% in write delay as compared to the conventional 6T SRAM cell, NBL, [Formula: see text] collapse and 9T UV SRAM, respectively.

In proposed work, aspect ratio optimization of Conventional 6T SRAM cell transistors has been presented for improvement cell in stability using gpdk 90nm technology with Cadence virtuoso tool. Initially read and write stability has been investigated by varying cell ratio, pull-up ratio, temperature and supply voltage by using N-curve method. Optimized 6-T SRAM cell stability parameters for 1V supply voltage have been compared with NC-SRAM cell and 9T SRAM cell. A significant improvement of 33.15%, 78.14%, 21.63% and 61.82% is observed in static voltage noise margin(SVNM), static current noise margin(SINM), write trip voltage (WTV) and write trip current (WTI) metrics respectively as compared to NC-SRAM cell. Improvement in stability parameters is observed with rise in supply voltage whereas, with rise in temperature stability parameters deteriorates gradually.