A Low Leakage with Enhanced Write Margin 10T SRAM Cell for IoT Applications

An increasing demand of on-chip assessment of data in IoT-based devices requires the design of low power on board memory circuits. In this context, a novel 10 T SRAM cell with lower power consumption and improved stability has been design and simulated on 45-nm technology node with cadence virtuoso tool. The loop cutting technique is utilized to improve the stability and minimize the power dissipation of 10 T SRAM cell. It has been noticed that read power consumption is reduced by 11.4% in 10 T SRAM cell as of standard 6 T SRAM cell. The read/write stability is enhanced by 2.4 times/ 2.36 times in comparison with standard 6 T SRAM cell. It occurs because of read decoupled structure. However, the read delay in 10 T SRAM cell is increased by 1.31 times in comparison with six-transistor SRAM cell.