Search

The next generation enterprise Xeon server processor maximum configuration supports 18 dual-threaded 64 bit Haswell cores, 45 MB L3 cache, 4 DDR4–2133 MHz memory channels, 40 8 GT/s PCIe lanes, and 40 9.6 GT/s QPI lanes. The processor has 5.56 B transistors on a 31.9 mm $\,\times\,$ 20.8 mm die in Intel's Hi-K metal-gate tri-gate 22 nm CMOS technology with 11 metal layers and achieves up to 33% performance boost. The design supports a wide range of configurations including thermal design power ranging from 55 to 160 W and frequencies ranging from 1.6 to 3.7 GHz. Key architectural innovations include the addition of AVX2 technology, DDR4, and fully integrated voltage regulators (FIVR) that enable per core p-states and uncore frequency scaling.

The next-generation enterprise Xeon server processor maximum configuration supports 18 dual-threaded 64b Haswell cores [1], 45MB L3 cache, 4 DDR4-2133MHz memory channels, 40 8GT/s PCIe lanes, and 60 9.6GT/S QPI lanes. The processor has 5.56B transistors on a 31.9mm×20.8mm die in Intel's high-K metal-gate tri-gate 22nm CMOS technology [2] with 11 metal layers and achieves a 33% performance boost, on average, over previous generations [3]. Two additional metal layers enable area optimization and performance improvement. The design supports a wide range of configurations, including thermal design power ranging from 55 to 165W and frequencies ranging from 1.6 to 3.8GHz. Fig. 4.5.1 shows the processor block diagram of the 18 core die. The floorplan allows for core and cache communication via a ring interconnect, as well as the ability to deliver derivative designs with lower core counts. The 4th column in the 18-core die is removed to implement the 12 core chop, and the 3rd column is removed for an 8 core chop. Key architectural innovations include the addition of AVX2 technology, DDR4, and fully integrated voltage regulators (FIVR) [4] that enable per-core p-states and uncore frequency scaling.

In this paper we introduce a method for computing the Elmore delay of MOS circuits which relies on a model of the capacitance of MOS devices and a model of the Elmore delay of individual MOS devices. The resistance of a device is not explicitly modelled. The Elmore models are used to compute the Elmore delay and the 50% point delay of CMOS circuits in a static timing verifier. Elmore delays computed with. These models fall within 10% of SPICE and can be computed thousands of times faster than if computed using SPICE. These models were used to verify critical paths during the design of a 600 MHz microprocessor.