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The Xeon® Processor E5-2600 v3: a 22 nm 18-Core Product Family

Authors :
Nevine Nassif
Jason Crop
Brian Brock
Christopher J. Bostak
Jayen J. Desai
Dave Bradley
Arvind Raghavan
C. Houghton
Daniel W. Krueger
Olivier Franza
C. Morganti
Bill Bowhill
Sal Bhimji
B. Stackhouse
Mendoza Oscar
Zibing Yang
Matthew Becker
Source :
IEEE Journal of Solid-State Circuits. 51:92-104
Publication Year :
2016
Publisher :
Institute of Electrical and Electronics Engineers (IEEE), 2016.

Abstract

The next generation enterprise Xeon server processor maximum configuration supports 18 dual-threaded 64 bit Haswell cores, 45 MB L3 cache, 4 DDR4–2133 MHz memory channels, 40 8 GT/s PCIe lanes, and 40 9.6 GT/s QPI lanes. The processor has 5.56 B transistors on a 31.9 mm $\,\times\,$ 20.8 mm die in Intel's Hi-K metal-gate tri-gate 22 nm CMOS technology with 11 metal layers and achieves up to 33% performance boost. The design supports a wide range of configurations including thermal design power ranging from 55 to 160 W and frequencies ranging from 1.6 to 3.7 GHz. Key architectural innovations include the addition of AVX2 technology, DDR4, and fully integrated voltage regulators (FIVR) that enable per core p-states and uncore frequency scaling.

Details

ISSN :
1558173X and 00189200
Volume :
51
Database :
OpenAIRE
Journal :
IEEE Journal of Solid-State Circuits
Accession number :
edsair.doi...........e24b3135ebe4be2d20a49543de8b8287