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Silicon-on-insulator latch designs and layouts that are robust to multiple-node charge collection are introduced. A general Monte Carlo radiative energy deposition (MRED) approach is used to identify potential single-event susceptibilities associated with different layouts prior to fabrication. MRED is also applied to bound single-event testing responses of standard and dual interlocked cell latch designs. Heavy ion single-event testing results validate new latch designs and demonstrate bounds for standard latch layouts.

The effect of a linear accelerator’s (LINAC’s) microstructure (i.e., train of narrow pulses) on devices and the associated transient photocurrent models are investigated. The data indicate that the photocurrent response of Si-based RF bipolar junction transistors and RF p-i-n diodes is considerably higher when taking into account the microstructure effects. Similarly, the response of diamond, SiO2, and GaAs photoconductive detectors (standard radiation diagnostics) is higher when taking into account the microstructure. This has obvious hardness assurance implications when assessing the transient response of devices because the measured photocurrent and dose rate levels could be underestimated if microstructure effects are not captured. Indeed, the rate the energy is deposited in a material during the microstructure peaks is much higher than the filtered rate which is traditionally measured. In addition, photocurrent models developed with filtered LINAC data may be inherently inaccurate if a device is able to respond to the microstructure.

Total ionizing dose results are provided, showing the effects of different threshold adjust implant processes and irradiation bias conditions of 14-nm FinFETs. Minimal radiation-induced threshold voltage shift across a variety of transistor types is observed. Off-state leakage current of nMOSFET transistors exhibits a strong gate bias dependence, indicating electrostatic gate control of the sub-fin region and the corresponding parasitic conduction path are the largest concern for radiation hardness in FinFET technology. The high- $V_{\textit {th}}$ transistors exhibit the best irradiation performance across all bias conditions, showing a reasonably small change in off-state leakage current and $V_{\textit {th}}$ , while the low- $V_{\textit {th}}$ transistors exhibit a larger change in off-state leakage current. The “ worst-case” bias condition during irradiation for both pull-down and pass-gate nMOSFETs in static random access memory is determined to be the on-state ( $V_{\textit {gs}}=V_{\textit {dd}}$ ). We find the nMOSFET pull-down and pass-gate transistors of the SRAM bit-cell show less radiation-induced degradation due to transistor geometry and channel doping differences than the low- $V_{\textit {th}}$ transistor. Near-threshold operation is presented as a methodology for reducing radiation-induced increases in off-state device leakage current. In a 14-nm FinFET technology, the modeling indicates devices with high channel stop doping show the most robust response to TID allowing stable operation of ring oscillators and the SRAM bit-cell with minimal shift in critical operating characteristics.

We discuss upsets in erased floating gate cells, due to large threshold voltage shifts, using statistical distributions collected on a large number of memory cells. The spread in the neutral threshold voltage appears to be too low to quantitatively explain the experimental observations in terms of simple charge loss, at least in SLC devices. The possibility that memories exposed to high energy protons and heavy ions exhibit negative charge transfer between programmed and erased cells is investigated, although the analysis does not provide conclusive support to this hypothesis.

In this study, we present low-energy proton single-event upset (SEU) data on a 65 nm SOI SRAM whose substrate has been completely removed. Since the protons only had to penetrate a very thin buried oxide layer, these measurements were affected by far less energy loss, energy straggle, flux attrition, and angular scattering than previous datasets. The minimization of these common sources of experimental interference allows more direct interpretation of the data and deeper insight into SEU mechanisms. The results show a strong angular dependence, demonstrate that energy straggle, flux attrition, and angular scattering affect the measured SEU cross sections, and prove that proton direct ionization is the dominant mechanism for low-energy proton-induced SEUs in these circuits.

This conference presents the recipients of the Outstanding Conference Paper Award from the 2015 IEEE Nuclear and Space Radiation Effects Conference.

Low- and high-energy proton experimental data and error rate predictions are presented for many bulk Si and SOI circuits from the 20-90 nm technology nodes to quantify how much low-energy protons (LEPs) can contribute to the total on-orbit single-event upset (SEU) rate. Every effort was made to predict LEP error rates that are conservatively high; even secondary protons generated in the spacecraft shielding have been included in the analysis. Across all the environments and circuits investigated, and when operating within 10% of the nominal operating voltage, LEPs were found to increase the total SEU rate to up to 4.3 times as high as it would have been in the absence of LEPs. Therefore, the best approach to account for LEP effects may be to calculate the total error rate from high-energy protons and heavy ions, and then multiply it by a safety margin of 5. If that error rate can be tolerated then our findings suggest that it is justified to waive LEP tests in certain situations. Trends were observed in the LEP angular responses of the circuits tested. As a result, grazing angles were the worst case for the SOI circuits, whereas the worst-case angle was at or nearmore » normal incidence for the bulk circuits.« less

The recipients of the 2014 NSREC Outstanding Conference Paper Award are Nathaniel A. Dodds, James R. Schwank, Marty R. Shaneyfelt, Paul E. Dodd, Barney L. Doyle, Michael Trinczek, Ewart W. Blackmore, Kenneth P. Rodbell, Michael S. Gordon, Robert A. Reed, Jonathan A. Pellish, Kenneth A. LaBel, Paul W. Marshall, Scot E. Swanson, Gyorgy Vizkelethy, Stuart Van Deusen, Frederick W. Sexton, and M. John Martinez, for their paper entitled "Hardness Assurance for Proton Direct Ionization-Induced SEEs Using a High-Energy Proton Beam." For older CMOS technologies, protons could only cause single-event effects (SEEs) through nuclear interactions. Numerous recent studies on 90 nm and newer CMOS technologies have shown that protons can also cause SEEs through direct ionization. Furthermore, this paper develops and demonstrates an accurate and practical method for predicting the error rate caused by proton direct ionization (PDI).

The locations of conductive regions in TaO x memristors are spatially mapped using a microbeam and Nanoimplanter by rastering an ion beam across each device while monitoring its resistance. Microbeam irradiation with 800 keV Si ions revealed multiple sensitive regions along the edges of the bottom electrode. The rest of the active device area was found to be insensitive to the ion beam. Nanoimplanter irradiation with 200 keV Si ions demonstrated the ability to more accurately map the size of a sensitive area with a beam spot size of 40 nm by 40 nm. Isolated single spot sensitive regions and a larger sensitive region that extends approximately 300 nm were observed.

The low-energy proton energy spectra of all shielded space environments have the same shape. This shape is easily reproduced in the laboratory by degrading a high-energy proton beam, producing a high-fidelity test environment. We use this test environment to dramatically simplify rate prediction for proton direct ionization effects, allowing the work to be done at high-energy proton facilities, on encapsulated parts, without knowledge of the IC design, and with little or no computer simulations required. Proton direct ionization (PDI) is predicted to significantly contribute to the total error rate under the conditions investigated. Scaling effects are discussed using data from 65-nm, 45-nm, and 32-nm SOI SRAMs. These data also show that grazing-angle protons will dominate the PDI-induced error rate due to their higher effective LET, so PDI hardness assurance methods must account for angular effects to be conservative. As a result, we show that this angular dependence can be exploited to quickly assess whether an IC is susceptible to PDI.

This work presents experimental Single Event Gate Rupture (SEGR) data for Metal–Insulator–Semiconductor (MIS) devices, where the gate dielectrics are made of stacked SiO2–Si3N4 structures. A semi-empirical model for predicting the critical gate voltage in these structures under heavy-ion exposure is first proposed. Then interrelationship between SEGR cross- section and heavy-ion induced energy deposition probability in thin dielectric layers is discussed. Qualitative connection between the energy deposition in the dielectric and the SEGR is proposed. peerReviewed

The effects of radiation on memristors created using tantalum oxide and titanium oxide are compared. Both technologies show changes in resistance when exposed to 800 keV Ta ion irradiation at fluences above 1010 cm-2. TaOx memristors show a gradual reduction in resistance at high fluences whereas TiO2 memristors show gradual increases in resistance with inconsistent decreases. After irradiation TaOx devices remain fully functional and can even recover resistance with repeated switching. TiO2 devices are more variable and exhibit significant increases and decreases in resistance when switching after irradiation. Irradiation with 28 MeV Si ions causes both technologies to switch from the off-state to the on-state when ionizing doses on the order of 60 Mrad(Si) or greater (as calculated by SRIM) are reached without applying current or voltage to the part. Irradiation with 10 keV X-rays up to doses of 18 Mrad(Si) in a single step show little effect on either technology. TaOx and TiO2 memristors both show high tolerance for displacement damage and ionization damage and are promising candidates for future radiation-hardened non-volatile memory applications.

This document describes the radiation environments, physical mechanisms, and test philosophies that underpin radiation hardness assurance test methodologies. The natural space radiation environment is presented, including the contributions of both trapped and transient particles. The effects of shielding on radiation environments are briefly discussed. Laboratory radiation sources used to simulate radiation environments are covered, including how to choose appropriate sources to mimic environments of interest. The fundamental interactions of radiation with materials via direct and indirect ionization are summarized. Some general test considerations are covered, followed by in-depth discussions of physical mechanisms and issues for total dose and single-event effects testing. The purpose of this document is to describe why the test protocols we use are constructed the way they are. In other words, to answer the question: “Why do we test it that way”?

This document gives detailed test guidelines for single-event upset (SEU), single-event latchup (SEL), single-event burnout (SEB), and single-event gate rupture (SEGR) hardness assurance testing. It includes guidelines for both heavy-ion and proton environments. The guidelines are based on many years of testing at remote site facilities and our present understanding of the mechanisms for single-event effects.

Radiation-induced effects on the electrical characteristics of TaOx memristive (or redox) memory are experimentally assessed. 10 keV x-ray irradiation is observed to cause switching of the memristors from high to low resistance states, as well as functional failure due to cumulative dose. Gamma rays and 4.5 MeV energy protons are not observed to cause significant change in resistance state or device function at levels up to 2.5 Mrad(Si) and 5 Mrad(Si) protons, respectively. 105 MeV and 480 MeV protons cause switching of the memristors from high to low resistance states in some cases, but do not exhibit a consistent degradation. 800 keV silicon ions are observed to cause resistance degradation, with an inverse dependence of resistance on oxygen vacancy density. Variation between different devices appears to be a key factor in determining the electrical response resulting from irradiation. The proposed degradation mechanism likely involves the creation of oxygen vacancies, but a better fundamental understanding of switching is needed before a definitive understanding of radiation degradation can be achieved.

A methodology for power MOSFET radiation hardness assurance is proposed. It is based on the statistical analysis of destructive events, such as gate oxide rupture. Examples of failure rate calculations are performed.

Techniques for removing the back substrate of SOI devices are described for both packaged devices and devices at the die level. The use of these techniques for microbeam, heavy-ion, and laser testing are illustrated.

The potential for using the degraded beam of high-energy proton radiation sources for proton hardness assurance testing for ICs that are sensitive to proton direct ionization effects are explored. SRAMs were irradiated using high energy proton radiation sources (~67-70 MeV). The proton energy was degraded using plastic or Al degraders. Peaks in the SEU cross section due to direct ionization were observed. To best observe proton direct ionization effects, one needs to maximize the number of protons in the energy spectrum below the proton energy SEU threshold. SRIM simulations show that there is a tradeoff between increasing the fraction of protons in the energy spectrum with low energies by decreasing the peak energy and the reduction in the total number of protons as protons are stopped in the device as the proton energy is decreased. Two possible methods for increasing the number of low energy protons is to decrease the primary proton energy to reduce the amount of energy straggle and to place the degrader close to the DUT to minimize angular dispersion. These results suggest that high-energy proton radiation sources may be useful for identifying devices sensitive to proton direct ionization.

Single-event upsets are studied in digital logic cells in a radiation-hardened CMOS SOI technology. The sensitivity of SEU to different strike locations and hardening approaches is explored using broadbeam and focused beam experiments. Error distributions in chains of logic flip-flops are studied to determine the impact of various cell designs and hardening techniques on upset uniformity.

Radiation effects are presented for the first time for vertically integrated 3 × 64-kb SOI SRAM circuits fabricated using the 3D process developed at MIT Lincoln Laboratory. Three fully-fabricated 2D circuit wafers are stacked using standard CMOS fabrication techniques including thin-film planarization, layer alignment and oxide bonding. Micron-scale dense 3D vias are fabricated to interconnect circuits between tiers. Ionizing dose and single event effects are discussed for proton irradiation with energies between 4.8 and 500 MeV. Results are compared with 14-MeV neutron irradiation. Single event upset cross section, tier-to-tier and angular effects are discussed. The interaction of 500-MeV protons with tungsten interconnects is investigated using Monte-Carlo simulations. Results show no tier-to-tier effects and comparable radiation effects on 2D and 3D SRAMs. 3DIC technology should be a good candidate for fabricating circuits for space applications.

Neutron-induced charge collection data and computer simulations presented here show that the presence of high-Z materials, like tungsten, can increase the single event upset (SEU) and multiple cell upset (MCU)cross sections of high critical charge (Qcrit) devices exposed to the terrestrial neutron environment because of interactions with high energy ( >; 100 MeV) neutrons. Time-of-flight data and computer simulations presented here demonstrate that 14 MeV neutrons do not produce highly ionizing secondary particles. Thus, 14 MeV neutrons can only simulate the SEU response of 65 nm SRAM devices in the terrestrial neutron environment for devices with a Qcrit

The amounts of charge collection by single-photon absorption (SPA) and by two-photon absorption (TPA) laser testing techniques have been directly compared using specially made SOI diodes. For SPA measurements and some TPA measurements, the back substrates of the diodes were removed by etching with XeF2. With the back substrates removed, the amount of TPA induced charge collection can be correlated to the amount of SPA induced charge collection. There are significant differences, however, in the amount of TPA induced charge collection for diodes with and without substrates. For the SOI diodes of this study, this difference appears to arise from several contributions, including nonlinear-optical losses and distortions that occur as the pulse propagates through the substrate, as well as displacement currents that occur only when the back substrate is present. These results illustrate the complexity of interpreting TPA and SPA single-event upset measurements.

A 1 GeV/amu 56Fe ion beam allows for true 90° tilt irradiations of various microelectronic components and reveals relevant upset trends at the GCR flux energy peak. Three SRAMs and an SRAM-based FPGA evaluated at the NASA Space Radiation Effects Laboratory demonstrate that a 90° tilt irradiation yields a unique device response. These tilt angle effects need to be screened for, and if found, pursued with radiation transport simulations to quantify their impact on event rate calculations.

Advances in microelectronics performance and density continue to be fueled by the engine of Moore's law. Although lately this engine appears to be running out of steam, recent developments in advanced technologies have brought about a number of challenges and opportunities for their use in radiation environments. For example, while many advanced CMOS technologies have generally shown improving total dose tolerance, single-event effects continue to be a serious concern for highly scaled technologies. In this paper, we examine the impact of recent developments and the challenges they present to the radiation effects community. Topics covered include the impact of technology scaling on radiation response and technology challenges for both total dose and single-event effects. We include challenges for hardening and mitigation techniques at the nanometer scale. Recent developments leading to hardness assurance challenges are covered. Finally, we discuss future radiation effects challenges as the electronics industry looks beyond Moore's law to alternatives to traditional CMOS technologies.

The effects of moisture on radiation-induced charge buildup in the oxides of a 0.35 μm SOI technology are explored. Data show no observable effects of moisture-related aging on radiation hardness. These results are in contrast to those of previous work performed on bulk MOS technologies fabricated in the 1980s. The cause of these differences do not appear to be due to differences in final chip passivation layers. Instead, other processing variables (including the use of different implant materials and thicker overlayers) may account for these differences. In any case, the SOI technology results indicate that not all advanced technologies exposed to moisture are necessarily susceptible to significant long-term radiation-induced aging effects.

Direct charge collection measurements are presented, which prove that the presence of tungsten near sensitive volumes leads to extreme charge collection events through nuclear reactions. We demonstrate that, for a fixed incident particle linear energy transfer (LET), increasing particle energy beyond a certain point causes a decrease in nuclear reaction-induced charge collection. This suggests that a worst-case energy exists for single-event effect (SEE) susceptibility, which depends on the technology, device layout, and the incident ions' fixed LET value. A Monte Carlo approach for identifying the worst-case energy is applied to certain bulk-Si and silicon-on-insulator (SOI) technologies. Simulation results suggest that the decrease in charge collection beyond the worst-case energy occurs because the secondary particles produced from the high-energy nuclear reactions have less mass and higher energy and are therefore less ionizing than those produced by lower-energy reactions.

The feasibility of developing an embeddable silicon-on-insulator (SOI) buried oxide MOS dosimeter (RadFET) has been demonstrated. This dosimeter takes advantage of the inherent properties for radiation-induced charge buildup in the buried oxides of commercial SOI wafers. Discrete SOI buried oxide RadFETs and fully-functional read-out circuitry have been fabricated in Sandia's CMOS7 radiation-hardened SOI technology. Discrete RadFETs have been irradiated under various radiation conditions and subjected to post-irradiation anneals. Data show only a small dose rate dependence and less than a 10% annealing or fade of the dosimeters output characteristics when irradiated with all pins shorted. These results show less fade than dual-dielectric RadFETs irradiated under the same bias conditions and support the use of SOI buried oxide RadFETs for low dose rate applications. Read-out circuitry has also been designed and fabricated to monitor changes in the ?off? state leakage current induced by radiation-induced charge buildup in the buried oxide dosimeter. The analog-to-digital output from the read-out circuit changes linearly with the ?off? state leakage current. Preliminary radiation characterizations of the read-out circuitry show no spurious effects of radiation-induced charge buildup in the read-out circuitry on the dosimeter output. These results indicate it is feasible to develop an embeddable SOI buried oxide RadFET as an attractive choice for many low power, low dose rate applications requiring real-time knowledge of total ionizing dose radiation levels.

The heavy-ion induced electron/hole charge yield in silicon-oxide versus electric field is presented. The heavy-ion charge yield was determined by comparing the voltage shifts of MOSFET transistors irradiated with 10-keV X-rays and several different heavy ions. The obtained charge yield for the heavy ions is in average nearly an order of magnitude lower than for the X-rays for the entire range of measured electric fields.

Gate-all-around MOSFETs were fabricated from single-crystal silicon nanowires as small as 500 A? across. The response to x-rays was measured for transistors with various gate oxide thicknesses, a variety of physical designs, and several different electric fields during irradiation. While the devices are otherwise very well behaved, the total dose degradation is larger than expected and is attributable to thicker, non-uniform gate oxide grown on non-(100) Si surfaces of the nanowires.

The radiation response of lateral power MOSFETs in total dose and energetic particle environments is explored. Results indicate that lateral power MOSFETs can be quite susceptible to single-event burnout. Tradeoffs involved in developing radiation hardened lateral power MOSFETs for point-of-load applications are studied using experiments and device simulations. Both design and fabrication process techniques can be used to significantly improve the single-event effect performance of lateral power MOSFETs, but the trade space between electrical and radiation performance must be carefully considered to produce an optimized design for point-of-load applications.

Experimental results are presented on single-bit-upsets (SBU) and multiple-bit-upsets (MBU) on a 45 nm SOI SRAM. The accelerated testing results show the SBU-per-bit cross section is relatively constant with technology scaling but the MBU cross section is increasing. The MBU data show the importance of acquiring and analyzing the data with respect to the location of the multiple-bit upsets since the relative location of the cells is important in determining which MBU upsets can be corrected with error correcting code (ECC) circuits. For the SOI SRAMs, a large MBU orientation effect is observed with most of the MBU events occurring along the same SRAM bit-line; allowing ECC circuits to correct most of these MBU events.

We have exposed MOS gate and field oxide transistors to moisture treatments with all pins grounded for up to three weeks. Irradiated field oxide structures showed a significant decrease in low frequency noise with moisture treatment, due to the passivation of Si dangling bonds at or near the Si/SiO2 interface. With moisture exposure, pMOS gate oxide transistors showed significant increases in pre-irradiation 1/f noise and post-irradiation oxide- and interface-trap charge densities. The 1/f noise of nMOS gate oxide transistors shows much less sensitivity to moisture exposure than pMOS transistors, before and after irradiation. We attribute these differences in sensitivities to moisture treatment to the enhancement of water diffusion in SiO2 by B atoms in the oxides that overlie the source/drain junctions of the pMOS transistors, in contrast to the retardation of moisture diffusion by P atoms in the corresponding regions of the nMOS devices.

Experimental results are presented on proton induced single-event-upsets (SEU) on a 65 nm silicon-on-insulator (SOI) SRAM. The low energy proton SEU results are very different for the 65 nm SRAM as compared with SRAMs fabricated in previous technology generations. Specifically, no upset threshold is observed as the proton energy is decreased down to 1 MeV; and a sharp rise in the upset cross-section is observed below 1 MeV. The increase below 1 MeV is attributed to upsets caused by direct ionization from the low energy protons. The implications of the low energy proton upsets are discussed for space applications of 65 nm SRAMs; and the implications for radiation assurance testing are also discussed.

It is shown that protons and neutrons can induce enhanced degradation in power MOSFETs, including both trench and planar geometry devices. Specifically, large shifts in current-voltage characteristics can be observed at extremely low proton total dose levels (as low as ~ 2 rad(SiO2)). These shifts can induce significant increases in device ldquooffrdquo state leakage current. Neutron irradiations show similar degradation at equivalent fluence levels, even though neutrons do not deposit dose due to direct ionization. These data suggest that the mechanism responsible for the enhanced degradation is a microdose effect associated with secondary particles produced through nuclear interactions between protons and neutrons and the materials in integrated circuits. The secondary particles deposit enough charge in the gate oxide to induce a parasitic drain to source leakage path in the transistor. Although the results are demonstrated here for only trench and planar geometry power MOSFETs, microdose effects can impact the radiation response of other integrated circuit types. Hardness assurances issues implications are discussed.

The propagation of single event transients (SET) is measured and modeled in SOI and bulk inverter chains. The propagation-induced pulse broadening (PIPB) effect is shown to determine the SET pulse width measured at the output of long chains of inverters after irradiation. Initially, narrow transients, less than 200 ps at the struck inverter, are progressively broadened into the nanosecond range. PIPB is induced by dynamic floating body effects (also called history effects) in SOI and bulk transistors, which depend on the bias state of the transistors before irradiation. Implications for SET hardness assurance, circuit modelling and hardening are discussed. Floating body and PIPB effects are usually not taken into account in circuit models, which can lead to large underestimation of SET sensitivity when using simulation techniques like fault injection in complex circuits.

Bipolar test structures were irradiated and annealed with various combinations of molecular hydrogen gas ambients, bias, and thermal conditions. The results show that the buildup and annealing behavior of defects in bipolar base oxides depend strongly on hydrogen concentration. Differences observed in trapped oxide charge annealing rates suggest that the charged defects created in hydrogen-rich environments may be attributed to different types of positive charge in addition to trapped holes.

For the first time, NROM-style nonvolatile memory elements were fabricated in SOI and irradiated. Total dose characterizations of these transistors indicate that this new style of memory can be functional to at least 500 krad (SiO2).

Transistors and ICs built in several different captive and commercial facilities were exposed to moisture, irradiated, and annealed. The moisture exposures were performed using highly accelerated stress test (HAST) at 130degC and 85% relative humidity. Irradiation of n-channel transistors exposed to HAST followed by a long-term anneal resulted in some increase in interface-trap and oxide-trapped charge buildup. However, exposing p-channel transistors to HAST preirradiation resulted in extremely large and unexpected voltage shifts immediately following irradiation. They were observed for devices with either doped oxide or nitride final chip passivation. Because of this, nitride passivation may not be sufficient to prevent H2O from causing enhanced radiation-induced degradation over long time periods in some devices (e.g., commercial devices with nitride final chip passivation packaged in plastic packages). The smaller voltage shifts for the n-channel transistors may be related to the formation of phosphosilicate glass (PSG) overlying the sources and drains of the n-channel transistors impeding the diffusion of moisture to the gate oxides. It is shown that, the large radiation-induced voltage shifts for the p-channel transistors can lead to enhanced IC parametric degradation and functional failure at lower radiation levels. Large increases in radiation-induced field oxide leakage current were also observed for transistors exposed to HAST preirradiation. Transistors were also annealed (prior to irradiation) and irradiated in H2. Approximately the same level of radiation-induced degradation was observed for n- and p-channel transistors suggesting that the diffusion kinetics for H2 diffusion are considerably different than for H2O diffusion. These results raise the concern that exposure of devices to moisture or hydrogen can lead to long-term radiation-induced aging effects.

The radiation effects community has developed a number of hardness assurance test guidelines to assess and assure the radiation hardness of integrated circuits for use in space and/or high-energy particle accelerator applications. These include test guidelines for total dose hardness assurance qualification and single event effects (SEE) qualification. In this work, issues associated with these hardness assurance test guidelines are discussed. For total dose qualification, the main test methodologies used in the U.S. and Europe are reviewed and differences between the guidelines are discussed. In addition, some key issues that must be considered when performing total dose hardness assurance testing are addressed. Following these discussions we review some emerging issues relevant to SEE device qualification that are not covered in present SEE test guidelines. The hardness assurance implications of these issues are addressed.

The effect of high energy proton irradiation and angle of incidence on single-event latchup (SEL) hardness is investigated as a function of temperature and power supply voltage to determine worst-case hardness assurance test conditions for space environments. SRAMs from several vendors were characterized for single-event latchup SEL hardness at proton energies from 20 to 500 MeV at temperatures of 25 degC and 80 degC, and at both normal and grazing angles of incidence. For all SRAMs investigated, the largest SEL cross section is observed for irradiation with protons with energies larger than 200 MeV. In addition, it is shown that for proton with energies ges 400 MeV, there is not a significant increase in SEL cross section for grazing angles of incidence compared to normal incidence irradiation. Based on the results of several years of research, in addition to these new results, we propose a hardness assurance test procedure for qualifying parts for use in proton-rich space environments.

Experimental evidence and Monte-Carlo simulations for several technologies show that accurate SEE response predictions depend on a detailed description of the variability of radiation events (e.g., nuclear reactions), as opposed to the classical single-valued LET parameter. Rate predictions conducted with this simulation framework exhibit excellent agreement with the average observed SEU rate on NASA's MESSENGER mission to Mercury, while a prediction from the traditional IRPP method, which does not include the contribution from ion-ion reactions, falls well below the observed rate. While rate predictions depend on availability of technology information, the approach described here is sufficiently flexible that reasonably accurate results describing the response to irradiation can be obtained even in the absence of detailed information about the device geometry and fabrication process.

The generation and propagation of single event transients (SET) is measured and modeled in SOI inverter chains with different designs. SET propagation in inverter chains induces significant modifications of the transient width. In some cases, a "propagation-induced pulse broadening" (PIPB) effect is observed. Initially narrow transients, less than 200 ps at the struck node, are progressively broadened up to the nanosecond range, with the degree of broadening dependent on the transistor design and the length of propagation. The chain design (transistor size and load) is shown to have a major impact on the transient width modification.

International audience; Abstract—We characterized the responses of three erbium-doped fibers with slightly different concentrations of rare-earth ions (240–290 ppm) and Al2O3 (7–10 wt.%) during proton and gamma-ray exposures. We have simultaneously measured the radiation-induced attenuation (RIA) around the Er3+ ion pumping wavelength (980 nm) and the associated changes of the Er3+ emission around 1530 nm. The three erbium-doped fibers show similar radiation responses. All fibers exhibit RIA levels between 9 10-3 and 1.7 10-2 dB m-1 Gy-1 at 980 nm and between 4 10-3 and 1.1 10-2 dB m-1 Gy-1 at 1530 nm. Protons and gamma-rays lead to similar radiation damages, with small differences between the protons of different energies (50 MeV and 105 MeV). Furthermore, we have performed online measurements of the spectral dependence of RIA from 600 to 1600 nm and offline measurements from 1200 to 2400 nm. The three fibers exhibit the same spectral response. Losses decrease monotonically from the visible to the infrared part of the spectrum. We have performed spectral decomposition of these RIA curves with the help of absorption bands previously associated with radiation-induced point defects. Our analysis shows that the main part of the RIA (600–1700 nm) in erbium-doped glass can be explained by the generation of Al-related point defects. The other defects related to the germanium and phosphorus doping of the silica seem to have a lower contribution to the induced losses. The Er3+ ion properties seem to be mainly unaffected by proton exposure, suggesting a solvation shell around the Er3+ ion formed by Al2O3 species.

Large, unexpected shifts in the current-voltage (IV) characteristics of commercial power MOSFETs irradiated with heavy ions have been observed. The shifts can be more than sixty-five times larger than the shifts resulting from total dose irradiation with gamma rays or electrons, and are shown to strongly depend on both the irradiation bias and the ion linear energy transfer (LET). These large shifts are a significant concern for devices intended to operate in low power space applications because it is shown that they can lead to off-state leakage currents greater than 1 A. The data are consistent with the formation of parasitic transistors resulting from the microdose deposited in the gate oxides of these devices by the heavy ions. These results have significant implications for hardness assurance testing of MOS devices for use in space.

The impact of heavy ion energy on SEU and SEL in commercial and radiation-hardened CMOS SRAMs is explored. Provided the ion range is large enough for the ions to reach the sensitive device region, standard low-energy heavy ion testing is conservative with respect to high-energy heavy ions, at least for LETs above the threshold for direct ionization-induced upsets. However, below the threshold LET for direct ionization-induced effects we find some differences between low- and high-energy tests. These differences are attributed to the effects of nuclear reaction-induced secondary particles. Implications for hardness assurance testing and error rate calculations are discussed.

Transistors and ICs were irradiated at dose rates from 0.2 to 2times109 rad(SiO2)/s using a wide range of radiation sources. The mechanisms causing parametric IC failure varied with dose rate. At low dose rates from 0.2 to 100 rad(SiO2)/s, parametric IC failure in these devices was dominated by radiation-induced degradation of the gate oxide transistors. At dose rates from 1.8times103 to 106 rad(SiO2)/s, parametric IC degradation was dominated by large increases in radiation-induced parasitic field oxide leakage current. At very high dose rates of 2times109 rad(SiO2)/s, no parametric failure was observed due to debiasing effects caused by rail-span collapse. These differences in dose rate response can make hardness assurance testing for high dose rate environments very challenging. Simple ldquoovertestsrdquo at dose rates from 50 to 300 rad(SiO2)/s may greatly underestimate the radiation hardness of ICs in high dose rate environments. Because the failure mechanism may vary with dose rate, circuit design, and/or device technology, the best procedure for ensuring IC radiation hardness in greater than 300 rad(SiO2)/s environments is to use radiation sources that mimic the system environment.

We irradiated floating gate (FG) memories with nor and nand architecture by using different TID sources, including 2 MeV, 98 MeV, and 105 MeV protons, X-rays, and Upsi-rays. Two classes of phenomena are responsible for charge loss from programmed FGs: the first is charge generation, recombination, and transport in the dielectrics, while the second is the emission of electrons above the oxide band. Charge loss from programmed FGs irradiated with protons of different energy closely tracks results from Upsi-rays, whereas the use of X-rays results in dose enhancement effects.

The radiation hardness of nominally identical SRAM test chips fabricated in five commercial foundries is examined. Large variations in single-event latchup and total dose response are observed. The softest SRAMs fail functionally at ~200 krad(SiO2) and have a fairly large single-event latchup cross section. This is in contrast to the hardest foundry split which is nearly immune to single-event latchup at room temperature, and remains functional to a total dose of 400 krad(SiO 2). Three of the splits show a similar increase in radiation induced leakage current, which is dependent on both the characterization bias as well as the pattern written to the memory array. The other two splits show neither a pattern nor a bias dependence on the leakage current. Heavy-ion microbeam experiments confirm that the most latchup sensitive area of these SRAMs is the peripheral circuitry, not the memory array itself. Qualification and hardened-by-design integrated circuit implications are discussed

To explore the impact of temperature on the post-irradiation response of ICs, we characterized the temperature response of transistors, SRAMs, and a custom mixed-signal ASIC. Devices were irradiated at room temperature and electrically characterized post irradiation as a function of temperature. Devices exhibit significantly more parametric degradation when characterized at elevated temperatures. In addition to parametric degradation, it is demonstrated that post-irradiation elevated temperature characterization can also induce functional failures at significantly lower total dose levels than at room temperature. As a result, to ensure system functionality, it is essential that devices be characterized over the full system temperature range pre- and post-irradiation. Recommendations for incorporating temperature testing into a hardness assurance test method (i.e., Method 1019) are suggested. Methods for minimizing the detrimental effects of elevated temperature anneals on hardness assurance testing are also discussed

The effect of proton angle of incidence on proton-induced single-event latchup (SEL) is investigated in detail at room and elevated temperatures in present-day SRAMs. SRAMs from seven different vendors were irradiated at proton energies from 50 to 200 MeV, at temperatures of 25 degC and 75 degC, and at angles of incidence from 0deg (normal) to 85deg (grazing). The effects of angle of incidence were also investigated for neutron-induced SEL. The angle of incidence can significantly impact SEL hardness. For one SRAM at a temperature of 75 degC, characterizing SEL cross section at grazing angle resulted in a 16 times increase in SEL cross section. Large increases in SEL cross section with angle were also observed for other SRAMs characterized at room temperature. These increases in SEL cross section with angle of incidence are much larger than those measured previously for older SRAM technologies. The mechanism for the effect of angle of incidence on SEL cross section is not due simply to the deposition of more energy in the sensitive volume caused by an increase in path length as the angle of incidence is increased. To investigate possible mechanisms nuclear scattering calculations were performed and combined with device simulations. Simulation results suggest that the mechanism is a consequence of the linear energy transfer (LET) and range distributions of secondary ions produced by proton-material (or neutron-material) interactions coupled with an increase in SEL sensitivity (decrease in LET threshold) as angle of incidence is increased. These results have significant impact on SEL hardness assurance testing, especially for system applications where latchups cannot be tolerated. To best ensure that SEL hardness requirement are met, SRAMs should be characterized at both grazing and normal angles of incidence, and at maximum temperature, voltage, and proton energy